CN210721103U

CN210721103U - Circuit structure for realizing multi-path output control of single processor

Info

Publication number: CN210721103U
Application number: CN201922030801.3U
Authority: CN
Inventors: 刘阳; 李兴建
Original assignee: NR Electric Co Ltd; NR Engineering Co Ltd
Current assignee: NR Electric Co Ltd; NR Engineering Co Ltd
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2020-06-09
Anticipated expiration: 2029-11-21

Abstract

The utility model discloses a circuit structure for realizing multi-way output control of a single processor, wherein a control signal CS pin, an LE pin and a data signal PO pin of the processor are respectively connected with a plurality of latches through data buses; a plurality of CS pins of the processor are respectively connected with an OE pin of a corresponding latch enabling end, a plurality of LE pins of the processor are respectively connected with an LE pin of a corresponding latch latching control end, and a plurality of PO pins of the processor are respectively connected with an input end of each latch. The utility model discloses effectively solved and opened out the restriction that the output number received treater IO interface quantity, improved veneer card and opened out density, reduced and opened out the action time, satisfied and opened out the test occasion fast, reduced testing arrangement cost and volume.

Description

Circuit structure for realizing multi-path output control of single processor

Technical Field

The utility model relates to a circuit structure that uniprocessor realized multichannel and opened out control belongs to power equipment switch signal processing technology field.

Background

As more and more power equipment are arranged in the power system, the number of the input signals is increased; the number of the board cards and the number of the access cards in the corresponding control protection device are obviously increased, which requires more access signals to be configured in the production test device to meet the test requirements.

At present, a test uses an open signal mode to output a control signal for an IO interface of a processor, and the control signal controls an electromagnetic relay through a driving loop to complete the closing and opening of the open signal; therefore, the number of the output signals is limited by the number of IO interfaces of the processor, the output action time is greatly influenced by the action time of the electromagnetic relay, and the situations with more output quantity requirements and quick output are difficult to meet; in order to meet the requirement of developing a large number of occasions, the existing strategies mainly include increasing the number of expansion outgoing board cards, increasing the number of processors, increasing expansion FPGA chips and the like, and the method leads to the increase of the volume and the cost of the testing device.

SUMMERY OF THE UTILITY MODEL

The purpose is as follows: in order to overcome the problem that the current signals of opening into and out constantly increase, testing arrangement can't satisfy, the utility model provides a circuit structure that single processor realized control is opened out to multichannel.

The technical scheme is as follows: in order to solve the technical problem, the utility model discloses a technical scheme does:

a circuit arrangement for a single processor implementing multiple-way egress control, comprising: the system comprises a processor and latches, wherein a control signal CS pin, an LE pin and a data signal PO pin of the processor are respectively connected with a plurality of latches through data buses; a plurality of CS pins of the processor are respectively connected with an OE pin of a corresponding latch enabling end, a plurality of LE pins of the processor are respectively connected with an LE pin of a corresponding latch latching control end, and a plurality of PO pins of the processor are respectively connected with an input end of each latch.

Preferably, the method further comprises the following steps: and the output ends of the latches are connected with the output input end and the output input end.

Preferably, the processor adopts ADSP-BF537, and the latch adopts 74HC 573; the data signals PO1-P08 of the processor, eight signal pins are respectively connected with each latch D0-D7 and eight input end pins through a data bus; the control signals CS1-CS4 of the processor are that the four control pins are respectively connected with the OE pins of the enable ends of the four latches through data buses; the four control pins of the control signals LE1-LE4 of the processor are respectively connected with the pin of the latch control end LE of the four latches through a data bus.

Preferably, the output is an optocoupler relay.

Preferably, the optocoupler relay adopts AQW 214.

Preferably, the control signal of the processor is controlled in a time division multiplexing manner.

As a preferred scheme, the open output input end receives an open signal sent by an output end Q pin of the latch; and the output end of the output is connected with the input loop to be tested.

Has the advantages that: the utility model provides a pair of circuit structure of control is driven out to single processor realization multichannel has effectively solved the restriction that drives out output number and receive treater IO interface quantity, improves veneer card and drives out density, reduces and drives out the action time, satisfies to drive out the test occasion fast, reduces testing arrangement cost and volume. The method has the following advantages:

(1) the single processor outputs control signals for time division multiplexing, each latch is controlled to be in an output effective state or a high-resistance state through a latch chip selection signal, each latch is controlled to output and latch output signals through latch latching signals, and the output quantity is expanded.

(2) The chip selection signal and the latch signal can realize that each latch is controlled independently, and can also realize that a plurality of latches are controlled in groups to realize that a plurality of latches output signals in groups.

(3) The opening action time of the opening control is about 0.3ms, and compared with the action time of about 5ms of the traditional electromagnetic relay, the action speed is greatly improved.

Drawings

Fig. 1 is a schematic diagram of the circuit structure of the present invention;

FIG. 2 is a schematic diagram of connection between an out output and an in loop to be tested;

fig. 3 is a schematic view of the usage flow of the present invention.

Detailed Description

The present invention will be further described with reference to the accompanying drawings.

As shown in fig. 1, a circuit structure for implementing multi-way output control by a single processor includes a processor, a latch, and an output; a control signal CS pin, an LE pin and a data signal PO pin of the processor are respectively connected with a plurality of latches through data buses; the output ends of the latches are connected with the output end; a plurality of CS pins of the processor are respectively connected with an OE pin of a corresponding latch enabling end, a plurality of LE pins of the processor are respectively connected with an LE pin of a corresponding latch latching control end, and a plurality of PO pins of the processor are respectively connected with an input end of each latch.

The processor adopts ADSP-BF537, and the latch adopts 74HC 573; the data signals PO1-P08 of the processor, eight signal pins are respectively connected with each latch D0-D7 and eight input end pins through a data bus; the control signals CS1-CS4 of the processor are that the four control pins are respectively connected with the OE pins of the enable ends of the four latches through data buses; the four control pins of the control signals LE1-LE4 of the processor are respectively connected with the pin of the latch control end LE of the four latches through a data bus.

And the control signal of the processor is controlled in a time division multiplexing mode.

As shown in fig. 2, the output is set as an optocoupler relay, the optocoupler relay is AQW214, for example, an optocoupler relay U6 is used, and the input terminal pin 2 and the input terminal pin 4 are respectively connected with the output terminal Q0 pin and the Q1 pin of the latch U1, and the output action time is about 0.3 ms.

The open output input end receives an open signal sent by an output end Q pin of the latch; the output end of the output is connected with the open-in loop to be tested, so that the open-in loop is tested;

as shown in fig. 3, the embodiment:

the working process of a circuit structure for realizing multi-way output control by a single processor is concretely explained as follows:

1. the processor U5 controls the output of 8-way open signal PO1-PO8, 4-way latch chip select signal CS1-CS4, and 4-way latch signal LE1-LE 4.

2. When the chip select signal CS1 is active, latch U1 is in an output active state; when the latch signal LE1 is effective, the latch U1 latches and outputs BO1-BO8 according to the states of input signals PO1-PO8, and one open signal output process is completed; when the latch signal LE1 changes from active to inactive, the output BO1-BO8 of the latch U1 remains unchanged until the output signals BO1-BO8 are updated when the latch signal LE1 changes back to active;

when the chip select signal CS1 is inactive, latch U1 is in an output high impedance state, independent of latch signal LE 1;

3. when the chip select signal CS2 is active, latch U2 is in an output active state; when the latch signal LE2 is effective, the latch U2 latches and outputs BO9-BO16 according to the states of input signals PO1-PO8, and one open signal output process is completed; when the latch signal LE2 changes from active to inactive, the output BO9-BO16 of the latch U2 remains unchanged until the output signals BO9-BO16 are updated when the latch signal LE2 changes back to active;

when the chip select signal CS2 is inactive, latch U2 is in an output high impedance state, independent of latch signal LE 2;

4. when the chip select signal CS3 is active, latch U3 is in an output active state; when the latch signal LE3 is effective, the latch U3 latches and outputs BO17-BO24 according to the states of input signals PO1-PO8, and one open signal output process is completed; when the latch signal LE3 changes from active to inactive, the output BO17-BO24 of the latch U3 remains unchanged until the output signals BO17-BO24 are updated when the latch signal LE3 changes back to active;

when the chip select signal CS3 is inactive, latch U3 is in an output high impedance state, independent of latch signal LE 3;

5. when the chip select signal CS4 is active, latch U4 is in an output active state; when the latch signal LE4 is effective, the latch U4 latches and outputs BO25-BO32 according to the states of input signals PO1-PO8, and one open signal output process is completed; when the latch signal LE4 changes from active to inactive, the output BO25-BO32 of the latch U4 remains unchanged until the output signals BO25-BO32 are updated when the latch signal LE4 changes back to active;

when the chip select signal CS4 is inactive, latch U4 is in an output high impedance state, independent of latch signal LE 4;

6. when the chip selection signals CS1, CS2, CS3 and CS4 are time-sharing effective, the latches U1, U2, U3 and U4 are time-sharing effective in output; when the latch signals LE1, LE2, LE3 and LE4 are effective in time sharing, 4 groups of outputs BO1-BO8, BO9-BO16, BO17-BO24 and BO25-BO32 are latched and output in time sharing updating states; realizing 32-path open signal packet output; and (4) flexible configuration.

The above description is only a preferred embodiment of the present invention, and it should be noted that: for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A circuit arrangement for a single processor implementing multiple-way egress control, comprising: a processor, characterized in that: further comprising: the control signal CS pin, the LE pin and the data signal PO pin of the processor are respectively connected with the latches through data buses; a plurality of CS pins of the processor are respectively connected with an OE pin of a corresponding latch enabling end, a plurality of LE pins of the processor are respectively connected with an LE pin of a corresponding latch latching control end, and a plurality of PO pins of the processor are respectively connected with an input end of each latch.

2. The circuit structure of claim 1, wherein the single processor implements multiple-way egress control, comprising: further comprising: and the output ends of the latches are connected with the output input end and the output input end.

3. A circuit arrangement for implementing multiple-way-out control by a single processor as claimed in claim 1 or 2, wherein: the processor adopts ADSP-BF537, and the latch adopts 74HC 573; the data signals PO1-P08 of the processor, eight signal pins are respectively connected with each latch D0-D7 and eight input end pins through a data bus; the control signals CS1-CS4 of the processor are that the four control pins are respectively connected with the OE pins of the enable ends of the four latches through data buses; the four control pins of the control signals LE1-LE4 of the processor are respectively connected with the pin of the latch control end LE of the four latches through a data bus.

4. The circuit structure of claim 2, wherein the single processor implements multiple-way egress control, and further comprising: the output is set as an optocoupler relay.

5. The circuit structure of claim 4, wherein the single processor implements multiple-way egress control, and further comprising: the optocoupler relay adopts AQW 214.

6. A circuit arrangement for implementing multiple-way-out control by a single processor as claimed in claim 1 or 2, wherein: and the control signal of the processor is controlled in a time division multiplexing mode.

7. The circuit structure of claim 2, wherein the single processor implements multiple-way egress control, and further comprising: the open output input end receives an open signal sent by an output end Q pin of the latch; and the output end of the output is connected with the input loop to be tested.