CN114860630A - Digital processing circuit and signal processing method - Google Patents
Digital processing circuit and signal processing method Download PDFInfo
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- CN114860630A CN114860630A CN202210466630.2A CN202210466630A CN114860630A CN 114860630 A CN114860630 A CN 114860630A CN 202210466630 A CN202210466630 A CN 202210466630A CN 114860630 A CN114860630 A CN 114860630A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application provides a digital processing circuit and a signal processing method, and relates to the technical field of signal processing. The digital processing circuit includes: the digital control circuit comprises a digital processor and N1 output latches, wherein N2 data bus pins of the digital processor are respectively connected with N2 input pins of each output latch, N1 first input/output pins of the digital processor are also respectively connected with control pins of N1 latches, and N2 output pins of each output latch are used for respectively connecting with input ends of N2 devices to be controlled so as to perform signal control on N2 devices to be controlled; wherein N1 and N2 are both integers greater than or equal to 1. Therefore, one pin can control multiple signals through a conventional digital processor, so that the pin resource is saved, the cost of the digital processor is saved, and the number of data buses is saved.
Description
Technical Field
The present invention relates to the field of signal processing technologies, and in particular, to a digital processing circuit and a signal processing method.
Background
A Micro Control Unit (MCU), also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer (MCU), is a Chip-level computer formed by appropriately reducing the frequency and specification of a Central Processing Unit (CPU) and integrating peripheral interfaces such as a memory, a counter (Timer), a USB, an a/D converter, a UART, a PLC, a DMA, etc., and even an LCD driving circuit on a Single Chip, and performing different combination control for different applications.
Because the MCU has the advantages of programmability and low-cost devices, the MCU is widely applied to electronic equipment and digital power supply equipment. The MCU processes digital signals to realize signal control, and the digital signals are controlled and detected through pins of the MCU.
At present, because the resources of pins of an MCU (micro controller unit) and a DSP (Digital Signal Processing) chip at a low end are limited, one pin can only control or detect one Signal, which may result in an increase in control cost.
Disclosure of Invention
The present invention is directed to provide a digital processing circuit and a signal processing method to solve the problems of high control cost in the prior art.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in a first aspect, an embodiment of the present application provides a digital processing circuit, including: the digital control circuit comprises a digital processor and N1 output latches, wherein N2 data bus pins of the digital processor are respectively connected with N2 input pins of each output latch, N1 first input/output pins of the digital processor are also respectively connected with control pins of the N1 latches, and N2 output pins of each output latch are used for respectively connecting input ends of N2 devices to be controlled so as to perform signal control on the N2 devices to be controlled;
wherein N1 and N2 are both integers greater than or equal to 1.
Optionally, the digital processing circuit further comprises: n3 input latches, N3 second input and output pins of the digital processor are further respectively connected with control pins of the N3 input latches, N2 data bus pins of the digital processor are further respectively connected with N2 output pins of each input latch, and N2 input pins of each input latch are used for being respectively connected with output ends of N2 devices to be detected so as to detect signals of the N2 devices to be detected;
wherein N3 is an integer greater than or equal to 1.
Optionally, the first input/output pin and/or the second input/output pin is: a general purpose input output pin.
Optionally, the digital processor is a micro control unit or a digital signal processor.
In a second aspect, an embodiment of the present application provides a signal processing method for a digital processor in a digital processing circuit as set forth in any one of claims 1 to 4 above; the method comprises the following steps:
detecting an interrupt signal at a preset timing interval;
if the interrupt signal is detected, configuring N2 data bus pins of the digital processor as output pins;
assigning values to N2 data bus pins of the digital processor respectively, and performing signal control on corresponding equipment to be controlled through a first output latch of N1 output latches;
and assigning values to N2 data bus pins of the digital processor again, and performing signal control on corresponding equipment to be controlled through a second output latch of the N1 output latches until the number of controlled equipment reaches a preset control number threshold.
Optionally, the assigning N2 data bus pins of the digital processor, and performing signal control on the corresponding device to be controlled through a first output latch of the N1 output latches, includes:
assigning values to N2 data bus pins of the digital processor respectively to obtain N2 output data;
sending a first latch chip select signal to a control pin of the first output latch to cause the first output latch to latch the N2 output data;
and sending a first latch access de-chip selection signal to a control pin of the first output latch, so that the first output latch cancels the latch function, and respectively performing signal control on N2 devices to be controlled based on the N2 output data.
Optionally, the method further comprises:
and sending the first latch chip selection signal to a control pin of the first output latch, so that the first output latch only latches data and stops signal control on corresponding equipment to be controlled.
Optionally, before the sending the first latch chip selection signal to the control pin of the first output latch, the method further includes:
and after the first cancel latch chip selection signal is sent, the first latch chip selection signal is sent to a control pin of the first output latch after a first preset time is delayed, wherein the first preset time is longer than or equal to the preset transmission time of the digital processor and the output latch.
Optionally, if the digital processing circuit further includes: n3 input latches, after the number of controlled devices reaches the preset number threshold, the method further comprising:
configuring N2 data bus pins of the digital processor as input pins;
and sequentially carrying out signal detection on the corresponding equipment to be detected through the input latches in the N3 input latches until the number of the equipment to be detected reaches a preset detection number threshold.
Optionally, the signal detection of the corresponding device to be detected sequentially through the input latches of the N3 input latches includes:
sending a second latch chip selection signal to a control pin of a preset input latch of the N3 input latches, so that the preset input latch latches N2 input data received by the input pin;
and sending a second latch cancellation chip selection signal to a control pin of the preset input latch, so that the preset input latch cancels the latch function, and respectively carrying out signal detection on N2 devices to be detected based on the N2 input data.
Compared with the prior art, the method has the following beneficial effects:
the embodiment of the application provides a digital processing circuit and a signal processing method, wherein the digital processing circuit comprises: the digital control circuit comprises a digital processor and N1 output latches, wherein N2 data bus pins of the digital processor are respectively connected with N2 input pins of each output latch, N1 first input/output pins of the digital processor are also respectively connected with control pins of N1 latches, and N2 output pins of each output latch are used for respectively connecting with input ends of N2 devices to be controlled so as to perform signal control on N2 devices to be controlled; wherein N1 and N2 are both integers greater than or equal to 1. Therefore, one pin can control multiple signals through a conventional digital processor, so that the pin resource is saved, the cost of the digital processor is saved, and the number of data buses is saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a digital processing circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a latch according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another digital processing circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of a signal processing method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a signal control method according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart of another signal control method according to an embodiment of the present disclosure;
fig. 7 is a schematic flowchart of another signal processing method according to an embodiment of the present application;
fig. 8 is a schematic flowchart of another signal detection method according to an embodiment of the present application;
fig. 9 is a schematic diagram of a signal processing apparatus according to an embodiment of the present application;
fig. 10 is a schematic diagram of a digital processor according to an embodiment of the present application.
Icon: 100-digital processor, 200-output latch, 300-input latch, 901-detection module, 902-configuration module, 903-first control module, 904-second control module, 1001-processor, 1002-storage medium.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
In order to reduce the cost of signal processing, the present application provides a digital processing circuit and a signal processing method, and first, a digital processing circuit provided in an embodiment of the present application is explained by using specific examples.
Fig. 1 is a connection diagram of a digital processing circuit according to an embodiment of the present disclosure. As shown in fig. 1, the digital processing circuit includes: the digital processing unit 100, N1 output latches 200, N2 data bus pins of the digital processing unit 100 are respectively connected to N2 input pins of each output latch 200, N1 first input/output pins of the digital processing unit 100 are also respectively connected to control pins of N1 output latches 200, and N2 output pins of each output latch 200 are used for respectively connecting to input terminals of N2 devices to be controlled, so as to perform signal control on N2 devices to be controlled; wherein N1 and N2 are both integers greater than or equal to 1. Specifically, N1 and N2 may be determined based on the total number of pins of a digital processor, such as the digital processing circuit illustrated in fig. 1, which has 2 first input-output pins and 8 data bus pins.
In the operation of the digital processing circuit, N1 first input/output pins of the digital processor 100 are respectively connected to the control pins of N1 output latches 200, and the digital processor 100 controls the N1 output latches 200 through the first input/output pins.
On the basis of fig. 1, the embodiment of the present application further provides a latch. Fig. 2 is a schematic structural diagram of a latch according to an embodiment of the present application. As shown in fig. 2, the latch has 3 kinds of pins, which are an input pin, an output pin and a control pin, respectively, the input pin is used for receiving a digital signal sent by the digital processor, the output pin is used for outputting the signal sent by the digital processor to the control device, and the control pin is used for receiving a control signal sent by the digital processor to control the latch to latch/unlatch. When the digital signal of the control pin of the digital processor control latch is changed from 'canceling the latch chip selection signal' to 'latching the chip selection signal', the current input data of the input pin can be immediately latched to the latch and can not be output, and when the digital signal of the control pin is 'latching the chip selection signal', the data of the output pin is always kept unchanged and can not be changed along with the data of the input pin; when the digital signal of the control pin is changed into a 'cancel latch chip selection signal', the latch is canceled, and the digital signal of the output pin is changed along with the change of the digital signal of the input pin.
The digital processor 100 may in turn control each output latch 200 of the N1 output latches 200 into an "unlatched" state via the control pins of the N1 output latches 200. When the digital processor 100 controls one of the output latches 200 to enter the "latch canceling" state, the other output latches 200 are controlled to enter the "latch" state, and at this time, the digital processor 100 controls N2 data bus pins of the digital processor 100 to be connected with N2 input pins of the output latch 200 in the "latch canceling" state through N2 data bus lines, but not connected with the output latch 200 in the "latch" state, so as to control the device to be controlled connected with the output latch 200 in the "latch canceling" state. The digital processor 100 sequentially controls each output latch 200 to enter a "latch canceling" state, so as to sequentially control the devices to be controlled connected to each output latch 200.
In the digital processing circuit, a conventional digital processor can complete one pin to control multiple signals, so that the pin resource is saved, and the cost of the digital processor is saved. Meanwhile, the data buses in the connection mode can be recycled, only N2 data buses are needed, and the number of the data buses is saved.
In summary, an embodiment of the present application provides a digital processing circuit, which includes: the digital control circuit comprises a digital processor and N1 output latches, wherein N2 data bus pins of the digital processor are respectively connected with N2 input pins of each output latch, N1 first input/output pins of the digital processor are also respectively connected with control pins of N1 latches, and N2 output pins of each output latch are used for respectively connecting with input ends of N2 devices to be controlled so as to perform signal control on N2 devices to be controlled; wherein N1 and N2 are both integers greater than or equal to 1. Therefore, one pin can control multiple signals through a conventional digital processor, so that the pin resource is saved, the cost of the digital processor is saved, and the number of data buses is saved.
On the basis of fig. 1, another digital processing circuit is provided in the embodiments of the present application. Fig. 3 is a schematic structural diagram of another digital processing circuit according to an embodiment of the present disclosure.
As shown in fig. 3, the digital processing circuit further includes: n3 input latches 300, N3 second input/output pins of the digital processor 100 are further connected to control pins of the N3 input latches 300, N2 data bus pins of the digital processor 100 are further connected to N2 output pins of each input latch 300, and N2 input pins of each input latch 300 are used for being connected to output terminals of N2 devices to be detected, so as to detect signals of the N2 devices to be detected; wherein N3 is an integer greater than or equal to 1. Specifically, N1, N2, and N3 may be determined according to the total number of pins of the digital processor 100, such as the digital processing circuit illustrated in fig. 3, where the digital processor 100 has 2 first input and output pins, 1 first input and output pin, and 8 data bus pins.
In the operation of the digital processing circuit, N3 second input/output pins of the digital processor 100 are respectively connected to the control pins of N3 input latches 300, and the digital processor 100 controls the N3 input latches 300 through the second input/output pins. The structure of input latch 300 is the same as that of the latch shown in fig. 2.
The digital processor 100 may sequentially control each input latch 300 of the N3 input latches 300 into an "unlatched" state via the control pins of the N3 input latches 300. When the digital processor 100 controls one of the input latches 300 to enter the "latch canceling" state, the other input latches 300 are controlled to enter the "latch" state, and at this time, the digital processor 100 controls the N2 data bus pins of the digital processor 100 to be connected to the N2 input pins of the input latch 300 in the "latch canceling" state through the N2 data bus lines, instead of being connected to the input latch 300 in the "latch" state, so as to detect the device to be detected to which the input latch 300 in the "latch canceling" state is connected. The digital processor 100 sequentially controls each input latch 300 to enter a "latch cancellation" state, so as to sequentially detect the devices to be detected connected to each input latch 300. And the principle of controlling the device to be controlled by sequentially controlling the N1 output latches 200 described in the above embodiments is further implemented. The digital processor can complete signal control and detection on the equipment through the N1 output latches 200 and the N3 input latches 300 in sequence.
In the digital processing circuit, a conventional digital processor can complete the control of one pin and the detection of multiple signals, so that the pin resource is saved, and the cost of the digital processor is saved. Meanwhile, the data buses of the connection mode can be recycled, only N2 data buses are needed, and the number of the data buses is saved.
To sum up, another digital processing circuit provided in the embodiments of the present application further includes: n3 input latches, N3 second input and output pins of the digital processor are further respectively connected with control pins of the N3 input latches, N2 data bus pins of the digital processor are further respectively connected with N2 output pins of each input latch, and N2 input pins of each input latch are used for being respectively connected with output ends of N2 devices to be detected so as to detect signals of the N2 devices to be detected; wherein N3 is an integer greater than or equal to 1. Therefore, the control and detection of multiple signals by one pin can be completed by a conventional digital processor, so that the pin resource is saved, the cost of the digital processor is saved, and the number of data buses is saved.
With continued reference to fig. 1 and 3, the first input/output pin and/or the second input/output pin is: a general purpose input output pin. The digital processor is a micro control unit or a digital signal processor.
On the basis of fig. 1 to fig. 3, an embodiment of the present application further provides a signal processing method. Fig. 4 is a flowchart illustrating a signal processing method according to an embodiment of the present application, where the signal processing method is executed by a digital processor in any one of the digital processing circuits shown in fig. 1 to fig. 3. As shown in fig. 4, the method includes:
s101, detecting an interrupt signal at a preset timing interval.
A timer in the digital processor is timed out, and the digital processor can perform relevant control operation on the latch during the timed out period. Therefore, it is necessary to detect an interrupt signal. It is worth noting that the interrupt duration of the digital processor is determined by the time of production, e.g., 1 millisecond.
And S102, if the interrupt signal is detected, configuring N2 data bus pins of the digital processor as output pins.
When the interrupt signal is detected, it indicates that the digital processor can perform the control operation. When the digital processor is used to control a device to be controlled through N1 output latches, then N2 data bus pins of the digital processor are configured as output pins. And connecting the N2 data bus pins with the output latches corresponding to the device to be controlled through the data bus for data transmission. It should be noted here that each device to be controlled maintains a connection relationship with its corresponding output latch, and it is ensured that the device to be controlled can be controlled in real time through the output latch.
S103, assigning values to N2 data bus pins of the digital processor respectively, and performing signal control on corresponding equipment to be controlled through a first output latch in N1 output latches.
When the connection of N2 data bus pins of the digital processor with the first output latch through the data bus is successful. The digital processor assigns values to N2 data bus pins of the digital processor respectively, transmits the control signal to the first output latch through the data bus, and the first output latch transmits the control signal to the device to be controlled corresponding to the first output latch, so that the signal control of the corresponding device to be controlled is realized. For example, N2 data buses of the digital processor may control N2 devices to be controlled simultaneously.
And S104, assigning values to N2 data bus pins of the digital processor again, and performing signal control on corresponding equipment to be controlled through a second output latch of the N1 output latches until the number of the controlled equipment reaches a preset control number threshold.
And after the signal control of the device to be controlled corresponding to the first output latch is finished, connecting N2 data bus pins of the digital processor with the first output latch is canceled. The N2 data bus pins of the digital processor are then connected to the second output latch through the data bus. And the digital processor assigns the N2 data bus pins of the digital processor again, transmits the control signal to the second output latch through the data bus, and transmits the control signal to the equipment to be controlled corresponding to the second output latch through the second output latch, so that the signal control of the corresponding equipment to be controlled is realized.
The digital processor is sequentially connected with output latches connected with the equipment to be controlled in the N1 output latches, and finishes signal control on all the equipment to be controlled.
For example, N2 data bus pins of the digital processor can control N2 devices to be controlled simultaneously through the output latches, and N1 output latches, so that N2 data buses of the digital processor can control (N1 × N2) devices to be controlled at most through N1 output latches. A conventional digital processor can control a plurality of signals by one pin, so that pin resources are saved, and meanwhile, only N2 data buses are needed, so that the control cost is saved.
To sum up, the signal processing method provided in the embodiment of the present application detects an interrupt signal at a predetermined time interval; if the interrupt signal is detected, configuring N2 data bus pins of the digital processor as output pins; assigning values to N2 data bus pins of the digital processor respectively, and performing signal control on corresponding equipment to be controlled through a first output latch of N1 output latches; and assigning values to N2 data bus pins of the digital processor again, and performing signal control on the corresponding equipment to be controlled through a second output latch of the N1 output latches until the number of the controlled equipment reaches a preset control number threshold. Therefore, one pin can control multiple signals through a conventional digital processor, so that the pin resource is saved, the cost of the digital processor is saved, and the number of data buses is saved.
On the basis of the above fig. 4, the embodiment of the present application further provides a signal control method. Fig. 5 is a flowchart illustrating a signal control method according to an embodiment of the present application. As shown in fig. 5, in S103, N2 data bus pins of the digital processor are respectively assigned, and a first output latch of the N1 output latches is used to perform signal control on a corresponding device to be controlled, including:
s201, assigning values to N2 data bus pins of the digital processor respectively to obtain N2 output data.
And the digital processor assigns N2 data bus pins of the digital processor according to the control requirement to obtain N2 output data, wherein the output data comprise control signals.
S202, sending a first latch chip select signal to a control pin of the first output latch, so that the first output latch latches the N2 output data.
The first latch chip select signal is sent to the control pin of the first output latch, so that the first output latch latches the N2 output data, that is, the currently input data at the input pin is immediately latched to the latch and is not output. After the first latch chip selection signal is sent out and the first preset time is delayed, the next operation is carried out, the first preset time is longer than or equal to the preset transmission time of the digital processor and the output latch, the transmission and latching of N2 output data can be completed within the first preset time, and N2 output data are collected in the latch.
S203, sending a first latch access and chip removal selection signal to a control pin of the first output latch, so that the first output latch removes a latch function, and respectively carrying out signal control on N2 devices to be controlled based on N2 output data.
And after the first latch chip selection signal is sent out, a first latch access chip removal selection signal is sent to a control pin of the first output latch after delaying for a first preset time. At this point, N2 output data have completed being collected within the latch. And then sending a first latch access chip removal selection signal to a control pin of the first output latch so that the first output latch cancels the latch function, and the digital signal of the output pin of the first output latch changes along with the change of the digital signal of the input pin. And transmitting the N2 output data to N2 devices to be controlled, and respectively carrying out signal control on N2 devices to be controlled.
In summary, in the signal control method provided in the embodiment of the present application, N2 data bus pins of a digital processor are respectively assigned to obtain N2 output data; sending a first latch chip select signal to a control pin of the first output latch to cause the first output latch to latch the N2 output data; and sending a first latch access de-chip selection signal to a control pin of the first output latch so that the first output latch cancels the latch function, and respectively performing signal control on N2 devices to be controlled based on N2 output data. Therefore, signal control of the equipment to be controlled is completed in sequence, and pin cost and data bus cost are saved.
On the basis of the above fig. 5, the embodiment of the present application further provides another signal control method. Fig. 6 is a flowchart illustrating another signal control method according to an embodiment of the present application. As shown in fig. 6, the method further includes:
s204, sending a first latch chip selection signal to a control pin of the first output latch, so that the first output latch only latches data and stops signal control on corresponding equipment to be controlled.
When the signal control of the corresponding N2 devices to be controlled of the first output latch is completed. I.e. without the need for controlling the first output latch. And sending a first latch chip selection signal to a control pin of the first output latch, so that the first output latch only latches data and stops signal control on the corresponding equipment to be controlled.
On the basis of fig. 6, before sending the first latch chip select signal to the control pin of the first output latch in S204, so that the first output latch only latches data, the method further includes:
and after the first latch chip selection canceling signal is sent out, a first latch chip selection signal is sent to a control pin of the first output latch after the first preset time is delayed.
After the first cancel latch chip selection signal is sent out, the digital signal of the output pin of the first output latch changes along with the change of the digital signal of the input pin, that is, the first output latch outputs N2 output data, and the N2 output data are used for respectively carrying out signal control on N2 devices to be controlled. And N2 output data exist, and the data are transmitted from the first output latch to the equipment to be controlled and the control is completed, the data are not completed instantly, certain transmission and control time is needed, therefore, after the first preset time is needed to be delayed, the first latch chip selection signal is sent to the control pin of the first output latch after the transmission and the control of the N2 output data are completed. The first preset duration is greater than or equal to the preset transmission duration of the digital processor and the output latch.
On the basis of the above fig. 4, the embodiment of the present application further provides another signal processing method. Fig. 7 is a schematic flowchart of another signal processing method according to an embodiment of the present application. As shown in fig. 7, if the digital processing circuit further includes: n3 input latches, after the number of controlled devices reaches the preset number threshold, the method further comprises:
s301, configuring N2 data bus pins of the digital processor as input pins.
The digital processor may be connected to the input latch for detecting the device to be tested in addition to the output latch for controlling the device to be controlled. When the digital processor is used to detect devices under test through N3 input latches, then N2 data bus pins of the digital processor are configured as output pins. And connecting the N2 data bus pins with the corresponding input latches of the equipment to be detected through the data bus for data transmission. It should be noted here that each device under test is connected to its corresponding input latch, so as to ensure that the device under test can be detected in real time through the input latch.
S302, signal detection is performed on the corresponding equipment to be detected through the input latches of the N3 input latches in sequence until the number of the equipment to be detected reaches a preset detection number threshold.
When N2 data bus pins of the digital processor are successfully connected with the input latch through the data bus. The signal to be detected is transmitted to the input latch by the equipment to be detected, and then the signal to be detected is transmitted to the digital processor by the input latch, so that the corresponding equipment to be detected is subjected to signal detection. For example, the N2 data buses of the digital processor can simultaneously detect N2 devices under test.
And after the signal control of the equipment to be detected corresponding to the first input latch is finished, connecting N2 data bus pins of the digital processor with the first input latch is canceled. The N2 data bus pins of the digital processor are then connected to the second input latch through the data bus. And the digital processor realizes signal detection on the corresponding equipment to be detected through the second input latch again.
And the digital processor is sequentially connected with the input latches connected with the equipment to be detected in the N3 input latches, so that signal detection of all the equipment to be detected is completed.
For example, N2 data bus pins of the digital processor can simultaneously detect N2 devices under test through the input latches, and N3 input latches, the N2 data buses of the digital processor can detect (N3 × N2) devices under test through N3 input latches at most. The conventional digital processor can complete one pin to detect multiple signals, so that the pin resource is saved, and meanwhile, only N2 data buses are needed, so that the detection cost is saved.
In summary, in another signal processing method provided by the embodiments of the present application, N2 data bus pins of a digital processor are configured as input pins; and sequentially carrying out signal detection on the corresponding equipment to be detected through the input latches in the N3 input latches until the number of the equipment to be detected reaches a preset detection number threshold. Therefore, the conventional digital processor can complete one pin to detect multiple signals, so that the pin resource is saved, and meanwhile, only N2 data buses are needed, so that the detection cost is saved.
On the basis of the above fig. 7, the embodiment of the present application further provides another signal detection method. Fig. 8 is a schematic flowchart of another signal detection method according to an embodiment of the present application. In S302, signal detection is performed on the corresponding device to be detected sequentially through the input latches of the N3 output latches, including:
s401, sending a second latch chip selection signal to a control pin of a preset input latch in the N3 input latches, so that the preset input latch latches N2 input data received by the input pin.
The second latch chip select signal is sent to the control pin of the input latch, so that the input latch latches the N2 input data, that is, the currently input data at the input pin is immediately latched to the latch and is not output. After the second latch chip selection signal is sent out and the second preset time is delayed, the next operation is carried out, the second preset time is longer than or equal to the preset transmission time of the digital processor and the input latch, the transmission and latching of N2 input data can be completed within the second preset time, and N2 output data are collected in the latch.
S402, sending a second latch cancellation chip selection signal to a control pin of the preset input latch, so that the preset input latch cancels the latch function, and performing signal detection on N2 devices to be detected respectively based on N2 input data.
And after the second latch chip selection signal is sent out, a second latch chip selection cancellation signal is sent to the control pin of the input latch after delaying for a second preset time. At this point, N2 input data have completed being collected within the latch. And sending a second latch cancellation chip selection signal to the control pin of the input latch so that the input latch cancels the latch function, and the digital signal of the output pin of the input latch changes along with the change of the digital signal of the input pin. And transmitting the N2 input data to a digital processor, and respectively carrying out signal detection on N2 devices to be detected.
After the second cancel latch chip selection signal is sent out, the digital signal of the output pin of the first input latch changes along with the change of the digital signal of the input pin, namely the first input latch outputs N2 input data, and the N2 input data are used for respectively carrying out signal detection on N2 devices to be detected. And N2 input data are provided, and the data are transmitted from the first input latch to the digital processor and the detection is completed, but the data are not completed instantly, and certain transmission and detection time is needed, so after the second preset time is needed to be delayed, the second latch chip selection signal is sent to the control pin of the first input latch after the transmission of the N2 input data is completed and the detection is completed. And the second preset duration is greater than or equal to the preset transmission duration of the digital processor and the input latch.
When the signal detection of the N2 devices to be detected corresponding to the first input latch is completed. I.e. without the need for controlling the first input latch. And sending a second latch chip selection signal to a control pin of the first input latch, so that the first input latch only latches data and stops signal detection on the corresponding device to be detected.
In summary, in another signal detection method provided in the embodiment of the present application, a second latch chip selection signal is sent to a control pin of a preset input latch of N3 input latches, so that the preset input latch latches N2 input data received by the input pin; and sending a second latch canceling chip selection signal to a control pin of the preset input latch, so that the preset input latch cancels the latch function, and respectively carries out signal detection on the N2 devices to be detected based on the N2 input data. Therefore, signal detection of the equipment to be detected is completed in sequence, and pin cost and data bus cost are saved.
The following describes a signal processing apparatus, a digital processor, a storage medium, and the like for implementing the present application, and specific implementation procedures and technical effects thereof are referred to above, and will not be described again below.
Fig. 9 is a schematic diagram of a signal processing apparatus according to an embodiment of the present disclosure, and as shown in fig. 9, the signal processing apparatus may include:
a detecting module 901, configured to detect an interrupt signal at a preset time interval;
a configuration module 902, configured to configure N2 data bus pins of the digital processor as output pins if the interrupt signal is detected;
the first control module 903 is configured to assign values to N2 data bus pins of the digital processor, and perform signal control on a corresponding device to be controlled through a first output latch of the N1 output latches;
and the second control module 904 is configured to re-assign values to N2 data bus pins of the digital processor, and perform signal control on the corresponding device to be controlled through a second output latch of the N1 output latches until the number of controlled devices reaches a preset control number threshold.
Further, the first control module 903 is specifically configured to assign values to N2 data bus pins of the digital processor, respectively, to obtain N2 output data; sending a first latch chip select signal to a control pin of the first output latch to cause the first output latch to latch the N2 output data; and sending a first latch access de-chip selection signal to a control pin of the first output latch so that the first output latch cancels the latch function, and respectively performing signal control on N2 devices to be controlled based on N2 output data.
Further, the first control module 903 is specifically configured to send a first latch chip selection signal to a control pin of the first output latch, so that the first output latch only performs data latch and stops performing signal control on the corresponding device to be controlled.
Further, the first control module 903 is specifically configured to send the first latch chip selection signal to the control pin of the first output latch after the first latch chip selection cancellation signal is sent and a first preset time is delayed, where the first preset time is greater than or equal to a preset transmission time of the digital processor and the output latch.
Further, the second control module 904 is specifically configured to configure N2 data bus pins of the digital processor as input pins; and sequentially carrying out signal detection on the corresponding equipment to be detected through the input latches in the N3 input latches until the number of the equipment to be detected reaches a preset detection number threshold.
Further, the second control module 904 is specifically configured to send a second latch chip selection signal to a control pin of a preset input latch of the N3 input latches, so that the preset input latch latches the N2 input data received by the input pin; and sending a second latch canceling chip selection signal to a control pin of the preset input latch, so that the preset input latch cancels the latch function, and respectively carries out signal detection on the N2 devices to be detected based on the N2 input data.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 10 is a schematic diagram of a digital processor according to an embodiment of the present application, where the digital processor may be an apparatus with a computing processing function.
The digital processor includes: a processor 1001, and a storage medium 1002. The processor 1001 and the storage medium 1002 are connected by a bus.
The storage medium 1002 is used for storing a program, and the processor 1001 calls the program stored in the storage medium 1002 to execute the above-described method embodiment. The specific implementation and technical effects are similar, and are not described herein again.
Optionally, the invention also provides a program product, for example a computer-readable storage medium, comprising a program which, when being executed by a processor, is adapted to carry out the above-mentioned method embodiments.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer-readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Claims (10)
1. A digital processing circuit, comprising: the digital control circuit comprises a digital processor and N1 output latches, wherein N2 data bus pins of the digital processor are respectively connected with N2 input pins of each output latch, N1 first input/output pins of the digital processor are also respectively connected with control pins of the N1 latches, and N2 output pins of each output latch are used for respectively connecting input ends of N2 devices to be controlled so as to perform signal control on the N2 devices to be controlled;
wherein N1 and N2 are both integers greater than or equal to 1.
2. The circuit of claim 1, wherein the digital processing circuit further comprises: n3 input latches, N3 second input and output pins of the digital processor are further respectively connected with control pins of the N3 input latches, N2 data bus pins of the digital processor are further respectively connected with N2 output pins of each input latch, and N2 input pins of each input latch are used for being respectively connected with output ends of N2 devices to be detected so as to detect signals of the N2 devices to be detected;
wherein N3 is an integer greater than or equal to 1.
3. The circuit of claim 2, wherein the first input-output pin and/or the second input-output pin is: a general purpose input output pin.
4. A circuit according to claims 1-3, wherein the digital processor is a micro control unit or a digital signal processor.
5. A signal processing method, for use in a digital processor in a digital processing circuit as claimed in any one of claims 1 to 4; the method comprises the following steps:
detecting an interrupt signal at a preset timing interval;
if the interrupt signal is detected, configuring N2 data bus pins of the digital processor as output pins;
assigning values to N2 data bus pins of the digital processor respectively, and performing signal control on corresponding equipment to be controlled through a first output latch of N1 output latches;
and assigning values to N2 data bus pins of the digital processor again, and performing signal control on corresponding equipment to be controlled through a second output latch of the N1 output latches until the number of controlled equipment reaches a preset control number threshold.
6. The method of claim 5, wherein assigning values to N2 data bus pins of the digital processor and controlling signals to the corresponding device to be controlled via a first output latch of N1 output latches comprises:
assigning values to N2 data bus pins of the digital processor respectively to obtain N2 output data;
sending a first latch chip select signal to a control pin of the first output latch to cause the first output latch to latch the N2 output data;
and sending a first latch access de-chip selection signal to a control pin of the first output latch, so that the first output latch cancels the latch function, and respectively performing signal control on N2 devices to be controlled based on the N2 output data.
7. The method of claim 6, further comprising:
and sending the first latch chip selection signal to a control pin of the first output latch, so that the first output latch only latches data and stops signal control on corresponding equipment to be controlled.
8. The method of claim 7, wherein prior to sending the first output latch control pin the first latch chip select signal, the method further comprises:
and after the first cancel latch chip selection signal is sent, the first latch chip selection signal is sent to a control pin of the first output latch after a first preset time is delayed, wherein the first preset time is longer than or equal to the preset transmission time of the digital processor and the output latch.
9. The method of claim 5, wherein the digital processing circuit further comprises: n3 input latches, after the number of controlled devices reaches the preset number threshold, the method further comprising:
configuring N2 data bus pins of the digital processor as input pins;
and sequentially carrying out signal detection on the corresponding equipment to be detected through the input latches in the N3 input latches until the number of the equipment to be detected reaches a preset detection number threshold.
10. The method of claim 9, wherein said sequentially passing through ones of the N3 input latches for signal detection of the corresponding device under test comprises:
sending a second latch chip selection signal to a control pin of a preset input latch of the N3 input latches, so that the preset input latch latches N2 input data received by the input pin;
and sending a second latch cancellation chip selection signal to a control pin of the preset input latch, so that the preset input latch cancels the latch function, and respectively carrying out signal detection on N2 devices to be detected based on the N2 input data.
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