CN219039599U

CN219039599U - Double-line 256-node matrix switch

Info

Publication number: CN219039599U
Application number: CN202223162333.3U
Authority: CN
Inventors: 杨晟辉; 丁意; 段宇; 时剑
Original assignee: Xi'an Kairui Measurement And Control Technology Co ltd
Current assignee: Xi'an Kairui Measurement And Control Technology Co ltd
Priority date: 2022-11-28
Filing date: 2022-11-28
Publication date: 2023-05-16
Anticipated expiration: 2032-11-28

Abstract

The utility model belongs to the technical field of switch networks, in particular to a double-line 256-node matrix switch, which comprises a front panel connector, a 4x16 relay unit matrix, a relay driving unit, a micro control unit FPGA, a storage unit EEPROM, a power management unit, a level conversion unit and an inter-board connector CPCI which are sequentially arranged.

Description

Double-line 256-node matrix switch

Technical Field

The utility model belongs to the technical field of switch networks, and particularly relates to a double-wire 256-node matrix switch.

Background

The switch network is an important component of an automatic test system, is responsible for the task of controlling signal flow direction, is key to the interface design for realizing automatic test, and has the following constraint factors in the development of the current PXI matrix switch network:

1. the 3U size is limited, the cost of the switch network is proportional to the matrix scale, and the common matrix switch network has no enough switching channels, so that the universality of the switch network in the application of each test system is restricted;

2. the arrangement of the unit matrixes is unreasonable, when the total number of the matrixes is the same, the matrix combination mode is less, the number of the rows and the columns of the matrix switch cannot be flexibly configured, the coping capacity of the matrix switch is shown to be the front part of the special requirement surface of different tested objects, the elbow is caught, and the efficiency of the switch network system is restricted;

3. the single-wire matrix switch can not better meet the requirements of accuracy and reliable operation of differential signals, and increases the interference to the tested signals.

For the above situation we propose a two-wire 256-node matrix switch.

Disclosure of Invention

In order to solve the problems in the prior art, the utility model provides the double-line 256-node matrix switch, which has the characteristics that a universal double-line matrix structure is adopted, the requirements of different test products on excitation signal types and single-end or differential connection are met, the universality of the double-line 256-node matrix switch in different test systems is increased, meanwhile, a user can replace connecting cables according to different product interfaces, frequent development of a switch module and unnecessary maintenance work are avoided, in addition, the matrix nodes are more, the matrix nodes are composed of 4 groups of 4x16 identity matrixes, the corresponding row or column signals on a front panel connector are connected through short circuit, the number of rows or columns of the matrix can be expanded, more test equipment is measured, and the work efficiency of a switch matrix network system is improved.

In order to achieve the above purpose, the present utility model provides the following technical solutions: the 256 node matrix switches of double-line, including front panel connector, 4x16 relay identity matrix, relay drive unit, little control unit FPGA, memory cell EEPROM, power management unit, level conversion unit and the board connector CPCI that sets gradually, wherein:

the front panel connector is used for connecting test resources and UUT units to be tested;

the 4x16 relay unit matrix is an array structure consisting of 4 pairs of row signals and 16 pairs of column signals;

the relay driving unit is used for driving the 4x16 relay unit matrix relay to be opened and closed and realizing the disconnection and the connection of row signal pairs and column signal pairs in the 4x16 relay unit matrix;

the micro control unit FPGA is used for communication interaction with the PCI bus, controlling the relay driving unit to respond to the instruction transmitted by the PCI bus and interaction with the storage unit EEPROM;

the storage unit EEPROM is used for storing user information;

the power management unit is used for converting various voltages required by the matrix switch and ensuring the stability of the voltages;

the level conversion unit is used for ensuring the conversion of the safe working level of the micro control unit FPGA and the PCI bus level;

the board-to-board connector CPCI is used for connection between the two-wire 256-node matrix switch and the PCI bus.

As the preferable technical scheme of the double-line 256-node matrix switch, the 4x16 relay unit matrix and the relay driving unit are provided with four groups.

As the preferable technical scheme of the double-line 256-node matrix switch, a double-pole double-throw relay switch is arranged on a node where row and column signals of the 4x16 relay unit matrix are crossed, and relays corresponding to row signals and column signals are controlled to be closed and opened.

As a preferable technical scheme of the double-line 256-node matrix switch, a plurality of array modes of 2 4x32 matrixes, 2 8x16 matrixes, 1 4x64 matrix and 1 x16 matrix can be formed by shorting corresponding row or column signal lines on the connector.

Compared with the prior art, the utility model has the beneficial effects that:

1. the utility model is a 256-node matrix switch module formed by 4x16 unit matrixes of 4 groups of double-wire structures, and the internal functional modules of the matrix switch module comprise a front panel connector, 4x16 relay unit matrixes, a relay driving unit, a micro control unit FPGA, a storage unit EEPROM, a power management unit, a level conversion unit and an inter-board connector CPCI; the working principle is as follows: the upper computer transmits control instructions to a micro control unit FPGA (main control unit) of the double-line 256-node matrix switch through a PCI bus, the micro control unit FPGA analyzes the instructions and controls a relay driving unit to act, and the relay is closed or opened, so that the communication or opening of corresponding row and column signals of the matrix is realized.

2. The utility model adopts a universal double-line matrix structure, can meet the connection requirements of different test products on excitation signal types and single-end or differential connection, and increases the universality of the double-line 256-node matrix switch in different test systems.

3. According to the utility model, a user can replace the connecting cable according to different product interfaces, so that frequent development of the switch module and unnecessary maintenance work are avoided.

4. The utility model has more matrix nodes and consists of 4 groups of 4x16 identity matrixes, and the corresponding row or column signals on the front panel connector are connected in a short circuit manner, so that the number of rows or columns of the matrix can be expanded, more test equipment can be measured, and the working efficiency of the switch matrix network system can be improved.

Drawings

The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the embodiments of the utility model, serve to explain the utility model. In the drawings:

FIG. 1 is a functional block diagram of the present utility model;

FIG. 2 is a schematic diagram of a 4x16 relay identity matrix of the present utility model;

FIG. 3 is a schematic diagram of a 4x32 relay identity matrix of the present utility model;

FIG. 4 is a schematic diagram of an 8x16 relay identity matrix of the present utility model;

FIG. 5 is a schematic diagram of a 4x64 relay identity matrix of the present utility model;

fig. 6 is a schematic diagram of a 16x16 relay identity matrix of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Examples

Referring to fig. 1, 2, 3, 4, 5 and 6, the present utility model provides the following technical solutions: the utility model is a 256-node matrix switch module composed of 4x16 unit matrixes of 4 groups of double-wire structures, the internal function modules of the matrix switch module are composed of a front panel connector, 4x16 relay unit matrixes, a relay driving unit, a micro control unit FPGA, a storage unit EEPROM, a power management unit, a level conversion unit and an inter-board connector CPCI, wherein:

front panel connector: the UUT is used for connecting the test resource and the tested unit;

4x16 relay identity matrix: is an array structure consisting of 4 pairs of row signals and 16 pairs of column signals;

relay driving unit: the switching device is used for driving the 4x16 relay unit matrix relay to be opened and closed, and realizing the disconnection and connection of row signal pairs and column signal pairs in the 4x16 relay unit matrix;

micro control unit FPGA: the relay driving unit is used for communicating with the PCI bus, controlling the relay driving unit to respond to the instruction transmitted by the PCI bus and interacting with the storage unit EEPROM;

a memory cell EEPROM: for storing user information;

a power management unit: for converting various voltages required for matrix switches and for ensuring the stabilization of the voltages;

level conversion unit: the switching device is used for ensuring the conversion of the safe working level of the micro control unit FPGA and the PCI bus level;

board-to-board connector CPCI: connection between two-wire 256 node matrix switch and PCI bus

Referring to fig. 1 and 2, further, the unit matrix is composed of 4 pairs of row signals and 16 pairs of column signals, a double-pole double-throw relay switch is placed on a node where the row signals and the column signals intersect, and the connection and disconnection of the row signals (ri+/Ri-) and the column signals (ci+/Ci-) are realized by controlling the relay corresponding to the row signals and the column signals to be closed and opened.

Further, as shown in fig. 3, 4, 5 and 6, by shorting the corresponding row or column signal lines on the connector, a plurality of array modes of 2 4x32 matrices, 2 8x16 matrices, 1 4x64 matrix, 1 16x16 matrix can be formed.

The working principle of the embodiment is as follows: the upper computer transmits control instructions to a micro control unit FPGA (main control unit) of the double-line 256-node matrix switch through a PCI bus, the micro control unit FPGA analyzes the instructions and controls a relay driving unit to act, and the relay is closed or opened, so that the communication or opening of corresponding row and column signals of the matrix is realized.

Advantages and beneficial effects of the present embodiment: the utility model adopts a general double-line matrix structure, can meet the connection requirements of different test products on excitation signal types (single-ended or differential), and increases the universality of the double-line 256-node matrix switch in different test systems; according to the utility model, a user can replace the connecting cable according to different product interfaces, so that frequent development of the switch module and unnecessary maintenance work are avoided; the utility model has more matrix nodes and consists of 4 groups of 4x16 identity matrixes, and the corresponding row or column signals on the front panel connector are connected in a short circuit manner, so that the number of rows or columns of the matrix can be expanded, more test equipment can be measured, and the working efficiency of the switch matrix network system can be improved.

Other alternatives to this embodiment: the PCI bus, PCI bridge chip, CPLD and DSP mode can complete the transmission of instructions from the PCI bus of the upper computer channel to the DSP, the DSP analyzes the instructions of the upper computer and transmits action instructions to the relay driving unit, and the relay is controlled to be opened and closed; using an AMR processor with a PCI interface to replace the micro control unit FPGA and the level conversion unit in FIG. 2; using PCIe interface instead of the board-to-board connector CPCI and level-shifting unit in fig. 2; PCIe interface + DSP is used instead of the board-to-board connector CPCI and micro-control unit FPGA in fig. 2.

Key point and protection point of this embodiment: flexible matrix combination, large matrix scale, and two-wire structure.

In this embodiment, the contents not described in detail are all known in the art.

Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present utility model, and the present utility model is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present utility model has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. Double-line 256 node matrix switch, including front panel connector, 4x16 relay identity matrix, relay drive unit, little control unit FPGA, memory cell EEPROM, power management unit, level conversion unit and the board connector CPCI that sets gradually, its characterized in that:

the storage unit EEPROM is used for storing user information;

2. The two-wire 256-node matrix switch of claim 1, wherein: four groups of relay unit matrixes and relay driving units are arranged in the 4x16 relay unit matrixes.

3. The two-wire 256-node matrix switch of claim 1, wherein: and a double-pole double-throw relay switch is arranged on a node of the row-column signal intersection of the 4x16 relay unit matrix, and the relay corresponding to the row signal and the column signal is controlled to be closed and opened.

4. The two-wire 256-node matrix switch of claim 1, wherein: by shorting the corresponding row or column signal lines on the connector, 2 multiple array modes of the 4x32 matrix, the 2 8x16 matrix, the 1 4x64 matrix, and the 1 16x16 matrix can be formed.