CN210640175U - Electronic chip packaging structure - Google Patents
Electronic chip packaging structure Download PDFInfo
- Publication number
- CN210640175U CN210640175U CN201921776919.4U CN201921776919U CN210640175U CN 210640175 U CN210640175 U CN 210640175U CN 201921776919 U CN201921776919 U CN 201921776919U CN 210640175 U CN210640175 U CN 210640175U
- Authority
- CN
- China
- Prior art keywords
- groove
- substrate
- chip
- carrier
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model adopts the technical proposal that: an electronic chip packaging structure is characterized by comprising a finished product carrier, a substrate and a chip; a groove is arranged on the finished product carrier, and the chip is fixed on the substrate; the substrate is arranged in the groove; the surface of the substrate with the chip faces the groove; the substrate and the finished product carrier are fixedly connected and packaged through viscose glue. The utility model aims at providing an electronic chip packaging structure to prior art's defect, effectively reducing the manufacturing cost of whole process.
Description
Technical Field
The utility model relates to a chip package technical field, concretely relates to electronic chip packaging structure.
Background
Electronic chips are currently packaged by a molding packaging process. The molded package can ensure the mechanical strength, airtightness and electrical connection performance of the finished electronic device. One or more electronic chips are encapsulated by molding to form an electronic device.
The development of the mold packaging process has led to a branch of numerous technological processes. Including BGA packaging and LGA packaging. These 2 package processes all lead the leads of the chip through the substrate circuitry to the bottom contacts of the molded package that form the electronic device. The purpose of the BGA packaging process is to solder these contacts, so solder balls are added to the contacts; the purpose of the LGA packaging process is to bring these contacts into contact with the contacts of the connector. In order to obtain excellent mechanical strength and electrical connection performance, more and more electronic products are also manufactured using a packaging process like BGA and LGA. The process is almost completely identical except that the physical dimensions and the placement of the contacts are slightly different from those of the conventional BGA and LGA.
The specific process steps of the molding packaging process are as follows:
1. a substrate material with high glass transition temperature (generally required to be about 175-230 ℃), high dimensional stability and low moisture absorption, and good electrical performance and high reliability is selected. A conductive circuit is formed on the substrate.
2. And binding one or more chips or flip-chip packaging or smt process mounting on the substrate. A plurality of substrates share one large-size substrate jointed board so as to improve the production efficiency. As shown in fig. 1.
3. The base plate jointed board is put into an injection molding grinding tool, and a plastic package material is injected. Epoxy resin mixtures are generally used as molding compounds. As shown in fig. 2.
4. And after the plastic package material attached to the jointed substrate board is solidified, cutting the jointed substrate board according to the design size specification to form the final electronic device or electronic product.
In order to meet the requirements of the above process, the production cost is expensive. The reason is as follows:
1. in order to achieve the appropriate performance specifications for each component, the materials used are relatively expensive. In order to obtain a substrate with higher glass transition temperature, high dimensional stability and low moisture absorption, BT resin material or ceramic is selected to be used for producing the substrate. Making the substrate very expensive.
2. The process of injecting the molding compound requires that the whole surface of the substrate is used as the bottom surface of the injected molding compound. The consumption of the substrate is increased. Taking the TF card and the internet of things card as examples, the minimum necessary substrate areas are the areas of the contact areas, respectively. But because of the mold encapsulation process, the entire bottom surface is used for the substrate.
3. The injection molding packaging of the electronic chip molding packaging process takes a long time. If the area of the electronic product or device is large, the efficiency of forming the substrate board is basically offset.
4. For cutting of finished products with non-rectangular appearances, the processes of laser cutting, water jet cutting and the like need to be used at present, and the efficiency is very low.
Among the above reasons, the cost of the substrate, in particular, accounts for a large half of the entire production cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an electronic chip packaging structure to prior art's defect, effectively reducing the manufacturing cost of whole process.
The utility model adopts the technical proposal that: an electronic chip packaging structure is characterized by comprising a finished product carrier, a substrate and a chip; a groove is arranged on the finished product carrier, and the chip is fixed on the substrate; the substrate is arranged in the groove; the surface of the substrate with the chip faces the groove; the substrate and the finished product carrier are fixedly connected and packaged through viscose glue.
The finished product carrier comprises three pieces of flaky insulating high-temperature-resistant materials with the same structural size, and a first through hole is formed in the first piece of insulating high-temperature-resistant material, wherein the shape and the size of the first through hole are matched with those of the substrate; forming a second through hole in the second piece of insulating high-temperature-resistant material, wherein the shape and the size of the second through hole are matched with those of the chip; the upper surface and the lower surface of the second piece of the insulating high-temperature-resistant material are coated with heat-curing glue/films, the first piece of the insulating high-temperature-resistant material, the second piece of the insulating high-temperature-resistant material and the third piece of the insulating high-temperature-resistant material are coaxially overlapped from top to bottom, and the first through hole and the second through hole are coaxially arranged and matched to form a groove; the first, second and third insulating refractory materials are pressed into a whole by heating and pressure to form the finished carrier.
The chip comprises one or more particles and is attached to the substrate through bonding, flip-chip packaging or a smt process.
The substrate can be made of glass fiber board, BT resin material and high TG material. The above materials are common circuit board materials, wherein glass fiber boards are the most common and have the lowest cost; the high TG material has better dimensional stability than the glass fiber board when the temperature changes; the BT resin material has the best dimensional stability and the highest cost when the temperature changes.
The viscose glue adopts heat curing glue, AB glue or anaerobic glue. Adhering the substrate with the chip to the groove of the finished carrier by using an adhesive which does not lose viscosity at high temperature
The plane size of the finished product carrier upper groove is larger than that of the substrate; the groove is a step groove, and the step groove comprises a primary groove and a secondary groove which sequentially extend towards the interior of the finished product carrier; the first through hole and the upper surface of the second piece of insulating high-temperature-resistant material are matched to form a primary groove, the substrate is arranged in the primary groove of the stepped groove, the first through hole and the upper surface of the second piece of insulating high-temperature-resistant material are matched to form a secondary groove, and the chip is arranged in the secondary groove of the stepped groove. Since the chip protrudes from the plane of the substrate, the step groove is provided to provide a space for mounting the chip on the finished carrier.
The adhesive is coated on one surface of the substrate with the chip and the peripheral edge of the substrate, so that the mounting stability of the substrate and the carrier is effectively ensured.
The finished carrier is made of metal or ceramic or plastic packaging material; the metal material is selected from metal with a melting point higher than 300 ℃ and a low thermal expansion coefficient; obtaining a finished product carrier and a groove with required dimension specifications by adopting a cutting or etching method; conducting and insulating treatment is carried out on the metal material; the finished carrier is made of ceramic and plastic packaging materials, and a groove is formed through an injection molding process.
The utility model discloses an electronic chip packaging method, including following step:
a. obtaining a finished product carrier, and arranging a groove on the finished product carrier;
b. mounting a chip onto a substrate;
c. the substrate with the chip is mounted into the slot.
In the step a, metal or ceramic and plastic package materials are used as finished product carriers of electronic devices or electronic products; if the metal material is selected as a finished product carrier, the metal material is selected from metal with the melting point higher than 300 ℃ and the thermal expansion coefficient lower than that of the metal material; obtaining a finished product carrier and a groove with required dimension specifications by adopting a cutting or etching method; conducting and insulating treatment is carried out on the metal material; if ceramic and plastic package materials are selected as finished product carriers, grooves are formed through an injection molding process;
the plane size of the upper groove of the finished product carrier in the step a is larger than that of the substrate; the groove is a step groove, wherein the substrate is arranged in a primary groove of the step groove, and the chip is arranged in a secondary groove of the step groove.
The step a comprises the following steps:
selecting three pieces of sheet-shaped insulating high-temperature-resistant materials with the same structural size, and forming a first through hole in the first piece of insulating high-temperature-resistant material, wherein the shape and the size of the first through hole are matched with those of the substrate; forming a second through hole in the second piece of insulating high-temperature-resistant material, wherein the shape and the size of the second through hole are matched with those of the chip; coating heat curing glue/films on the upper surface and the lower surface of the second piece of the insulating high-temperature-resistant material, and coaxially overlapping the first piece of the insulating high-temperature-resistant material, the second piece of the insulating high-temperature-resistant material and the third piece of the insulating high-temperature-resistant material from top to bottom, wherein the first through hole and the second through hole are coaxially arranged and matched to form a groove; and pressing the first, second and third sheets of insulating high-temperature-resistant materials into a whole by heating and pressing to form a finished carrier.
In the above technical solution, further comprising step d: the heated finished carrier is divided by means of routing, milling or stamping to form the desired shape to form a single finished product, i.e. a finished carrier is provided with only one substrate with chips.
And b, binding one or more chips of particles on the substrate, or inversely packaging or mounting the particles on the substrate by a smt process.
The substrate in the step b can be made of glass fiber boards, BT resin materials and high TG materials. The above materials are common circuit board materials, wherein glass fiber boards are the most common and have the lowest cost; the high TG material has better dimensional stability than the glass fiber board when the temperature changes; the BT resin material has the best dimensional stability and the highest cost when the temperature changes.
And c, adhering the substrate with the chip into the groove of the finished product carrier by adopting an adhesive which does not lose viscosity at high temperature, such as a heat-curing adhesive, an AB adhesive and an anaerobic adhesive, wherein the adhesive is easy to implement.
And the plane size of the groove on the carrier in the step a is larger than that of the substrate. The difference in planar dimensions of the slot and the substrate depends on the difference in thermal expansion coefficients of the components, and the tolerances of the production build-up. The groove is a step groove. Since the chip protrudes from the plane of the substrate, the step groove is provided to provide a space for mounting the chip on the finished carrier. The first through hole of the first-level groove is of a rectangular structure and is used for placing a substrate; the secondary groove, namely the second through hole, is of a circular structure and provides mounting space for the chip on the carrier. The chip is arranged in the secondary groove.
And c, coating the adhesive on one surface of the substrate with the chip and the peripheral edge of the substrate, so as to effectively ensure the mounting stability of the substrate and the carrier. Placing the substrate coated with the viscose glue into a groove of a carrier to apply pressure, and after at least 10 seconds, fixedly bonding the substrate and the carrier; wherein the surface of the substrate with the chip faces the carrier groove for placement
And c, after the substrate coated with the viscose is placed in the groove, heating and pressurizing the three insulating high-temperature-resistant materials by using a laminating machine, and after lamination is finished, putting the three insulating high-temperature-resistant materials into a heating furnace for continuous heating. Wherein the side of the substrate with the chip is placed facing the carrier slot.
A plurality of uniformly distributed grooves are formed in the finished product carrier in the step a; a substrate with a chip is placed in each groove;
in the step d, the heated finished product carrier is divided in a routing, milling or stamping mode to form a plurality of single final products, namely, one finished product carrier is only provided with one substrate with chips.
The materials adopted by the utility model are all high temperature resistant materials with good dimensional stability under temperature change; the sealing measure is adopted to prevent moisture from directly contacting the chip crystal grains, so that the waterproof effect is effectively achieved, and the product size cannot be forced to be enlarged. The selection of the substrate material of the invention is not very strict, and the substrate material which can be generally subjected to reflow soldering can be satisfied. The area of the substrate can be adjusted according to the area required by the position of the actual contact, and the bottom of the whole finished product is not required to be the substrate. Taking the TF card and the internet of things card as examples, the minimum necessary substrate areas are the areas of the contact areas respectively. The process for generating the carrier and the bonding process of the carrier and the substrate can realize large-scale batch production, and the production method is very simple. Therefore, the invention can effectively reduce the packaging cost. The finished carrier is made of insulating high-temperature-resistant materials, so that the product has good mechanical strength, certain toughness, strong adhesive force with the components close to those of the substrate, basically consistent thermal expansion coefficients, low possibility of deformation after high and low temperature changes and low cost.
Drawings
FIG. 1 is a schematic diagram of a prior art configuration
FIG. 2 is a schematic diagram of a prior art package
FIG. 3 is a schematic view of the structure of the present invention
FIG. 4 is a schematic view of the finished carrier of the present invention
FIG. 5 is a schematic view of the chip and substrate connection of the present invention
FIG. 6 is a schematic view of a substrate package according to the present invention
FIG. 7/8 is a process schematic of the present invention
The manufacturing method comprises the following steps of 1-substrate, 2-chip, 3-injection mold, 4-finished product carrier, 5-groove, 6-pin, 7-metal conductor, 8-thermosetting adhesive film, 9-insulating high-temperature-resistant material, 91-first piece of insulating high-temperature-resistant material, 92-second piece of insulating high-temperature-resistant material, 93-third piece of insulating high-temperature-resistant material, 10-first through hole, 11-second through hole and 12-final product.
Detailed Description
The invention will be further described in detail with reference to the drawings and the following detailed description, which are provided for the purpose of clearly understanding the invention and are not intended to limit the invention.
As shown in fig. 1, the present invention provides 2 specific embodiments of a package internet of things card. But not limited to, the internet of things card, and the same product can also be used for producing TF cards and other products which originally use a molding packaging process.
In this embodiment 1, a 0.2mm thick sheet-like insulating high temperature resistant material 91 is selected, and a first through hole 10 (rectangle) and a positioning hole and an exhaust hole of the slot 5 are punched thereon.
Selecting a sheet-shaped insulating high-temperature-resistant material 92 with the thickness of 0.35mm, attaching thermosetting glue/films with the thickness of 0.025mm on the front and back surfaces of the sheet-shaped insulating high-temperature-resistant material, and then forming a second through hole 11 (circular) of the groove 5, a positioning hole and an exhaust hole on the sheet-shaped insulating high-temperature-resistant material by using a drilling machine or a die.
The first piece of insulating high-temperature-resistant material 91 is placed on the top, the second piece of insulating high-temperature-resistant material 92 is placed in the middle, a piece of sheet material with the thickness of 0.2mm, namely a third piece of insulating high-temperature-resistant material 93 is placed below the first piece of insulating high-temperature-resistant material, the three pieces of sheet material are aligned according to set positions, overlapped together, and slightly heated and pressed, so that the three pieces of sheet material are initially integrated into a whole (the heat curing glue/film is not completely cured). The first through hole and the second through hole are coaxially arranged and matched with the upper surface of the third piece of insulating high-temperature-resistant material 93 to form a groove 5; the dimensions of the groove 5 are not well defined from the dimensions of the base plate 1, depending on the differences in the coefficients of thermal expansion between the parts, and the tolerances resulting from production. The groove 5 is a stepped groove. Since the chip 2 protrudes above the plane of the substrate 1, a step groove is provided, providing a mounting space for the chip 2 on the finished carrier 4. A first-level groove of the stepped grooves, namely a first through hole, is of a rectangular structure and is used for placing the substrate 1; the secondary slot, i.e., the second through hole, has a circular structure, and provides a mounting space for the chip 2 on the carrier. The chip 2 is arranged in the secondary tank.
A circuit board is selected as a substrate 1, and a printed circuit is arranged on the circuit board. One plane of the substrate 1 is provided with at least 5 metal contacts for connecting with the card seat contacts of the application equipment; at least 5 pins 6 are arranged on one plane of the substrate 1 and are used for connecting with the Internet of things card chip 2. The metal contacts on the two sides of the substrate 1 are respectively communicated with the pins 6 one by one through the conductive circuits of the metal wires. The material of the substrate 1 is not particularly required, and it is sufficient if reflow soldering can be performed. The planar dimensions of the base plate 1 are slightly smaller than the planar dimensions of the grooves 5 of the carrier. The other side of the plane of the substrate 1 shown in fig. 5 is where the metal contacts are located.
And binding the particles of the chip 2 required by the Internet of things card to the surface of the substrate 1 with at least 5 pins 6 by flip-chip sealing or smt process mounting. The chip 2 is thus finally connected to the metal contacts on the other side by means of the pins 6 on the connection substrate 1. Fig. 5 is a schematic diagram of the chip 2 bound therein.
Placing the substrate 1 in the groove 5, heating and pressurizing the three stacked sheets of the insulating high-temperature-resistant material 9 with the substrate 1 in a laminating machine for a period of time (180 ℃, preheating and exhausting for 10s, and then 30 kg/cm)3For 300s) after lamination, the insulating and refractory material 9 is placed in a heating furnace for heating at 180 ℃ for more than 60 min.
The heated insulating high-temperature-resistant material 9 is finally divided into final products 12 by using a pattern of engraving, milling or punching and the like to piece together a plurality of products.
The invention has the following effects:
1. the Internet of things card manufactured by the method reduces the size of the substrate 1, enlarges the selection range of the substrate 1 material, can realize large-scale production in the process and greatly reduces the production cost. In this embodiment, the size of the substrate 1 is less than one-fourth of the molding process.
2. The process of the finished product carrier (fig. 6 and 7) manufactured by the three-layer material laminating process is similar to the process of the multilayer circuit board production of a PCB (printed circuit board) factory, so that the common PCB factory can realize mass production without adding specific equipment; the pattern matching mode is adopted, and the formal lamination is carried out after the substrate 1 is placed in the groove 5, so that the production efficiency can be greatly improved.
In this embodiment 2, an aluminum alloy plate, an aviation aluminum sheet, with a thickness of about 0.8mm, a low thermal expansion coefficient and a high hardness, is selected as the finished product carrier 4.
When in manufacturing, the aircraft aluminum sheet is firstly processed by the cnc. And milling a groove 5 on one plane of the aircraft aluminum sheet, and cutting the periphery of the plane. The semi-finished product of the internet of things card carrier is obtained as shown in the figure, and the size of the groove 5 is not limited by the difference of definite sizes of the base plate 1, and depends on the difference of thermal expansion coefficients of various parts and the tolerance formed by production. The groove 5 is a stepped groove. Since the chip 2 protrudes above the plane of the substrate 1, a step groove is provided, providing a mounting space for the chip 2 on the finished carrier 4. The primary groove of the stepped groove is of a rectangular structure and is used for placing the substrate 1; the secondary slot is of a circular structure, is convenient to open and provides a mounting space for the chip 2 on the carrier. The chip 2 is arranged in the secondary tank.
And then carrying out anodic oxidation treatment on the outer surface of the semi-finished product of the Internet of things card carrier to obtain a finished product of the carrier. After the anodic oxidation treatment, the surface of the carrier is insulated and can not conduct electricity any more. And after the anodic oxidation treatment, the color of the surface of the carrier can be changed into any color such as gold, silver, black and the like according to the requirement.
The substrate 1 carries printed circuitry thereon. One plane of the substrate 1 is provided with at least 5 metal contacts for connecting with the card seat contacts of the application equipment; at least 5 pins 6 are arranged on one plane of the substrate 1 and are used for connecting with the Internet of things card chip 2. The metal contacts on the two sides of the substrate 1 are respectively communicated with the pins 6 one by one through the conductive circuits of the metal wires. The material of the substrate 1 is not particularly required, and it is sufficient if reflow soldering can be performed. The planar dimensions of the base plate 1 are slightly smaller than the planar dimensions of the grooves 5 of the carrier. One side of the substrate 1 is provided with metal contacts.
The chip 2 particles required by the internet of things card are bonded or flip-chip sealed or smt process mounted on the surface of the substrate 1 with at least 5 pins 6. The chip 2 is thus finally connected to the metal contacts on the other side by means of the pins 6 on the connection substrate 1. Fig. 5 is a schematic diagram of the chip 2 bound therein.
The thermosetting adhesive film 8 is attached to the substrate 1 with the chip 2 at a temperature of about 70 c. The thermosetting adhesive film 8 is attached to the side of the substrate 1 having the chip 2, and the thermosetting adhesive film 8 is attached to the peripheral edge of the substrate 1. As shown in fig. 6.
The processed substrate 1 is placed in the bath 5 of the carrier at a temperature of about 180 c and a certain pressure is applied, and after several tens of seconds, the substrate 1 and the carrier are completely adhered together. Later, under the temperature environment below 300 ℃, the two can not be separated. Wherein the side of the substrate 1 with the chips 2 is placed facing the carrier bath 5.
The invention has the following effects:
1. the Internet of things card manufactured by the method reduces the size of the substrate 1, enlarges the selection range of the substrate 1 material, can realize large-scale production in the process and greatly reduces the production cost. In this embodiment, the size of the substrate 1 is less than one-fourth of the molding process.
2. Because the aluminum alloy is adopted as the carrier, the mechanical strength of the product is enhanced, the toughness of the product is particularly enhanced, and the heat dissipation capability is also enhanced.
3. The metal anodizing process can be colorful so that the color of the product is no longer limited to the black color of the molded package.
Details not described in this specification are within the skill of the art that are well known to those skilled in the art.
Claims (9)
1. An electronic chip packaging structure is characterized by comprising a finished product carrier, a substrate and a chip; a groove is arranged on the finished product carrier, and the chip is fixed on the substrate; the substrate is arranged in the groove; the surface of the substrate with the chip faces the groove; the substrate and the finished product carrier are fixedly connected and packaged through viscose glue.
2. The electronic chip package structure of claim 1, wherein the finished carrier comprises three sheets of insulating refractory materials with the same size, and the first sheet of insulating refractory material is provided with a first through hole, wherein the shape and size of the first through hole are matched with those of the substrate; a second through hole is formed in the second piece of insulating high-temperature-resistant material, wherein the shape and the size of the second through hole are matched with those of the chip; the upper surface and the lower surface of the second piece of the insulating high-temperature-resistant material are coated with heat-curing glue/films, the first piece of the insulating high-temperature-resistant material, the second piece of the insulating high-temperature-resistant material and the third piece of the insulating high-temperature-resistant material are coaxially overlapped from top to bottom, and the first through hole and the second through hole are coaxially arranged and matched to form a groove; the first, second and third insulating refractory materials are pressed into a whole by heating and pressure to form the finished carrier.
3. The electronic chip package of claim 1, wherein the chip comprises one or more particles that are attached to the substrate by bonding, flip-chip bonding, or a smt process.
4. The electronic chip package structure of claim 1, wherein the substrate is made of glass fiber, BT resin, or high-TG material.
5. The electronic chip package structure of claim 1, wherein the planar dimensions of the slots on the finished carrier are greater than the planar dimensions of the substrate; the groove is a step groove, and the step groove comprises a primary groove and a secondary groove which sequentially extend towards the interior of the finished product carrier; the substrate is arranged in the primary groove of the step groove, and the chip is arranged in the secondary groove of the step groove.
6. The electronic chip package structure of claim 2, wherein the planar dimensions of the slots on the finished carrier are greater than the planar dimensions of the substrate; the groove is a step groove, and the step groove comprises a primary groove and a secondary groove which sequentially extend towards the interior of the finished product carrier; the first through hole and the upper surface of the second piece of insulating high-temperature-resistant material are matched to form a primary groove, the substrate is arranged in the primary groove of the stepped groove, the first through hole and the upper surface of the second piece of insulating high-temperature-resistant material are matched to form a secondary groove, and the chip is arranged in the secondary groove of the stepped groove.
7. The electronic chip package structure of claim 1, wherein the thermosetting adhesive is coated on the side of the substrate having the chip and the peripheral edge of the substrate.
8. The electronic chip package structure of claim 1, wherein the adhesive is a thermal curing adhesive, an AB adhesive, or an anaerobic adhesive.
9. The electronic chip package structure of claim 1, wherein the finished carrier is selected from metal, ceramic, and plastic package material; the metal material is selected from metal with a melting point higher than 300 ℃ and a low thermal expansion coefficient; obtaining a finished product carrier and a groove with required dimension specifications by adopting a cutting or etching method; conducting and insulating treatment is carried out on the metal material; the finished carrier is made of ceramic and plastic packaging materials, and a groove is formed through an injection molding process.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2019209627543 | 2019-06-25 | ||
| CN201920962754 | 2019-06-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210640175U true CN210640175U (en) | 2020-05-29 |
Family
ID=70797536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921776919.4U Active CN210640175U (en) | 2019-06-25 | 2019-10-22 | Electronic chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210640175U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081561A (en) * | 2019-06-25 | 2020-04-28 | 姜凤明 | Electronic chip packaging structure and method thereof |
-
2019
- 2019-10-22 CN CN201921776919.4U patent/CN210640175U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081561A (en) * | 2019-06-25 | 2020-04-28 | 姜凤明 | Electronic chip packaging structure and method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10204882B2 (en) | Stacked package module having an exposed heat sink surface from the packaging | |
| CN109257888B (en) | Circuit board double-sided packaging method and structure and mobile terminal | |
| JP6672113B2 (en) | Electronic circuit device and method of manufacturing electronic circuit device | |
| JP5198265B2 (en) | Apparatus and method for forming a flat surface of a thin flexible substrate | |
| CN101278383B (en) | Electronic circuit device and method for manufacturing same | |
| CN105643855A (en) | Electronic component, method and apparatus for producing same | |
| WO2008061464A1 (en) | Ic card manufacturing method by interally sealing the combination of chips and elements by using plastic package technique | |
| US8421204B2 (en) | Embedded semiconductor power modules and packages | |
| JP2012248602A (en) | Resin-sealed electronic control device and manufacturing method of the same | |
| JPH09169187A (en) | Manufacture of a set of electronic modules for electronic memory card | |
| JPS5980946A (en) | Ceramic leadless package and its manufacture | |
| CN102074518A (en) | Semiconductor chip assembly with post/base heat spreader and conductive trace | |
| CN210640175U (en) | Electronic chip packaging structure | |
| CN108321092B (en) | Method for manufacturing circuit component and circuit component | |
| CN111081561A (en) | Electronic chip packaging structure and method thereof | |
| CN117577620A (en) | Resin sheet lamination packaging support and processing technology thereof | |
| US20190139702A1 (en) | Irreversible circuit element, irreversible circuit device, and method for manufacturing said element and device | |
| JPH032099A (en) | Preparation of ic card | |
| CN215815839U (en) | Electronic chip packaging structure | |
| CN213546318U (en) | Three-dimensional packaging structure based on radio frequency chip | |
| CN112614786A (en) | Method for assembling integrated circuit board | |
| TW201630131A (en) | A circuit module package structure and packaging method thereof | |
| JP3398580B2 (en) | Semiconductor device manufacturing method and substrate frame | |
| CN219286393U (en) | Novel copper substrate carrier and intelligent power semiconductor module | |
| CN112838016B (en) | Chip thickening method for embedded substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |