CN210639511U

CN210639511U - Computer with automatic clear CMOS circuit

Info

Publication number: CN210639511U
Application number: CN201922216396.4U
Authority: CN
Inventors: 江晓东
Original assignee: Shenzhen Xinhongsheng Electronic Co Ltd
Current assignee: Shenzhen Xinhongsheng Electronic Co Ltd
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2020-05-29
Anticipated expiration: 2029-12-11

Abstract

The utility model discloses a computer with clear CMOS circuit automatically, including D1, D2, Q85, first delay circuit, the second delay circuit, the third delay circuit, first delay circuit input end is connected with PSON, first delay circuit output end is connected with RD1 foot of D1, the Q1 foot of D1 is connected with Q85's G utmost point through the second delay circuit, Q85's D utmost point connects ICH _ RTCRST, D1's-Q1 foot is connected with D2's RD2 foot through the third delay circuit, D1's Q1 foot still is connected with D2's SD2 foot, D2's Q2 foot is connected with Q85's G utmost point, D2's D foot passes through R645 ground connection. The utility model discloses a set up two triggers D1 and D2, first delay circuit, second delay circuit, third delay circuit and Q85, guarantee that the user starts at the computer, shuts down the button in-process and realizes automatic clear CMOS, reduce the rate of reprocessing, practice thrift commodity circulation and cost of maintenance, circuit structure is simple, and the cost is lower.

Description

Computer with automatic clear CMOS circuit

Technical Field

The utility model relates to a computer maintenance field especially relates to a computer with clear CMOS circuit of automation.

Background

In the prior art, the repaired clean CMOS of a computer can account for 10% -20% of the repaired fault, the fault is very simple for repairing, but is disastrous for users, and the high repair rate of the clean CMOS causes the increase of the logistics cost, the maintenance cost and the like.

Accordingly, the prior art is deficient and needs improvement.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is: the computer with the automatic CMOS circuit cleaning function is convenient to maintain and capable of reducing maintenance cost.

The technical scheme of the utility model as follows: a computer with an automatic CMOS cleaning circuit comprises a computer mainboard, and further comprises D1, D2, Q85, a first delay circuit, a second delay circuit and a third delay circuit which are positioned on the computer mainboard, wherein an input end of the first delay circuit is connected with PSON, an output end of the first delay circuit is connected with RD1 pin of D1, a D pin and an SD1 pin of D1 are respectively connected with a VCC pin of D1, a VCC pin of D1 is connected with + V5AL, a CP pin of D AL is connected with FP-PWRSW-L, a Q AL pin of D AL is connected with a G pole of Q AL through the second delay circuit, a D pole of Q AL is connected with ICH-RTCRST, an S pole of Q AL is grounded, a-Q AL pin of D AL is connected with the RD AL pin of D AL through the third delay circuit, a Q pole of D AL is connected with VCC pin of SD-RTCRST, a D pole of D AL is connected with D AL, a D pole of Q AL is connected with a D AL, a D pole of Q72 is connected with a D AL, a D AL, the CP pin of D2 is grounded through R646.

In the technical scheme, the first delay circuit comprises R647 and C296, the first end of the R647 is connected with PSON, the second end of the R647 is connected with RD1 pin of D1, the first end of the C296 is grounded, and the second end of the C296 is connected with RD1 pin of D1.

With the above technical solutions, in the computer with the automatic CMOS circuit, the second delay circuit includes R644 and C298, the first end of the R644 is connected to pin Q1 of D1, the second end of the R644 is connected to the G pole of Q85, the first end of the C298 is grounded, and the second end of the C298 is connected to the G pole of Q85.

With the above technical solutions, in the computer with an automatic clear CMOS circuit, the third delay circuit includes R649 and C299, a first end of the R649 is connected to a-Q1 pin of D1, a second end of the R649 is connected to an RD2 pin of D2, a first end of the C299 is grounded, and a second end of the C299 is connected to an RD2 pin of D2.

By adopting the technical scheme, the computer with the automatic clear CMOS circuit further comprises a D72, wherein the anode of the D72 is connected with the G pole of Q85, and the cathode of the D72 is connected with the Q2 pin of the D2.

By adopting the technical scheme, in the computer with the automatic clear CMOS circuit, the VCC pin of D1 is grounded through C295.

Adopt above-mentioned each technical scheme, the utility model discloses a set up two triggers D1 and D2, first delay circuit, second delay circuit, third delay circuit and Q85, guarantee that the user starts at the computer, shuts down the button in-process and realizes automatic clear CMOS, reduces the rate of reprocessing, practices thrift commodity circulation and cost of maintenance, and circuit structure is simple, and the cost is lower.

Drawings

Fig. 1 is a schematic diagram of the circuit structure of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

It should be noted that D1 and D2 in this embodiment are 74HCT74 flip-flops, and this embodiment is provided with a double flip-flop, where D72 is a diode, and Q85 is an N-channel MOS transistor.

The embodiment provides a computer with an automatic CMOS circuit, which comprises a computer motherboard, and further comprises D1, D2, Q85, a first delay circuit, a second delay circuit, and a third delay circuit, which are located on the computer motherboard, wherein an input terminal of the first delay circuit is connected to PSON, an output terminal of the first delay circuit is connected to RD1 pin of D1, a D pin of D1 and a SD1 pin are respectively connected to VCC pin of D1, a VCC pin of D1 is connected to + V5AL, a CP pin of D AL is connected to FP _ PWRSW _ L, a Q AL pin of D AL is connected to a G pole of Q AL through the second delay circuit, a D pole of Q AL is connected to ICH _ RTCRST, an S pole of Q AL is grounded, a-Q AL pin of D AL is connected to RD pin of D AL through the third delay circuit, a SD pole of D AL is connected to Q72, a Q pole of Q72 is connected to Q72, a D pole of Q72 is connected to a D pin of Q AL is connected to a + V AL through Q72, a D AL pin of Q72 is connected to a D AL, a Q645 pin of Q72 is connected to a D AL, a Q72 is connected to a D + V AL pin of Q72 is connected to a, the CP pin of D2 is grounded through R646.

Preferably, the first delay circuit comprises R647 and C296, a first end of the R647 is connected with PSON, a second end of the R647 is connected with RD1 pin of D1, a first end of the C296 is grounded, and a second end of the C296 is connected with RD1 pin of D1.

Preferably, the second delay circuit comprises R644 and C298, a first end of the R644 is connected with pin Q1 of D1, a second end of the R644 is connected with pole G of Q85, a first end of the C298 is grounded, and a second end of the C298 is connected with pole G of Q85.

Preferably, the third delay circuit comprises R649 and C299, a first end of the R649 is connected with a pin-Q1 of D1, a second end of the R649 is connected with a pin RD2 of D2, a first end of the C299 is grounded, and a second end of the C299 is connected with a pin RD2 of the D2.

Preferably, the device also comprises D72, wherein the positive electrode of D72 is connected with the G electrode of Q85, and the negative electrode of D72 is connected with the Q2 pin of D2.

Preferably, the VCC pin of D1 is also grounded through C295.

The automatic clear CMOS principle is explained below with reference to fig. 1.

The logical relationship between the D1 and D2 flip-flops is shown in the following table 1

TABLE 1

According to the above table 1 and fig. 1, the specific principle is as follows:

r647 and C296 form an RC delay circuit to keep RD1 pin low during power up.

1. Initial state at normal boot: SD1 ═ H, RD1 ═ L, Q1 ═ L, -Q1 ═ H, QA ═ L, Q85 nonconductive, CMOS normal, SD2 ═ Q1 ═ L, RD2 ═ L, Q2 ═ H, -Q2 ═ L.

2. State after completion of charging: SD1, RD1, Q1, Q1, H, and CP have no signal, although RD1 changes state, so the output level remains unchanged. SD2 ═ L, RD2 may be high or low, Q2 ═ H, -Q2 ═ L or-Q2 ═ H.

3. Change of the user's press POWER switch process: when a rising edge is detected, D1 is H, Q1n +1 is H, and Q1n +1 is L, an RC delay circuit formed by R644 and C298 starts to charge pin 1 of Q85, and if the voltage reaches 1.2V or more, Q85 is turned on, so that clear CMOS occurs. In this case, SD2 ═ H, RD2 ═ H, RD2 ═ L, RD2 ═ L, Q2 ═ L, and-Q2 ═ H, and when RD2 ═ H and no CP, the original output is maintained, and Q2 ═ H.

4. After the POWER switch is pressed for 2ms in normal startup, the PSON becomes low, and the process changes: SD1 ═ H, RD1 ═ L, Q1 ═ L, -Q1 ═ H, and C298 were discharged by R644. Wherein, it is required to ensure that within 2ms, the 1 pin of Q85 cannot be high. SD2 ═ L, RD2 may be high or low, Q2 ═ H, -Q2 ═ L or-Q2 ═ H, and do not affect the voltage of pin 1 of Q85.

5. Change of normal shutdown under system or DOS: under the conditions of POWER _ SW, SD 1-H, RD 1-L, Q1-L, Q1-H, SD 2-L, RD 2-H, Q2-H, and Q2-L. After the system is shut down, SD1 is H, RD1 is H, Q1 is L, and Q1 is H, and at this time, the output level remains unchanged because the CP has no signal although the state of RD1 changes. And returning to the initial state, the circuit has no influence on normal open shutdown. And in a fault state, when the computer has a fault and the CMOS needs to be cleaned, the state at this time is that when the POWER switch is pressed, the system is not powered on, and correspondingly, the PSON signal is not changed.

The circuit changes as follows: in an initial state after POWER on or POWER off, SD1 is H, RD1 is H, Q1 is L, Q1 is H, after a POWER switch is pressed, when a rising edge is detected, D1 is H, Q1n +1 is H, Q1n +1 is L, an RC circuit formed by R644 and C298 starts to charge to pin 1 of Q85, Q2 is H, Q85 is charged to 1.2V or more, Q85 is turned on, the system is cleared of CMOS, when Q2 is L, Q85 is clamped by Q2, and the system is cleared of CMOS.

SD2 becomes H, RD2 becomes H, Q2 becomes L, if the power switch is pressed again, press before: SD1 ═ H, RD1 ═ H, D1 ═ H, Q1 ═ H, -Q1 ═ L; according to the following steps: after the CMOS is cleared, the PSON can normally emit a low level, SD 1-H, RD 1-L, Q1-L, and-Q1-H.

6. Three delay circuits are illustrated below:

the first delay circuits R647 and C296 illustrate: the method mainly ensures that the startup is at a low level, the PSON can respond quickly when becoming low, and the corresponding speed is within 10 ms.

The second delay circuits R644 and C298 illustrate: the instant of starting the computer becomes high, the CMOS cannot be triggered to be cleared within 2ms, R643 is convenient to adjust, and the CMOS must be cleared when the time exceeds 20 ms.

The third delay circuits R649 and C299 illustrate: the method mainly comprises the steps that the CMOS can be automatically finished after being cleaned, otherwise, a rebooting system cannot respond, the time is longer than 5s and shorter than 10s in principle, the CMOS can be cleaned if the time is too short, and the time is too long if the time is too long.

The overall operation process of the circuit principle is summarized in the following table 2

TABLE 2

In table 2, when the discharge of R644 and C298 is completed at the time of failure, the CMOS cleaning is finished.

The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A computer with an automatic CMOS cleaning circuit comprises a computer mainboard and is characterized by further comprising D1, D2 and Q85, a first delay circuit, a second delay circuit and a third delay circuit which are positioned on the computer mainboard, wherein an input end of the first delay circuit is connected with PSON, an output end of the first delay circuit is connected with an RD1 pin of D1, a D pin and an SD1 pin of D1 are respectively connected with a VCC pin of D1, a VCC pin of D1 is connected with + V5AL, a CP pin of D AL is connected with FP _ PWRSW _ L, a Q AL pin of D AL is connected with a G pole of Q AL through the second delay circuit, a D pole of Q AL is connected with an ICH _ RTCRST, an S pole of Q AL is grounded, a-Q AL pin of D AL is connected with the RD AL pin of D AL through the third delay circuit, an SD pole of D AL is connected with a D pole of ICH _ RTCRST, an S pole of Q AL is connected with a ground, a D pole of D AL is connected with a D AL, a D pole of Q72, a D pole of D AL is connected with a D AL, a D pole of Q72 is connected with a D AL, a D pole, the CP pin of D2 is grounded through R646.

2. The computer with the CMOS circuit for automatically clearing away as claimed in claim 1, wherein said first delay circuit comprises R647 and C296, said R647 first terminal is connected to PSON, said R647 second terminal is connected to RD1 pin of D1, said C296 first terminal is grounded, said C296 second terminal is connected to RD1 pin of D1.

3. The computer with automatic CMOS circuit clearing as claimed in claim 1, wherein said second delay circuit comprises R644 and C298, said R644 first terminal is connected with Q1 pin of D1, said R644 second terminal is connected with G pole of Q85, said C298 first terminal is grounded, said C298 second terminal is connected with G pole of Q85.

4. The computer with the automatic clear CMOS circuit as claimed in claim 1, wherein said third delay circuit comprises R649 and C299, said R649 first terminal is connected to pin-Q1 of D1, said R649 second terminal is connected to pin RD2 of D2, said C299 first terminal is grounded, said C299 second terminal is connected to pin RD2 of D2.

5. The computer with the automatic clear CMOS circuit as claimed in claim 1, further comprising D72, wherein the positive pole of D72 is connected with the G pole of Q85, and the negative pole of D72 is connected with the Q2 pin of D2.

6. The computer with automatic CMOS circuit clearing as claimed in claim 1, wherein said VCC pin of D1 is further grounded through C295.