CN210639509U

CN210639509U - Computer mainboard with power-on logic level locking circuit

Info

Publication number: CN210639509U
Application number: CN201922182873.XU
Authority: CN
Inventors: 赵舟
Original assignee: Shenzhen Xinhongsheng Electronic Co Ltd
Current assignee: Shenzhen Xinhongsheng Electronic Co Ltd
Priority date: 2019-12-06
Filing date: 2019-12-06
Publication date: 2020-05-29
Anticipated expiration: 2029-12-06

Abstract

The utility model discloses a computer mainboard with start logic level locking circuit, including the mainboard body, still including bistable circuit, NAND gate circuit, anti-interference buffer circuit, surge protection circuit, the resistance of pulling up that is located on the mainboard body, surge protection circuit is located between PWRSW and PWRBTN, pull up resistance first end and +3.3V power connection, pull up resistance second end and PWRBTN and be connected, surge protection circuit passes through anti-interference buffer circuit and is connected with bistable circuit, bistable circuit passes through NAND gate circuit and is connected with SIO _ PSON. The utility model solves the problem of disordered power logic on the mainboard by arranging the bistable circuit and the NAND gate circuit on the mainboard body of the computer under the condition of reducing the production cost of the mainboard, and effectively prevents the automatic startup of the computer when the computer is plugged for the first time; the circuit has the advantages of cost saving, strong practicability, simple circuit structure and the like.

Description

Computer mainboard with power-on logic level locking circuit

Technical Field

The utility model relates to a computer motherboard field especially relates to a computer motherboard with start logic level locking circuit.

Background

In the prior art, a super IO chip of a motherboard mainly integrates functions of a COM port, power-on logic, PS2, fan control, and the like. And manufacturers on the market do not set COM and PS2 functions on the mainboard for saving cost, even some mainboards are not configured with fan control functions, the super IO chip of the whole mainboard only utilizes the power-on logic function, some manufacturers directly delete the super IO from the mainboard for reducing cost, and if the super IO is directly removed, the power-on logic of the mainboard is disordered, so that the computer mainboard can be automatically started when a 220V power supply is plugged for the first time.

Accordingly, the prior art is deficient and needs improvement.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is: the computer mainboard with the power-on logic level locking circuit saves cost, has a simple circuit structure, and prevents the computer from being automatically started up after the computer is plugged in for the first time.

The technical scheme of the utility model as follows: a computer mainboard with a power-on logic level locking circuit comprises a mainboard body, and further comprises a bistable circuit, a NAND gate circuit, an anti-interference isolation circuit, a surge protection circuit and a pull-up resistor, wherein the bistable circuit, the NAND gate circuit, the anti-interference isolation circuit, the surge protection circuit and the pull-up resistor are arranged on the mainboard body, the surge protection circuit is arranged between PWRSW and PWRBTN, the first end of the pull-up resistor is connected with a +3.3V power supply, the second end of the pull-up resistor is connected with PWRBTN, the surge protection circuit is connected with the bistable circuit through the anti-interference isolation circuit, and the bistable circuit is connected with SIO.

By adopting the technical scheme, in the computer main board with the power-on logic level locking circuit, the bistable circuit comprises Q1 and Q2, the NAND gate circuit comprises Q2 and Q3, the bistable circuit and the NAND gate circuit share Q2, the D pole of Q1 is connected with a +3.3V power supply through R3, the S pole of Q1 is grounded, the G pole of Q1 is respectively connected with the D pole of Q2 and the first end of C1, the second end of C1 is grounded, the G pole of Q2 is respectively connected with an anti-interference isolation circuit and the S pole of Q3, the D pole of Q2 is also connected with the +3.3V power supply through R4, the D pole of Q3 is connected with SIO _ PSON, and the G pole of Q3 is connected with SLP _ S3_ L.

By adopting the technical scheme, in the computer mainboard with the power-on logic level locking circuit, the Q1, the Q2 and the Q3 are respectively N-channel triodes.

By adopting the technical scheme, in the computer mainboard with the power-on logic level locking circuit, the anti-interference isolation circuit comprises D1, the negative electrode of D1 is connected with the surge protection circuit, and the positive electrode of D1 is connected with the G electrode of Q2.

By adopting the technical scheme, in the computer mainboard with the power-on logic level locking circuit, the surge protection circuit comprises R2 and C2, the first end of R2 is respectively connected with the first end of C2, the negative electrode of D1 and PWRSW, the second end of C2 is grounded, and the second end of R2 is respectively connected with the second end of a pull-up resistor and PWRBTN.

By adopting the technical proposal, the utility model discloses a Q1 and Q2 constitute bistable circuit, and Q2 and Q3 constitute NAND gate circuit, adopt the mode that sets up bistable circuit and NAND gate circuit on the mainboard body of computer, can avoid the problem that the computer just starts up automatically when plugging in the power for the first time to appear; meanwhile, an anti-interference isolation circuit and a surge protection circuit are arranged on the main board body, so that surges and interference voltage generated on the circuit can be absorbed, and the safety is high; the circuit structure on the mainboard body is simple, the practicality is strong, under the circumstances that reduces mainboard manufacturing cost, can solve the chaotic problem of mainboard power-on logic again, prevents effectively that the computer from inserting the electricity for the first time and will start the machine automatically.

Drawings

Fig. 1 is a schematic circuit flow diagram of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, a computer motherboard with a power-on logic level locking circuit includes a motherboard body, and further includes a bistable circuit, a nand gate circuit, an anti-interference isolation circuit, a surge protection circuit, and a pull-up resistor R1, which are located on the motherboard body, the surge protection circuit is located between PWRSW and PWRBTN, a first end of the pull-up resistor R1 is connected with a +3.3V power supply P1, a second end of the pull-up resistor R1 is connected with PWRBTN, the surge protection circuit is connected with the bistable circuit through the anti-interference isolation circuit, and the bistable circuit is connected with SIO _ PSON through the nand gate circuit.

Preferably, the bistable circuit includes a transistor Q1 and a transistor Q2, the nand circuit includes a transistor Q2 and a transistor Q3, the bistable circuit and the nand circuit share a transistor Q2, a D pole of the transistor Q1 is connected to the +3.3V power supply P2 through a third resistor R3, an S pole of the transistor Q1 is grounded, a G pole of the transistor Q1 is connected to a D pole of the transistor Q2 and a first end of a first capacitor C1, a second end of the first capacitor C1 is grounded, a G pole of the transistor Q2 is connected to the anti-interference isolation circuit and an S pole of the transistor Q3, a D pole of the transistor Q2 is further connected to the +3.3V power supply P3 through a fourth resistor R4, a D pole of the transistor Q3 is connected to the SIO _ PSON, a G pole of the transistor Q3 is connected to the SLP _ S3_ L

In this embodiment, PWRSW is a power-on button signal, and when pressed, PWRSW outputs a low level signal. PWRBTN is the PCH chip input signal of mainboard body, and when PWRBTN received the low level signal, think that the user has pressed the start button. The SLP _ S3_ L is a motherboard power control signal sent by the motherboard body, and outputs a high level signal when the power is turned on, and it should be noted that the SLP _ S3_ L outputs a high level signal when the power is plugged for the first time. The SIO _ PSON is a switching signal of the ATX power supply of the computer host, and when the SIO _ PSON receives the low level signal, the ATX power supply is turned on, and the computer host is turned on.

It should be noted that, after a manufacturer removes Super IO on a motherboard to reduce cost, the reason that the computer is automatically turned on when the computer is plugged in for the first time is that an SLP _ S3_ L signal sent by a PCH chip on the motherboard body is used to control the power-on state of the motherboard, when the SLP _ S3_ L signal is high, the motherboard is in the power-on state, when the SLP _ S3_ L signal is low, the motherboard is in the power-off state, but due to the operating mechanism of the PCH chip of the motherboard, when the computer is plugged in for the first time, the SLP _ S3_ L signal is high, which causes disorder of power-on logic.

In this embodiment, the transistor Q1 and the transistor Q2 form a bistable circuit, the transistor Q2 and the transistor Q3 form a nand gate, and the nand gate means that the D-pole of the transistor Q3 outputs a low level only when the G-poles of the transistor Q2 and the transistor Q3 are simultaneously high. When the power supply is plugged in a mainboard body of a computer, the three +3.3V power supplies power simultaneously, due to the delay effect of the first capacitor C1, the triode Q2 is firstly conducted, the D pole of the triode Q1 in the bistable circuit is locked in a high-level state, the D pole of the triode Q2 is in a low-level state, at the moment, the overturning condition of the NAND gate circuit formed by the triode Q2 and the triode Q3 is not established, namely the D pole of the triode Q3 is a high-level signal, the SIO _ PSON receives the high-level signal, the ATX power supply is not turned on, the host computer is not started, and at the moment, the problem that the computer can be automatically started when the power supply is plugged in for the first time.

When the power-on button PWRSW is pressed, a low-level signal is output, meanwhile, a D pole of the triode Q1 and a G pole of the triode Q2 also output low-level signals, at the moment, a D pole of the triode Q1 in the bistable circuit is low-level, a D pole of the triode Q2 is high-level, at the moment, the overturn condition of a NAND gate circuit formed by the triode Q2 and the triode Q3 is met, a D pole of the triode Q3 outputs a low-level signal, the SIO _ PSON receives the low-level signal, the ATX power supply is turned on, meanwhile, the PWRBTN also outputs a low-pulse signal to a PCH chip of the mainboard body, at the moment, all the power-on signals are in place, and the computer mainboard.

In this embodiment, the pull-up resistor R1 may provide a high level voltage for PWRSW, PWRBTN. The anti-jamming isolation circuit can prevent the high level of the PWRSW from causing interference to the bistable circuit. The surge protection circuit can absorb surge voltage on the circuit and prevent interference.

Preferably, the transistor Q1, the transistor Q2, and the transistor Q3 are N-channel transistors, respectively.

Preferably, the anti-interference isolation circuit comprises a diode D1, the cathode of the diode D1 is connected with the surge protection circuit, and the anode of the diode D1 is connected with the G pole of the triode Q2.

Preferably, the surge protection circuit includes a second resistor R2 and a second capacitor C2, a first end of the second resistor R2 is connected to a first end of the second capacitor C2, a negative electrode of the diode D1 and PWRSW, a second end of the second capacitor C2 is grounded, and a second end of the second resistor R2 is connected to a second end of the pull-up resistor R1 and PWRBTN.

The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A computer mainboard with a power-on logic level locking circuit comprises a mainboard body and is characterized by further comprising a bistable circuit, a NAND gate circuit, an anti-interference isolation circuit, a surge protection circuit and a pull-up resistor, wherein the bistable circuit, the NAND gate circuit, the anti-interference isolation circuit, the surge protection circuit and the pull-up resistor are located on the mainboard body, the surge protection circuit is located between PWRSW and PWRBTN, a first end of the pull-up resistor is connected with a +3.3V power supply, a second end of the pull-up resistor is connected with PWRBTN, the surge protection circuit is connected with the bistable circuit through the anti-interference isolation circuit, and the bistable circuit is connected with SIO _ PS.

2. The computer motherboard having a power-on logic level lock circuit as recited in claim 1 wherein: the bistable circuit comprises Q1 and Q2, the NAND gate circuit comprises Q2 and Q3, the bistable circuit and the NAND gate circuit share Q2, the D pole of Q1 is connected with a +3.3V power supply through R3, the S pole of Q1 is grounded, the G pole of Q1 is respectively connected with the D pole of Q2 and the first end of C1, the second end of C1 is grounded, the G pole of Q2 is respectively connected with an anti-interference isolation circuit and the S pole of Q3, the D pole of Q2 is further connected with a +3.3V power supply through R4, the D pole of Q3 is connected with SIO _ PSON, and the G pole of Q3 is connected with SLP _ S3_ L.

3. The computer motherboard having a power-on logic level lock circuit as recited in claim 2 wherein: and the Q1, the Q2 and the Q3 are N-channel triodes respectively.

4. The computer motherboard having a power-on logic level lock circuit as recited in claim 3 wherein: the anti-interference isolation circuit comprises a D1, the negative pole of the D1 is connected with the surge protection circuit, and the positive pole of the D1 is connected with the G pole of the Q2.

5. The computer motherboard having a power-on logic level lock circuit as recited in claim 4 wherein: the surge protection circuit comprises R2 and C2, wherein a first end of R2 is respectively connected with a first end of C2, a negative electrode of D1 and PWRSW, a second end of C2 is grounded, and a second end of R2 is respectively connected with a second end of a pull-up resistor and PWRBTN.