CN210629440U - Power tube grid driving circuit and integrated circuit - Google Patents
Power tube grid driving circuit and integrated circuit Download PDFInfo
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- CN210629440U CN210629440U CN201921550062.4U CN201921550062U CN210629440U CN 210629440 U CN210629440 U CN 210629440U CN 201921550062 U CN201921550062 U CN 201921550062U CN 210629440 U CN210629440 U CN 210629440U
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Abstract
The utility model discloses a power tube gate drive circuit for the grid of power tube provides gate drive signal, include: the control signal generating module is used for outputting a first control voltage signal and a second control voltage signal according to the control signal; the first driving voltage output module is used for outputting a first grid driving signal according to the drain voltage of the power tube, a first control voltage signal and a second control voltage signal; and the second driving voltage output module is used for outputting a second grid driving signal according to the first grid driving signal, the first control voltage signal and the second control voltage signal, and the second grid driving signal is used for driving the grid of the power tube. The utility model also discloses an integrated circuit. The on-resistance of the power tube when the low voltage is conducted can be reduced, and the conduction loss of the power tube is reduced.
Description
Technical Field
The utility model relates to a power tube control technical field, concretely relates to power tube grid drive circuit and integrated circuit.
Background
Power transistors are important components constituting various functional circuits, and are the most important active components in integrated circuits. In particular, the present invention has a very wide application as a core element of a DC/DC converter for high power applications, such as a BUCK regulator circuit (BUCK regulator circuit) and the like, and a push-pull output circuit. In the above applications, the power transistors are generally divided into PMOS power transistors and NMOS power transistors according to their conductivity types, and their gate driving circuits generally have similar structures.
Fig. 1 shows a block diagram of a gate driving circuit of a power transistor in the prior art, and fig. 2 shows a schematic diagram of a gate driving circuit of a power transistor in fig. 1, in the prior art, a drain of an NMOS power transistor MN1 is connected to a power supply terminal Vdd, a source is connected to an output terminal Vout, and a gate is connected to the gate driving circuit. As shown in fig. 1 and 2, the gate driver circuit 100 of the power transistor MN1 includes: a control signal generating module 110 and a driving voltage output module 120. The control signal generating module 110 is configured to output a first control voltage signal and a second control voltage signal according to the control signal Ctrl, and includes: a first inverter U1, a second inverter U2. The driving voltage output module 120 has a first input terminal connected to the power source terminal Vdd, a second input terminal connected to the control signal generating module 110, and an output terminal connected to the gate of the power transistor MN1, and is configured to output a gate driving signal to the gate of the power transistor MN1 according to the power source voltage, the first control voltage signal, and the second control voltage signal, and includes: the current source Icp, the first switch tube SW1, the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW 4.
The current source Icp, the first switch tube SW1 and the second switch tube SW2 are sequentially connected in series between a power supply terminal Vdd and the gate of the power tube MN1, and the third switch tube SW3 and the fourth switch tube SW4 are connected in series and then connected in parallel to two ends of the first switch tube SW1 and the second switch tube SW 2; the input end of the first inverter U1 receives the control signal Ctrl, and the output end thereof passes through the first capacitor C1 and then is connected between the first switch tube SW1 and the second switch tube SW 2; the input end of the second inverter U2 is connected to the output end of the first inverter U1, and the output end of the second inverter U2 is connected to the third switching tube SW3 and the fourth switching tube SW4 after passing through the second capacitor C2. Meanwhile, the output signal of the first inverter U1 controls the third switching tube SW3 and the fourth switching tube SW4 to be turned off, and the output signal of the second inverter U2 controls the first switching tube SW1 and the second switching tube SW2 to be turned off.
Theoretically, the maximum output voltage of the gate control circuit is equal to Vdd + Vdd — 2 Vdd. When the drain of the power transistor MN1 receives a voltage input of 1.5V, its gate voltage Vgate is 3V. Since the power transistor MN1 operates in the linear region in practical applications, it can be known that the source output voltage Vout of the power transistor MN1 is approximately equal to the drain voltage 1.5V. Generally, the on-threshold voltage Vth of the power transistor MN1 is 0.7V, and then the overdrive voltage Vdsat _ 1.5V-Vgs-Vth-Vgate-Vout-Vth-0.8V of the power transistor MN 1. Similarly, when the drain of the power transistor MN1 is input with a voltage of 5V, the overdrive voltage Vdsat _ 5V-Vth-Vgate-Vout-Vth-4.3V of the power transistor MN1 is obtained. According to the formula of the on-resistance of the linear region of the MOS tube:
and the above derived magnitude relationship between the overdrive voltage Vdsat _1.5V when the drain of the power transistor MN1 is input at 1.5V and the overdrive voltage Vdsat _5V when the drain of the power transistor MN1 is input at 5V can be known: the on-resistance of the drain of the power tube MN1 when the voltage of 1.5V is input is much larger than that of the drain of the power tube MN1 when the voltage of 5V is input. That is, the on-resistance of the NMOS power transistor MN1 at the low voltage input is much larger than the on-resistance of the NMOS power transistor MN1 at the high voltage input.
If the gate driving circuit of the power transistor in the conventional technology is adopted, a large conduction loss is generated when the NMOS power transistor is turned on at a low voltage.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a power tube grid drive circuit and integrated circuit can reduce the on-resistance of power tube when the low-voltage switches on, reduces the conduction loss of power tube.
According to the utility model provides a pair of power tube gate drive circuit is connected with the grid of power tube, be used for doing the grid of power tube provides grid drive signal, include: the control signal generating module is connected with the input end of the control signal and used for receiving the control signal and outputting a first control voltage signal and a second control voltage signal according to the control signal, wherein the first control voltage signal and the second control voltage signal are high level at the same time within a certain time; a first driving voltage output module, a first input end of which is connected with the drain electrode of the power tube, and a second input end of which is connected with the control signal generation module, and is used for outputting a first gate driving signal according to the drain electrode voltage of the power tube, the first control voltage signal and the second control voltage signal; and the first input end of the second driving voltage output module is connected with the output end of the first driving voltage output module, the second input end of the second driving voltage output module is connected with the control signal generation module, and the output end of the second driving voltage output module is connected with the grid electrode of the power tube and used for outputting a second grid electrode driving signal according to the first grid electrode driving signal, the first control voltage signal and the second control voltage signal.
Preferably, the power tube is an NMOS power tube.
Preferably, the control signal generating module includes: the input end of the first phase inverter is connected with the control signal input end, and the output end of the first phase inverter is respectively connected with a first capacitor and a third capacitor so as to output the first control voltage signal through the first capacitor or the third capacitor; and the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is respectively connected with the second capacitor and the fourth capacitor so as to output the second control voltage signal through the second capacitor or the fourth capacitor.
Preferably, the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all active capacitors.
Preferably, the first driving voltage output module includes: the first switch and the second switch are sequentially connected in series between the drain electrode of the power tube and the output end of the first driving voltage output module, and the control end receives the second control voltage signal; the third switch and the fourth switch are sequentially connected in series between the drain electrode of the power tube and the output end of the first driving voltage output module, and the control end receives the first control voltage signal, wherein the control end of the first switch and the control end of the second switch are connected with the output end of the first driving voltage output module through the fourth switch, and the control end of the third switch and the control end of the fourth switch are connected with the output end of the first driving voltage output module through the second switch.
Preferably, the first driving voltage output module further includes: and the current source is connected between the drain electrode of the power tube and the first switch or the third switch.
Preferably, the second driving voltage output module includes: the fifth switch and the sixth switch are sequentially connected in series between the output end of the first driving voltage output module and the grid of the power tube, and the control end receives the second control voltage signal; a seventh switch and an eighth switch sequentially connected in series between the output end of the first driving voltage output module and the gate of the power transistor, wherein the control end receives the first control voltage signal, the control ends of the fifth switch and the sixth switch are connected with the gate of the power transistor through the eighth switch, and the control ends of the seventh switch and the eighth switch are connected with the gate of the power transistor through the sixth switch
According to the utility model provides a pair of integrated circuit, a serial communication port, include: the drain electrode of the power tube is connected with the signal input end, and the source electrode of the power tube is connected with the signal output end; the power tube gate driving circuit is connected with the gate of the power tube and used for providing a gate driving signal to control the on-off of the power tube.
Preferably, the power tube is an NMOS power tube.
Preferably, the integrated circuit comprises a switching power supply circuit, an audio amplification circuit, a direct current motor driving circuit and a power output circuit
The utility model has the advantages that: the utility model discloses set up first drive voltage output module and second drive voltage output module in the gate drive circuit of power tube, through the output drive voltage who improves gate drive circuit, further improved the overdrive voltage of power tube, and then reduced the on-resistance of power tube when the low-voltage switches on, reduced the conduction loss of power tube.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a block diagram of a gate driving circuit of a power transistor in the prior art;
fig. 2 is a schematic structural diagram of a gate driving circuit of the power transistor in fig. 1;
fig. 3 shows a block diagram of a power transistor gate driving circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a gate driving circuit of the power transistor in fig. 3.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 3 shows a block diagram of a gate driving circuit of a power transistor according to an embodiment of the present invention, and fig. 4 shows a schematic structural diagram of the gate driving circuit of the power transistor in fig. 3.
In this embodiment, the power transistor gate driving circuit 200 (hereinafter referred to as the gate driving circuit 200) is connected to the gate of the power transistor MN1, and is configured to provide a gate driving signal to the gate of the power transistor MN1, and the power transistor MN1 operates in different states according to the gate driving signal.
As shown in fig. 3 and 4, in the present embodiment, the drain of the power transistor MN1 is connected to the power supply terminal Vdd, the source is connected to the output terminal Vout, and the gate is connected to the gate driving circuit 200. The power transistor MN1 is an NMOS power transistor.
In an embodiment of the present invention, the gate driving circuit 200 of the power transistor MN1 includes a control signal generating module 210, a first driving voltage output module 220, and a second driving voltage output module 230.
The input end of the control signal generating module 210 is connected to the input end of the control signal Ctrl, and is configured to receive the control signal Ctrl and output a first control voltage signal and a second control voltage signal according to the control signal Ctrl.
In this embodiment, the control signal generating module 210 includes: a first inverter U1 and a second inverter U2. The first inverter U1 and the second inverter U2 are respectively connected with a power supply terminal Vdd and a ground terminal; the input end of the first inverter U1 is connected to the input end of the control signal Ctrl, and the output end of the first inverter U1 is connected to the first capacitor C1 and the third capacitor C3, respectively, so as to output a first control voltage signal through the first capacitor C1 or the third capacitor C3; an input end of the second inverter U2 is connected to an output end of the first inverter U1, and an output end of the second inverter U2 is connected to the second capacitor C2 and the fourth capacitor C4, respectively, so as to output a second control voltage signal through the second capacitor C2 or the fourth capacitor C4.
Preferably, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all active capacitors.
Further, since the power source terminal voltage values of the first inverter U1 and the second inverter U2 are both Vdd, when the first inverter U1 and the second inverter U2 output the control voltage signal of high level, the voltage value of the output control voltage signal is approximately equal to the power source terminal output voltage Vdd.
The first driving voltage output module 220 has a first input terminal connected to the drain of the power transistor MN1, and a second input terminal connected to the control signal generating module 210, and is configured to output a first gate driving signal according to the drain voltage of the power transistor MN1, the first control voltage signal, and the second control voltage signal.
Further, in the present embodiment, the drain voltage of the power transistor MN1 is equal to the power supply voltage Vdd.
In this embodiment, the first driving voltage output module 220 includes: a first switching tube SW1, a second switching tube SW2, a third switching tube SW3 and a fourth switching tube SW 4. The first switch tube SW1 and the second switch tube SW2 are sequentially connected in series between the drain of the power tube MN1 and the output end of the first driving voltage output module 220, and the third switch tube SW3 and the fourth switch tube SW4 are sequentially connected in series between the drain of the power tube MN1 and the output end of the first driving voltage output module 220; the control terminals of the first switch SW1 and the second switch SW2 are connected to the control signal generating module 210 through the second capacitor C2, and connected to the output terminal of the first driving voltage output module 220 through the fourth switch SW4, so as to receive the second control voltage signal, and turn on/off according to the second control voltage signal; the control terminals of the third switch tube SW3 and the fourth switch tube SW4 are connected to the control signal generating module 210 through the first capacitor C1, and connected to the output terminal of the first driving voltage output module 220 through the second switch tube SW2, for receiving the first control voltage signal, and turning on/off according to the first control voltage signal.
Further, the first driving voltage output module 220 further includes a current source Icp connected between the drain of the power transistor MN1 and the first switch SW1 or the third switch SW 3.
The first input terminal of the second driving voltage output module 230 is connected to the output terminal of the first driving voltage output module 220, the second input terminal is connected to the control signal generating module 210, and the output terminal is connected to the gate of the power transistor MN1, and is configured to output a second gate driving signal according to the first gate driving signal, the first control voltage signal, and the second control voltage signal. The second gate driving signal is used to drive the gate of the power transistor MN 1.
In this embodiment, the second driving voltage output module 230 includes: a fifth switching tube SW5, a sixth switching tube SW6, a seventh switching tube SW7 and an eighth switching tube SW 8. The fifth switching tube SW5 and the sixth switching tube SW6 are sequentially connected in series between the output end of the first driving voltage output module 220 and the gate of the power tube MN1, and the seventh switching tube SW7 and the eighth switching tube SW8 are sequentially connected in series between the output end of the first driving voltage output module 220 and the gate of the power tube MN 1; the control terminals of the fifth switch SW5 and the sixth switch SW6 are connected to the control signal generating module 210 through the fourth capacitor C4, and connected to the gate of the power transistor MN1 through the eighth switch SW8, so as to receive the second control voltage signal, and turn on/off according to the second control voltage signal; the control terminals of the seventh switch SW7 and the eighth switch SW8 are connected to the control signal generating module 210 through the third capacitor C3, and connected to the gate of the power transistor MN1 through the sixth switch SW6, for receiving the first control voltage signal and turning on/off according to the first control voltage signal.
In this embodiment, when the control signal Ctrl is at a high level, the output signal of the inverter U1 is at a low level, and the output signal of the inverter U2 is at a high level. The output signal of the inverter U2 is charged by the second capacitor C2, so that the second control voltage signal is high, and the first control voltage signal is low.
When the control signal Ctrl changes from high to low, the output signal of the inverter U1 is high, and the output signal of the inverter U2 is low. The output signal of the inverter U1 is charged by the first capacitor C1 to make the first control voltage signal high, and the second control voltage signal is still high for a certain time due to the discharging action of the second capacitor C2. Similarly, when the control signal Ctrl changes from low level to high level, the second control voltage signal is at high level, and the first control voltage signal is still at high level for a certain time due to the discharging function of the first capacitor C1.
In summary, when the control signal Ctrl performs a voltage jump, due to the charging and discharging characteristics of the capacitor, the output control voltage signal of the control signal generation module 210 has a certain delay characteristic, that is, the first control voltage signal and the second control voltage signal are at a high level at the same time within a certain time range. In this time range, the maximum output voltage of the first driving voltage output module 220 is added to the input voltage by the voltage value when the first control voltage signal/the second control voltage signal is at the high level. Similarly, the maximum output voltage of the second driving voltage output module 230 is added to the input voltage thereof with the voltage value of the first control voltage signal/the second control voltage signal at the high level.
Further, when the first control voltage signal and the second control voltage signal are at a high level, the voltage value thereof is approximately equal to the power source terminal input voltage Vdd.
Therefore, in the present embodiment, the maximum output voltage of the gate driving circuit 200 is equal to 3 Vdd. When the drain of the power transistor MN1 receives the input of the voltage Vdd of 1.5V, the gate driving voltage Vgate thereof is 4.5V. Since the power transistor MN1 operates in the linear region in practical applications, it can be known that the source output voltage Vout of the power transistor MN1 is approximately equal to the drain voltage 1.5V. Generally, the on-threshold voltage Vth of the power transistor MN1 is 0.7V, and then the overdrive voltage Vdsat _ 1.5V-Vgs-Vth-Vgate-Vout-Vth-2.3V of the power transistor MN 1.
Referring to fig. 2, in the gate driving circuit 100 of the prior art power transistor MN1, the overdrive voltage of the power transistor MN1 is 0.8V under the same drain input voltage of 1.5V. Thus, in contrast, it can be found that: when the second driving signal output module 230 is added to the original gate driving circuit 100, the overdrive voltage of the power transistor MN1 is increased, and then according to the formula of the MOS transistor linear region on-resistance:
it can be seen that the on-resistance of the power transistor MN1 is reduced in the case of low voltage conduction.
In another embodiment of the present invention, a third driving voltage output module may be further disposed between the second driving voltage output module 230 of the power transistor gate driving circuit 200 and the gate of the power transistor MN1, and the third driving voltage output module is similar to the second driving voltage output module 220 in structure and connection relationship. By providing the third driving voltage output module, the low-voltage on-resistance of the power transistor MN1 can be further reduced, but the power consumption of the circuit is also increased. Further, when the number of the driving voltage output modules increases, the number of the output terminals and the number of the capacitors of the control signal generating module 210 should also be increased accordingly.
In a similar way, the technical solution of setting more driving voltage output modules between the second driving voltage output module of the power transistor gate driving circuit 200 and the gate of the power transistor MN1 should also be within the protection scope of the present invention. In practical application, the most appropriate number of driving voltage output modules should be selected according to comprehensive factors such as power consumption and on-resistance.
The utility model also discloses an integrated circuit, including the power tube and as in fig. 3 and the grid drive circuit in fig. 4, the signal input part is connected to the drain electrode of power tube, and signal output part is connected to the source electrode, and the grid is connected with grid drive circuit. The grid driving circuit is used for providing a grid driving signal for the grid of the power tube, and the power tube receives the grid driving signal and is switched on or switched off according to the grid driving signal, so that the output control of a drain electrode input signal is realized.
Furthermore, the power tube is an NMOS power tube.
Further, the integrated circuit includes, but is not limited to: the device comprises a switching power supply circuit, an audio amplification circuit, a direct current motor driving circuit and a power output circuit. All use in the circuit the power tube with the utility model discloses a power tube grid drive circuit's integrated circuit all should be within the protection scope of the utility model.
In this embodiment, the gate driver circuit shown in fig. 3 and 4 is used in an integrated circuit, so that the operating loss of the integrated circuit is reduced.
To sum up, the utility model discloses set up first drive voltage output module and second drive voltage output module in the gate drive circuit of power tube, through the output drive voltage who improves gate drive circuit, further improved the overdrive voltage of power tube, and then reduced the on-resistance of power tube when the low-voltage switches on, reduced the conduction loss of power tube.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications may be made without departing from the scope of the present invention.
Claims (10)
1. A power tube grid driving circuit is connected with a grid of a power tube and used for providing a grid driving signal for the grid of the power tube, and the power tube grid driving circuit is characterized by comprising:
the control signal generating module is connected with the input end of the control signal and used for receiving the control signal and outputting a first control voltage signal and a second control voltage signal according to the control signal, wherein the first control voltage signal and the second control voltage signal are high level at the same time within a certain time;
a first driving voltage output module, a first input end of which is connected with the drain electrode of the power tube, and a second input end of which is connected with the control signal generation module, and is used for outputting a first gate driving signal according to the drain electrode voltage of the power tube, the first control voltage signal and the second control voltage signal; and
and the first input end of the second driving voltage output module is connected with the output end of the first driving voltage output module, the second input end of the second driving voltage output module is connected with the control signal generation module, and the output end of the second driving voltage output module is connected with the grid electrode of the power tube and used for outputting a second grid electrode driving signal according to the first grid electrode driving signal, the first control voltage signal and the second control voltage signal.
2. The power transistor gate driver circuit of claim 1, wherein the power transistor is an NMOS power transistor.
3. The power tube gate driving circuit according to claim 1, wherein the control signal generating module comprises:
the input end of the first phase inverter is connected with the control signal input end, and the output end of the first phase inverter is respectively connected with a first capacitor and a third capacitor so as to output the first control voltage signal through the first capacitor or the third capacitor; and
and the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is respectively connected with the second capacitor and the fourth capacitor so as to output the second control voltage signal through the second capacitor or the fourth capacitor.
4. The power tube gate drive circuit according to claim 3, wherein the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all active capacitors.
5. The power tube gate driving circuit according to claim 1, wherein the first driving voltage output module comprises:
the first switch and the second switch are sequentially connected in series between the drain electrode of the power tube and the output end of the first driving voltage output module, and the control end receives the second control voltage signal;
a third switch and a fourth switch which are sequentially connected in series between the drain electrode of the power tube and the output end of the first driving voltage output module, a control end receives the first control voltage signal,
the control ends of the first switch and the second switch are connected with the output end of the first driving voltage output module through the fourth switch, and the control ends of the third switch and the fourth switch are connected with the output end of the first driving voltage output module through the second switch.
6. The power tube gate drive circuit of claim 5, wherein the first drive voltage output module further comprises:
and the current source is connected between the drain electrode of the power tube and the first switch or the third switch.
7. The power tube gate driving circuit according to claim 1, wherein the second driving voltage output module comprises:
the fifth switch and the sixth switch are sequentially connected in series between the output end of the first driving voltage output module and the grid of the power tube, and the control end receives the second control voltage signal;
a seventh switch and an eighth switch which are sequentially connected in series between the output end of the first driving voltage output module and the grid of the power tube, a control end receives the first control voltage signal,
the control ends of the fifth switch and the sixth switch are connected with the grid electrode of the power tube through the eighth switch, and the control ends of the seventh switch and the eighth switch are connected with the grid electrode of the power tube through the sixth switch.
8. An integrated circuit, comprising:
the drain electrode of the power tube is connected with the signal input end, and the source electrode of the power tube is connected with the signal output end;
the power tube gate drive circuit as claimed in any one of claims 1 to 7, connected to the gate of the power tube, for providing a gate drive signal to control the on/off of the power tube.
9. The integrated circuit of claim 8, wherein the power transistor is an NMOS power transistor.
10. The integrated circuit of claim 8, wherein the integrated circuit comprises a switching power supply circuit, an audio amplification circuit, a dc motor drive circuit, and a power output circuit.
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| CN201921550062.4U CN210629440U (en) | 2019-09-17 | 2019-09-17 | Power tube grid driving circuit and integrated circuit |
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| CN201921550062.4U CN210629440U (en) | 2019-09-17 | 2019-09-17 | Power tube grid driving circuit and integrated circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114520584A (en) * | 2020-11-20 | 2022-05-20 | 圣邦微电子（北京）股份有限公司 | Driving circuit and driving method of power tube and switching circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114520584A (en) * | 2020-11-20 | 2022-05-20 | 圣邦微电子（北京）股份有限公司 | Driving circuit and driving method of power tube and switching circuit |
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