CN210575959U

CN210575959U - Display panel and display device

Info

Publication number: CN210575959U
Application number: CN201922034615.7U
Authority: CN
Inventors: 青海刚; 肖云升
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2019-11-22
Filing date: 2019-11-22
Publication date: 2020-05-19
Anticipated expiration: 2029-11-22

Abstract

The utility model provides a display panel and display device. The display panel comprises a test circuit, and a signal lead wire is arranged between the first end of the test circuit and the input end of the test circuit; the test circuit comprises a first test sub-circuit and a second test sub-circuit; the first test sub-circuit comprises a first test sub-line and a second test sub-line, and the second test sub-circuit comprises a third test sub-line; the orthographic projection of the signal lead on the substrate base plate is not overlapped with the orthographic projection of the second test sub-wire on the substrate base plate; the orthographic projection of the signal lead on the substrate base plate is at least partially overlapped with the orthographic projection of the third test sub-wire on the substrate base plate. The utility model provides an adopt the individual layer test to walk the line among the correlation technique to the high problem that leads to the panel to burn easily of heat generation when ageing treatment.

Description

Display panel and display device

Technical Field

The utility model relates to a show technical field, especially relate to a display panel and display device.

Background

With the maturity of the AMOLED (Active-matrix organic light-emitting diode) technology, the use of the AMOLED display in the mobile terminal is more and more common, and the market has a more and more narrow requirement on the lower frame of the AMOLED screen, which leads to a problem that the line width of the panel test signal line located on the lower frame of the AMOLED screen is also thinner and thinner, and related designs all use a single-layer metal-routing test signal line, in the aging process of panel production, a higher voltage is applied to the panel test signal line, so as to perform aging processing on the devices in the panel, in this process, because the loaded voltage is higher, the current flowing through the test circuit signal line is larger, when the line width is thinned, the resistance is increased, the heat productivity of the test circuit signal line is also increased, and because the heat is not conducted away in a local area, the temperature is rapidly increased, when the temperature is higher than the temperature endured by the organic film layer of the panel, burn may occur in the area.

SUMMERY OF THE UTILITY MODEL

A primary object of the present invention is to provide a display panel and a display device, which solve the problem of the related art in which a single layer test is adopted to run the wires, thereby easily causing the burn of the panel due to the high heat generation amount during the aging process.

In order to achieve the above object, the present invention provides a display panel, which includes a substrate, and a test circuit disposed on the substrate; the display panel further comprises a test circuit, wherein a first end of the test circuit is electrically connected with the first test pin, a second end of the test circuit is electrically connected with an input end of the test circuit, and the display panel further comprises a signal lead between the first end of the test circuit and the input end of the test circuit;

the test circuit comprises a first test sub-circuit and a second test sub-circuit electrically connected with the first test sub-circuit;

the first test sub-circuit comprises a first test sub-line and a second test sub-line electrically connected with the first test sub-line, and the second test sub-circuit comprises a third test sub-line;

the orthographic projection of the signal lead on the substrate base plate is not overlapped with the orthographic projection of the second test sub-wire on the substrate base plate;

the orthographic projection of the signal lead on the substrate base plate is at least partially overlapped with the orthographic projection of the third test sub-wire on the substrate base plate.

In implementation, the first test sub-trace and the second test sub-trace are located at different layers.

In implementation, at least a part of orthographic projections of the first test sub-trace and the second test sub-trace on the substrate are overlapped.

In implementation, the second test sub-circuit further comprises a conversion sub-line and a connection sub-line; the conversion sub-wire is electrically connected with the third test sub-wire;

the conversion sub-wiring comprises a first sub-wiring and a second sub-wiring; the second sub-wiring is electrically connected with the connecting sub-wiring; the connecting sub-wire is electrically connected with the input end of the test circuit;

the first sub-wiring and the second sub-wiring are located on different layers, and the first sub-wiring is electrically connected with the second sub-wiring;

the second sub-wiring and the connecting sub-wiring are positioned on the same layer;

the orthographic projection of the first sub-routing on the substrate base plate is at least partially not overlapped with the orthographic projection of the second sub-routing on the substrate base plate.

When the second sub-wiring is implemented, the second sub-wiring and the connecting sub-wiring are of an integrated structure.

When the integrated structure is implemented, the orthographic projection of the integrated structure on the substrate base plate covers the orthographic projection of the first sub-wires on the substrate base plate.

In implementation, the orthographic projection of the signal lead on the substrate base plate and the orthographic projection of the connecting sub-trace on the substrate base plate are not overlapped.

In implementation, the connecting sub-trace and the second testing sub-trace are arranged on the same layer.

In implementation, the connecting sub-trace is electrically connected to the second testing sub-trace.

When in implementation, the display panel of the utility model also comprises an auxiliary test pin; the auxiliary test pin is electrically connected with the second sub-routing.

In implementation, the conversion sub-trace further comprises a third sub-trace; the third sub-wiring is electrically connected with the second sub-wiring;

the first sub-routing and the third sub-routing are located on different layers, and the second sub-routing and the third sub-routing are located on different layers.

In practice, the signal lead is a power supply voltage signal line.

In implementation, the first test sub-line further comprises a fourth test sub-line;

the fourth test sub-trace and the first test sub-trace are located at different layers, and the fourth test sub-trace and the second test sub-trace are located at different layers;

the fourth test sub-trace is electrically connected to the first test sub-trace.

In implementation, at least a part of orthographic projections of the fourth test sub-trace and the second test sub-trace on the substrate are overlapped.

In implementation, the second test sub-line further includes a fifth test sub-line; the fifth test sub-trace is electrically connected with the third test sub-trace;

the fifth test sub-trace and the third test sub-trace are located at different layers;

the orthographic projection of the signal lead on the substrate base plate is at least partially overlapped with the orthographic projection of the fifth test sub-wire on the substrate base plate.

In implementation, the display panel comprises a first metal graphic layer, a second metal graphic layer and a third metal graphic layer;

the first test sub-wire and the first metal pattern layer are arranged on the same layer, the fourth test sub-wire and the second metal pattern layer are arranged on the same layer, and the second test sub-wire and the third metal pattern layer are arranged on the same layer.

In implementation, the first test sub-trace, the third test sub-trace and the first metal pattern layer are included in a first metal layer, the fourth test sub-trace and the second metal pattern layer are included in a second metal layer, and the second test sub-trace and the third metal pattern layer are included in a third metal layer;

a first insulating layer is arranged between the first metal layer and the second metal layer, and a second insulating layer is arranged between the second metal layer and the third metal layer;

the second testing sub-wire is electrically connected with the fourth testing sub-wire through a first via hole penetrating through the second insulating layer;

the second testing sub-trace is electrically connected with the first testing sub-trace through at least one second via hole penetrating through the second insulating layer, the second metal layer and the first insulating layer.

In implementation, the second test sub-line further includes a fifth test sub-line; the fifth test sub-trace and the third test sub-trace are located at different layers;

the orthographic projection of the signal lead on the substrate base plate is at least partially overlapped with the orthographic projection of the fifth test sub-wire on the substrate base plate;

the fifth test sub-trace is included in the second metal layer.

In implementation, the second test sub-circuit further comprises a conversion sub-line and a connection sub-line; the conversion sub-wiring comprises a first sub-wiring and a second sub-wiring; the conversion sub-wire is electrically connected with the third test sub-wire; the first sub-wiring is electrically connected with the second sub-wiring; the second sub-routing is electrically connected with the input end of the test circuit;

the second sub-trace and the connecting sub-trace are contained in the third metal layer;

the first sub-trace is included in the first metal layer.

the third sub-trace is included in the second metal layer.

In implementation, the first metal layer is a first gate metal layer, the second metal layer is a second gate metal layer, and the third metal layer is a source-drain metal layer.

In practice, the display panel includes a display driving circuit;

the display driving circuit comprises a thin film transistor and a storage capacitor;

the first metal pattern layer comprises a grid electrode pattern layer of the thin film transistor, the second metal pattern layer comprises an electrode pattern layer of the storage capacitor, and the third metal layer comprises a source electrode pattern layer of the thin film transistor and a drain electrode pattern layer of the thin film transistor.

The utility model also provides a display device, including foretell display panel.

Compared with the related art, the display panel and the display device of the invention comprise a test circuit, the test circuit comprises a first test sub-circuit and a second test sub-circuit which are electrically connected with each other, the first test sub-circuit comprises a first test sub-circuit and a second test sub-circuit which are electrically connected with each other, the second test sub-circuit comprises a third test sub-circuit, the first test sub-circuit can be a laminated sub-circuit, the orthographic projection of the signal lead on the substrate is not overlapped with the orthographic projection of the second test sub-circuit on the substrate, the orthographic projection of the signal lead on the substrate is at least partially overlapped with the orthographic projection of the third test sub-circuit on the substrate, so that the signal lead can utilize the wiring space of the test circuit, and at least one part of the test circuit can adopt the multilayer design to reduce the circuit burning loss, the heat generated in the aging process is rapidly dispersed and led out, so that the problem that the panel is easily burnt due to high heat of a single-layer test wire is solved.

Drawings

Fig. 1 is a schematic diagram of the test circuit 11, the test line L1, the data test pin CTD, and the scan test pin CTSW included in the display panel 10;

fig. 2A is a structural diagram of an embodiment of a test circuit included in a display panel according to an embodiment of the present invention;

FIG. 2B is a block diagram of the addition of signal leads to the embodiment of the test circuit shown in FIG. 2A;

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a display panel according to another embodiment of the present invention;

FIG. 5A is a schematic diagram of a third orthographic projection S3 of a fourth test sub-trace on the substrate base plate;

FIG. 5B is a schematic diagram of a second orthographic projection S2 of a second test sub-trace on the substrate base plate;

FIG. 5C is a schematic view of a first orthographic projection S1 of a first test sub-trace on the substrate base plate;

fig. 6 is a schematic diagram of an orthographic projection of each test sub-wire included in the first test sub-circuit on the substrate base (the orthographic projection includes a first orthographic projection S1, a second orthographic projection S2, and a third orthographic projection S3), an orthographic projection of the first via on the substrate base, and an orthographic projection of the second via on the substrate base;

fig. 7 is a schematic structural diagram of an embodiment of a test circuit included in the display panel according to the present invention;

3 FIG. 3 8 3 is 3 a 3 sectional 3 view 3 A 3- 3 A 3' 3 of 3 FIG. 3 7 3; 3

Fig. 9A is a circuit diagram of an embodiment of a display driving circuit in a display panel according to an embodiment of the present invention;

fig. 9B is a circuit diagram of another embodiment of a display driving circuit in a display panel according to an embodiment of the present invention;

fig. 10 is a structural diagram of a display panel according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The transistors adopted in all the embodiments of the utility model can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, to distinguish the two electrodes of the transistor except the control electrode, one of the two electrodes is referred to as a first electrode, and the other electrode is referred to as a second electrode.

In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

The embodiment of the utility model provides a display panel, including the substrate base plate to and, set up the test circuit on the substrate base plate; the display panel further comprises a test circuit, wherein a first end of the test circuit is electrically connected with the first test pin, a second end of the test circuit is electrically connected with an input end of the test circuit, and the display panel further comprises a signal lead between the first end of the test circuit and the input end of the test circuit;

The embodiment of the present invention provides an embodiment, the first test pin can be a data test pin, and the test data voltage signal is accessed, but not limited thereto.

The embodiment of the utility model provides a display panel include the test line, the test line includes first test sub-line and the second test sub-line that mutual electricity is connected, first test sub-line includes first test sub-line and the second test sub-line that mutual electricity is connected, the second test sub-line includes the third test sub-line, first test sub-line can be the stromatolite sub-line, the signal lead wire is in orthographic projection on the substrate base plate with the second test sub-line is in orthographic projection on the substrate base plate is not overlapped, the signal lead wire is in orthographic projection on the substrate base plate with the third test sub-line is in orthographic projection on the substrate base plate at least partly overlaps for the signal lead wire can utilize the line space of test line, and make test line have at least partly can adopt the multilayer design in order to reduce the circuit burning loss, the heat generated in the aging process is rapidly dispersed and led out, so that the problem that the panel is easily burnt due to high heat of a single-layer test wire is solved.

In the embodiment of the present invention, the signal lead may be a power voltage signal line for providing the first power voltage signal VDD or the second power voltage signal VSS, but not limited thereto.

In specific implementation, the power supply voltage signal line may be located at the same layer as the second test sub-trace;

the power supply voltage signal line and the first test sub-line can be located at different layers; therefore, the orthographic projection of the power supply voltage signal wire on the substrate is set to be not overlapped with the orthographic projection of the second test sub-wire on the substrate, so that the power supply voltage signal wire and the second test sub-wire are not short-circuited;

and the power supply voltage signal line and the third testing sub-line may be located at different layers, and an orthographic projection of the power supply voltage signal line on the substrate is set to be at least partially overlapped with an orthographic projection of the third testing sub-line on the substrate, so that the power supply voltage signal line can utilize a line space of the testing line.

In the embodiment of the present invention, the power voltage signal line and the second test sub-line are located the same layer and indicate can be: the power voltage signal line and the second test sub-trace are formed by a single patterning process, but not limited thereto.

In an embodiment of the present invention, the power supply voltage signal line and the first testing sub-line are located at different layers and can be: the power supply voltage signal line and the first test sub-wire are made of two metal layers through different composition processes, but not limited to;

the indication that the power supply voltage signal line and the third test sub-line are located at different layers may be: the power voltage signal line and the third testing sub-trace are made of two metal layers through different patterning processes, but not limited thereto.

And the first testing sub-line and the second testing sub-line included in the first testing sub-line are positioned on different layers, namely the first testing sub-line is a laminated sub-line, so that heat generated in an aging process can be rapidly dispersed and rapidly led out, and the problem that a panel is easily burnt due to high heat of a single-layer testing sub-line is solved.

Specifically, the first test sub-trace and the second test sub-trace may be located at different layers.

In an embodiment of the present invention, the first testing sub-trace and the second testing sub-trace located on different layers may be: the first test sub-trace and the second test sub-trace are made of two metal layers through different patterning processes, but not limited thereto.

In specific implementation, at least a part of orthographic projections of the first test sub-trace and the second test sub-trace on the substrate can be overlapped, so that a smaller trace space can be occupied.

The embodiment of the utility model provides an in, because first test son walk the line with second test son walks the line and is located different layers, then first test son walk the line with second test son walks the line and is in can at least part overlap between the orthographic projection on the substrate base plate to save wiring space.

Under the preferable condition, the orthographic projection of the first testing sub-wiring on the substrate and the orthographic projection of the second testing sub-wiring on the substrate can be overlapped, so that the problem that the single-layer testing wiring is high in heat quantity and easily causes panel burn can be avoided under the condition that wiring space is not increased.

In an implementation, the test line may be a data test line, but is not limited thereto.

In fig. 1, reference numeral AA is an effective display area of the display panel 10, reference numeral 11 is a test circuit, reference numeral CTD is a data test pin, and reference numeral CTSW is a scan test pin;

the test circuit 11 may be disposed on a lower frame of the display panel 10;

the test circuit 11 includes a plurality of test transistors, a control electrode of each test transistor is electrically connected to a scan test pin CTSW, a first electrode of each test transistor is electrically connected to a data test pin CTD, the data test pin CTD is used for providing a test data voltage, and a test line L1 between the data test pin CTD and the test circuit 11 is easily burned by a large current.

In fig. 1, the first test pin is the data test pin CTD;

a first end of the test line L1 is electrically connected to the data test pin CTD, and a second end of the test line L1 is electrically connected to the input end of the test circuit 11.

As shown in fig. 2A, the display panel according to the embodiment of the present invention includes a test circuit, where the test circuit includes a first test sub-circuit S21 and a second test sub-circuit electrically connected to the first test sub-circuit S21; the second test sub-line comprises a third test sub-trace S22;

the first end of the first test sub-circuit S21 is electrically connected with a first test pin P1;

the first test sub-line S21 is electrically connected to the third test sub-trace S22.

In the embodiment shown in FIG. 2A, the first test sub-line S21 may be a laminated sub-line.

In fig. 2A, the first test sub-line S21 is a two-layer test sub-line, but not limited thereto. In actual operation, the first test sub-circuit S21 may be a three-layer test sub-circuit, but is not limited thereto.

In the embodiment of the present invention, the first test pin P1 may be a data test pin, but not limited thereto.

In fig. 2B, a first signal lead X1 and a second signal lead X2 are added on the basis of the embodiment of the test circuit shown in fig. 2A.

In a specific implementation, the first signal lead X1 and the second signal lead X2 may be power supply voltage signal leads.

According to an embodiment, the first and second signal leads X1 and X2 may be used to supply a cathode voltage VSS, in which case the first and second signal leads X1 and X2 are introduced to a peripheral region of the display panel to overlap with the cathode.

According to another embodiment, the first signal lead X1 and the second signal lead X2 may be used to provide a power voltage signal VDD, and the first signal lead X1 and the second signal lead X2 may be introduced into a display region of a display panel to provide the power voltage signal VDD to a display driving circuit.

In particular implementation, the display panel may include a first metal layer, a second metal layer, and a third metal layer;

the first metal layer includes a first test sub-trace and a third test sub-trace, and the third metal layer includes a second test sub-trace, but not limited thereto.

In an embodiment of the present invention, the third metal layer may include the signal lead, but is not limited thereto.

The embodiment of the present invention provides a method for manufacturing a semiconductor device, which comprises a substrate, a first metal layer, a second metal layer, a third metal layer, a gate metal layer, a.

In practical operation, a first insulating layer may be disposed between the first metal layer and the second metal layer, and a second insulating layer may be disposed between the second metal layer and the third metal layer, but not limited thereto.

As shown in fig. 3, the display panel according to the embodiment of the present invention may include a substrate 20, and a first gate insulating layer 21, a first gate metal layer 22, a second gate insulating layer 23, a second gate metal layer 24, a pixel defining layer 25, a source drain metal layer 26, and a planarization layer 27 sequentially disposed on the substrate 20;

the substrate 20 may be an organic and inorganic alternating film layer, the first gate insulating layer 21, the second gate insulating layer 23 and the pixel defining layer are inorganic layers, the planarization layer 27 is an organic layer, and the first gate metal layer 22, the second gate metal layer 24 and the source drain metal layer 26 are metal layers;

the first gate metal layer 22 includes a first test sub-trace (the first test sub-trace is not shown in fig. 3), and the source-drain metal layer 26 includes a second test sub-trace;

the second test sub-trace (the second test sub-trace is not shown in fig. 3) is electrically connected to the first test sub-trace through a via H0 passing through the pixel defining layer 25, the second gate metal layer 24 and the second gate insulating layer 23.

In the embodiment shown in fig. 3, the first metal layer may be the first gate metal layer 22, the second metal layer may be the second gate metal layer 24, and the third metal layer may be the source-drain metal layer 26; the first insulating layer disposed between the first metal layer and the second metal layer may be the second gate insulating layer 23, and the second insulating layer disposed between the second metal layer and the third metal layer may be the pixel defining layer 25.

In fig. 3, only one via H0 is schematically shown, and in actual operation, the number of the vias H0 may be at least one.

Adopt the embodiment of the utility model provides a display panel, when carrying out ageing process, first grid metal level 22 with source leakage metal level 26 can test the reposition of redundant personnel that the son walked the line current, and the electric current that flows through on single metal level is less like this, and calorific capacity is corresponding to be reduced, and more importantly, double-deck test son walks the surface area that the line has increased first test sub-circuit for the heat distributes away more easily, thereby avoids the heat to burn the panel.

When specifically implementing, the embodiment of the utility model provides a first test sub-circuit among display panel can adopt double-deck test sub-wiring to increase the surface area, make the heat distribute away more easily, thereby avoid the heat gathering to burn the panel.

Specifically, an orthographic projection of the first test sub-trace on the substrate base plate is a first orthographic projection, and an orthographic projection of the second test sub-trace on the substrate base plate is a second orthographic projection;

the first orthographic projection and the second orthographic projection at least partially overlap.

In specific implementation, the first orthographic projection and the second orthographic projection are at least partially overlapped to occupy less routing space.

Under the preferable condition, the first orthographic projection and the second orthographic projection are overlapped, so that the problem that the panel is easily burnt due to high heat quantity of a single-layer testing wire can be avoided under the condition that the wire routing space is not increased.

In specific implementation, the first test sub-line may further include a fourth test sub-line;

the fourth test sub-trace and the first test sub-trace may be located at different layers, and the fourth test sub-trace and the second test sub-trace may be located at different layers;

Preferably, at least a part of orthographic projections of the fourth test sub-trace and the second test sub-trace on the substrate are overlapped, so that a smaller trace space can be occupied.

In an embodiment of the present invention, the second metal layer may include the fourth testing sub-trace, the first metal layer may include the first testing sub-trace, the third metal layer may include the second testing sub-trace, the first testing sub-trace the second testing sub-trace with the fourth testing sub-trace is electrically connected.

In an embodiment of the present invention, the fourth testing sub-line and the first testing sub-line are located at different layers and can be: the fourth test sub-trace and the first test sub-trace are made of two metal layers through different patterning processes, but not limited thereto.

In an embodiment of the present invention, the fourth testing sub-line and the second testing sub-line are located at different layers and can be: the fourth test sub-trace and the second test sub-trace are made of two metal layers through different patterning processes, but not limited thereto.

As shown in fig. 4, a display panel according to another embodiment of the present invention may include a substrate 20, and a first gate insulating layer 21, a first gate metal layer 22, a second gate insulating layer 23, a second gate metal layer 24, a pixel defining layer 25, a source drain metal layer 26, and a planarization layer 27 sequentially disposed on the substrate 20;

the first metal layer may be the first gate metal layer 22, the second metal layer may be the second gate metal layer 24, and the third metal layer may be the source-drain metal layer 26;

the first insulating layer disposed between the first metal layer and the second metal layer may be the second gate insulating layer 23, and the second insulating layer disposed between the second metal layer and the third metal layer may be the pixel defining layer 25;

the first testing sub-circuit in the display panel according to the embodiment of the present invention includes a first testing sub-circuit, a second testing sub-circuit, and a fourth testing sub-circuit (the testing sub-circuit is not shown in fig. 4), the first gate metal layer 22 includes the first testing sub-circuit, the second gate metal layer 24 includes the second testing sub-circuit, and the source-drain metal layer 26 includes the fourth testing sub-circuit;

the fourth test sub-trace is electrically connected with the second test sub-trace through a first via H1 penetrating through the pixel defining layer 25;

the fourth test sub-trace is electrically connected to the first test sub-trace through a second via H2 passing through the pixel defining layer 25, the second gate metal layer 24 and the second gate insulating layer 23.

In fig. 4, only one first via H1 and one second via H2 are schematically illustrated, and in actual operation, the number of the first vias H1 and the number of the second vias H2 may be at least one.

Adopt the embodiment of the utility model provides a display panel, when carrying out ageing process, first grid metal level 22, second grid metal level 24 with source leakage metal level 26 can test the reposition of redundant personnel that the son walked the line current, and the electric current that flows through on single metal level is less like this, and calorific capacity is corresponding to be reduced, more importantly, and the three-layer test is walked the line and is increased the surface area of first test sub-circuit for the heat distributes away more easily, thereby avoids the heat to burn the panel.

Specifically, the number of the first vias may be at least two, and the number of the second vias may be at least two;

the first via holes and the second via holes may be alternately arranged along a direction in which the first test sub-line extends. The first via holes and the second via holes are alternately arranged, so that the first metal layer, the second metal layer and the third metal layer can uniformly distribute current in the shortest distance, the resistance of a local area is minimized, the generation of heat is reduced, and the third metal layer can conduct the heat away from the first metal layer and the second metal layer.

In the embodiment of the present invention, the third orthographic projection S3 of the fourth test sub-line on the substrate base plate may be as shown in fig. 5A, the second orthographic projection S2 of the second test sub-line on the substrate base plate may be as shown in fig. 5B, and the first orthographic projection S1 of the first test sub-line on the substrate base plate may be as shown in fig. 5C; in fig. 5B, a first block K1 shows a first opening on the second gate metal layer 24, a second block K2 shows a second opening on the second gate metal layer 24, and a third block K3 shows a third opening on the second gate metal layer 24.

in fig. 6, an orthographic projection of a first via hole on the substrate base plate is denoted by H11, an orthographic projection of a second first via hole on the substrate base plate is denoted by H12, and an orthographic projection of a third first via hole on the substrate base plate is denoted by H13;

an orthographic projection of the first second via hole on the substrate base plate is denoted by H21, an orthographic projection of the second via hole on the substrate base plate is denoted by H22, and an orthographic projection of the third second via hole on the substrate base plate is denoted by H23.

As shown in fig. 6, the third orthographic projection S3 at least partially overlaps the first orthographic projection S1 (S3 within S1), and the third orthographic projection S3 at least partially overlaps the second orthographic projection (S3 within S2).

In the embodiment of the present invention, S3 may not be completely within S1, or S1 may be within S3.

In the embodiment of the present invention, S3 may not be completely within S2, or S2 may be within S3.

In implementation, the second test sub-line may further include a conversion sub-line and a connection sub-line; the conversion sub-wire is electrically connected with the third test sub-wire;

In the embodiment of the present invention, the conversion sub-routing can be a dual-layer sub-routing, but not limited thereto.

In an embodiment of the present invention, the first sub-routing line and the second sub-routing line are located on different layers and can be: the first sub-trace and the second sub-trace are made of two metal layers through different composition processes, but not limited thereto;

the second sub-trace and the connecting sub-trace located in the same layer may be: the second sub-trace and the connecting sub-trace are formed by a single patterning process, but not limited thereto.

In a specific implementation, the second testing sub-trace may include a third testing sub-trace, a converting sub-trace and a connecting sub-trace, where the converting sub-trace includes a first sub-trace and a second sub-trace; the first metal layer may include the third test sub-trace and the first sub-trace, and the third metal layer may include the second sub-trace and the connection sub-trace;

the conversion sub-trace is used for electrically connecting the third test sub-trace and the connection sub-trace, the conversion sub-trace comprises a first sub-trace and a second sub-trace which are electrically connected with each other, the conversion sub-trace is electrically connected with the third test sub-trace, the second sub-trace is electrically connected with the connection sub-trace, the connection sub-trace is electrically connected with the input end of the test circuit, and the orthographic projection of the first sub-trace on the substrate base plate and the orthographic projection of the second sub-trace on the substrate base plate are at least partially not overlapped.

Specifically, the second sub-trace and the connecting sub-trace may be an integral structure, but not limited thereto.

In a specific implementation, the second sub-trace and the connecting sub-trace may both be included in the third metal layer, and at this time, the second sub-trace and the connecting sub-trace may be an integrated structure.

In an embodiment of the present invention, the second sub-routing line and the connecting sub-routing line can be indicated as an integrated structure: the second sub-routing and the connecting sub-routing are formed by adopting the same material and one-time composition process.

Preferably, the orthographic projection of the integrated structure on the substrate base plate covers the orthographic projection of the first sub-wires on the substrate base plate, so that the resistance can be reduced, and the wiring space can be saved.

Specifically, the orthographic projection of the signal lead on the substrate and the orthographic projection of the connecting sub-trace on the substrate may not overlap.

In a specific implementation, the signal lead and the connecting sub-trace may be both included in the third metal layer, so that an orthogonal projection of the signal lead on the substrate and an orthogonal projection of the connecting sub-trace on the substrate are set to be not overlapped, so as to prevent a short circuit between the signal lead and the connecting sub-trace.

In an embodiment of the present invention, the connecting sub-trace and the second testing sub-trace can be disposed on the same layer.

In practical operation, both the connecting sub-trace and the second testing sub-trace may be included in the third metal layer, that is, the connecting sub-trace and the second testing sub-trace may be disposed on the same layer, but not limited thereto.

In a specific implementation, the connecting sub-trace and the second testing sub-trace are electrically connected to each other.

Specifically, the display panel according to the embodiment of the present invention may further include an auxiliary test pin; the auxiliary test pin is electrically connected with the second sub-routing.

When specifically implementing, display panel can also include the auxiliary test pin, through the second sub-line with the auxiliary test pin electricity is connected.

In the embodiment of the present invention, the auxiliary test pin can be connected to the test data voltage signal or the test switch control signal, but not limited thereto.

Specifically, the conversion sub-trace may further include a third sub-trace; the third sub-wiring is electrically connected with the second sub-wiring;

In an embodiment of the present invention, the first sub-routing line and the third sub-routing line located on different layers may be: the first sub-trace and the third sub-trace are made of two metal layers through different composition processes, but not limited thereto;

in an embodiment of the present invention, the second sub-routing line and the third sub-routing line located on different layers may be: the second sub-trace and the third sub-trace are made of two metal layers through different patterning processes, but not limited thereto.

In a specific implementation, the converting sub-trace may further include a third sub-trace, that is, the converting sub-trace may be a three-layer sub-trace, and the third sub-trace may be included in the second metal layer.

the conversion sub-trace may include a first sub-trace, a second sub-trace, and a third sub-trace electrically connected to each other; the second sub-wiring is electrically connected with the connecting sub-wiring; the connecting sub-wire is electrically connected with the input end of the test circuit;

the first sub-routing and the second sub-routing are located on different layers; the third sub-routing and the first sub-routing are located on different layers, and the third sub-routing and the second sub-routing are located on different layers;

the second sub-trace and the connecting sub-trace may be located at the same layer;

In a specific implementation, the first sub-trace may be included in the first metal layer, the second sub-trace may be included in the third metal layer, and the third sub-trace may be included in the second metal layer, but not limited thereto.

As shown in fig. 7, on the basis of the embodiment of the display panel shown in fig. 2A, the display panel according to the embodiment of the present invention may further include an auxiliary test pin Pf;

the second test sub-line may further include a conversion sub-line S23 and a connection sub-line S24; the conversion sub-trace S23 is electrically connected with the third test sub-trace S22;

the conversion sub-trace S23 is electrically connected to the auxiliary test pin Pf;

the conversion sub-trace S23 is electrically connected with the connection sub-trace S24;

the connecting sub-trace S24 is electrically connected to the input terminal of the test circuit 11.

3 fig. 3 8 3 is 3 a 3 sectional 3 view 3 a 3- 3 a 3' 3 in 3 fig. 3 7 3. 3

In fig. 8, a first sub-trace denoted by 81 is included for the converting sub-trace, a second sub-trace denoted by 82 is included for the converting sub-trace, and a third sub-trace denoted by 83 is included for the converting sub-trace;

a substrate reference numeral 20, a first gate insulating layer reference numeral 21, a second gate insulating layer reference numeral 23, a pixel defining layer reference numeral 25, and a planarization layer reference numeral 27;

the second sub-trace 82 is electrically connected to the third sub-trace 83 through a third via H3 and a fourth via H4;

the second sub-trace 82 is electrically connected to the first sub-trace 81 through a fifth via H5 and a sixth via H6.

In the embodiment shown in fig. 8, the first sub-trace 81 may be included in the first gate metal layer, the second sub-trace 82 may be included in the source-drain metal layer, and the third sub-trace 83 may be included in the second gate metal layer, but not limited thereto.

Specifically, the second test sub-line may further include a fifth test sub-line; the fifth test sub-trace is electrically connected with the third test sub-trace;

In an embodiment of the present invention, the fifth testing sub-line and the third testing sub-line are located on different layers and can be: the fifth test sub-trace and the third test sub-trace are made of two metal layers through different patterning processes, but not limited thereto.

In a specific implementation, the second testing sub-circuit may be a dual-layer testing sub-circuit, and the second testing sub-circuit may include a third testing sub-line and a fifth testing sub-line, where the third testing sub-line may be included in the first metal layer, and the fifth testing sub-line may be included in the second metal layer, but not limited thereto. And the orthographic projection of the signal lead on the substrate base plate is at least partially overlapped with the orthographic projection of the fifth test sub-wire on the substrate base plate, so that the signal lead can utilize the wire space of the test wire.

Specifically, the display panel may include a first metal pattern layer, a second metal pattern layer, and a third metal pattern layer;

In an embodiment of the present invention, the first test sub-trace and the first metal pattern layer may indicate on the same layer as: manufacturing the first test sub-wire and the first metal pattern layer through a one-time composition process;

the arrangement of the fourth test sub-trace and the second metal pattern layer on the same layer may be: manufacturing the fourth test sub-trace and the second metal pattern layer by a one-time composition process;

the arrangement of the second test sub-trace and the third metal pattern layer on the same layer may be: and manufacturing the second test sub-wiring and the third metal pattern layer by a one-time composition process.

In particular implementations, the display panel may include a display driving circuit;

the first metal pattern layer may include a gate pattern layer of the thin film transistor, the second metal pattern layer may include an electrode pattern layer of the storage capacitor, and the third metal layer may include a source pattern layer of the thin film transistor and a drain pattern layer of the thin film transistor.

Specifically, the first test sub-trace, the third test sub-trace and the first metal pattern layer may be included in a first metal layer, the fourth test sub-trace and the second metal pattern layer may be included in a second metal layer, and the second test sub-trace and the third metal pattern layer may be included in a third metal layer;

In specific implementation, the first metal layer includes a first test sub-trace, a third test sub-trace and a first metal pattern layer, the second metal layer includes a fourth test sub-trace and a second metal pattern layer, the third metal layer includes a second test sub-trace and a third metal pattern layer, and the first test sub-trace, the third test sub-trace, the fourth test sub-trace and the second test sub-trace are electrically connected to each other.

In the preparation the utility model discloses during preparation display panel, can adopt relevant manufacturing process, the metal level adopts the sputtering technology preparation, and inorganic layer uses chemical vapor deposition technology preparation, and organic layer adopts coating technology preparation, nevertheless does not regard this as the limit.

Specifically, the second test sub-line may further include a fifth test sub-line; the fifth test sub-trace and the third test sub-trace are located at different layers;

the fifth test sub-trace is included in the second metal layer.

In a specific implementation, the second test sub-line may include a third test sub-line and a fifth test sub-line, the second test sub-line is a dual-layer test sub-line, and the second metal layer includes the fifth test sub-line.

Specifically, the second test sub-line may further include a conversion sub-line and a connection sub-line; the conversion sub-wiring comprises a first sub-wiring and a second sub-wiring; the conversion sub-wire is electrically connected with the third test sub-wire; the first sub-wiring is electrically connected with the second sub-wiring; the second sub-routing is electrically connected with the input end of the test circuit;

the first sub-trace is included in the first metal layer.

In a specific implementation, the second test sub-line may include a conversion sub-line and a connection sub-line, the conversion sub-line includes a first sub-line and a second sub-line, the first metal layer includes the first sub-line, and the third metal layer includes the second sub-line and the connection sub-line.

the third sub-trace is included in the second metal layer.

In a specific implementation, the converting sub-trace may include a third sub-trace, and the second metal layer includes the third sub-trace.

The circuit diagram of an embodiment of the display driving circuit in the display panel according to the embodiment of the present invention can be as shown in fig. 9A.

As shown in fig. 9A, a display driving circuit 121 is used to drive the light emitting element 120, and the display driving circuit 121 may include a driving circuit 122, a first light emission control circuit 123, and a second light emission control circuit 124. The driving circuit 122 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current for driving the light emitting element 120 to emit light to the light emitting element 120. For example, the first light emission control circuit 123 is connected to a first terminal of the driving circuit 122 and a power supply voltage terminal for supplying the power supply voltage signal VDD, and is configured to control connection or disconnection between the driving circuit 122 and the power supply voltage terminal for supplying the power supply voltage signal VDD, and the second light emission control circuit 124 is electrically connected to a second terminal of the driving circuit 122 and the first light emission voltage application electrode of the light emitting element 120, and is configured to control connection or disconnection between the driving circuit 122 and the light emitting element 120.

As shown in fig. 9A, the pixel circuit 121 further includes a data writing circuit 126, a storage circuit 127, a threshold value compensation circuit 128, and a reset circuit 129. The data writing circuit 126 is electrically connected to the first end of the driving circuit 122, and is configured to write the data voltage on the data line Vd into the storage circuit 127 under the control of the scan signal; the storage circuit 127 is electrically connected to the control terminal of the driving circuit 122 and the power supply voltage terminal, and is configured to store a data voltage; the threshold compensation circuit 128 is electrically connected to the control terminal of the driving circuit 122 and the second terminal of the driving circuit 122, and is configured to perform threshold compensation on the driving circuit 122; the reset circuit 129 is electrically connected to the control terminal of the drive circuit 122 and the first light-emitting voltage application electrode of the light-emitting element 120, and is configured to reset the control terminal of the drive circuit 122 and the first light-emitting voltage application electrode of the light-emitting element 120 under the control of a reset control signal.

For example, as shown in fig. 9A, the driving circuit 122 includes a driving transistor T1, the control terminal of the driving circuit 122 includes a gate of a driving transistor T1, the first terminal of the driving circuit 122 includes a first pole of a driving transistor T1, and the second terminal of the driving circuit 122 includes a second pole of a driving transistor T1.

For example, as shown in fig. 9A, the data write circuit 126 includes a data write transistor T2, the memory circuit 127 includes a storage capacitor C2, the threshold compensation circuit 128 includes a threshold compensation transistor T3, the first light emission control circuit 123 includes a first light emission control transistor T4, the second light emission control circuit 124 includes a second light emission control transistor T5, the reset circuit 129 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

For example, as shown in fig. 9A, a first pole of the data writing transistor T2 is electrically connected with a first pole of the driving transistor T1, a second pole of the data writing transistor T2 is configured to be electrically connected with the data line Vd to receive a data voltage, and a gate of the data writing transistor T2 is configured to be electrically connected with the first gate line Ga1 to receive a scan signal; a first plate CC1a of the storage capacitor C2 is electrically connected with the power supply voltage end, and a second plate CC2a of the storage capacitor C2 is electrically connected with the gate of the driving transistor T1; a first pole of the threshold compensation transistor T3 is electrically connected with the second pole of the driving transistor T1, a second pole of the threshold compensation transistor T3 is electrically connected with the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 is configured to be electrically connected with the second gate line Ga2 to receive a compensation control signal; a first pole of the first reset transistor T6 is configured to be electrically connected to a first reset power source terminal Vinit1 to receive a first reset signal, a second pole of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first reset control signal line Rst1 to receive a first sub-reset control signal; a first pole of the second reset transistor T7 is configured to be electrically connected to the second reset power source terminal Vinit2 to receive the second reset signal, a second pole of the second reset transistor T7 is electrically connected to the first light-emitting voltage applying electrode of the light emitting element 120, and a gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second sub-reset control signal; a first pole of the first light emission control transistor T4 is connected to the power supply voltage signal VDD, a second pole of the first light emission control transistor T4 is electrically connected to the first pole of the driving transistor T1, and a gate of the first light emission control transistor T4 is configured to be electrically connected to the first light emission control signal line EM1 to receive the first light emission control signal; a first pole of the second light emission controlling transistor T5 is electrically connected to the second pole of the driving transistor T1, a second pole of the second light emission controlling transistor T5 is electrically connected to the first light emission voltage applying electrode of the light emitting element 120, and a gate of the second light emission controlling transistor T5 is configured to be electrically connected to the second light emission control signal line EM2 to receive the second light emission control signal; the second light-emitting voltage application electrode of the light-emitting element 120 is electrically connected to the low voltage terminal VSS.

In the embodiment of the present invention, the first light-emitting voltage applying electrode of the light-emitting element 120 may be an anode, and the second light-emitting voltage applying electrode of the light-emitting element 120 may be a cathode; the anode layer is connected to the second light emission control transistor T5 through a via hole.

In the embodiment of the display driving circuit shown in fig. 9A, each transistor may be a thin film transistor, but is not limited thereto.

In another embodiment of the display driver circuit shown in fig. 9B, based on the embodiment of the display driver circuit shown in fig. 9A, EM1 may be electrically connected to EM2, Rst1 may be electrically connected to Rst2, Ga1 may be electrically connected to Ga2, so that EM1 and EM2 may be combined into one signal terminal, Rst1 and Rst2 may be combined into one signal terminal, and Ga1 and Ga2 may be combined into one signal terminal, but not limited thereto.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, and the like. The source and drain of the transistor may be symmetrical in structure, so that the source and drain may be physically indistinguishable. In the embodiments of the present disclosure, in order to distinguish transistors, in addition to the gate electrode as the control electrode, one of the electrodes is directly described as a first electrode, and the other electrode is directly described as a second electrode, so that the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure may be interchanged as necessary.

As shown in fig. 10, the display panel according to the embodiment of the present invention may include a substrate 20, a buffer layer 101, an active layer 102, a first gate insulating layer 21, a first gate metal layer 22, a second gate insulating layer 23, a second gate metal layer 24, a pixel defining layer 25, a source/drain metal layer 26, a planarization layer 27, an anode layer 103, a light emitting layer 104, and a cathode layer 105;

the first gate metal layer 22 may include a first metal pattern layer, a first test sub-trace and a third test sub-trace;

the second gate metal layer 24 may include a second metal pattern layer, a fourth test sub-trace and a fifth test sub-trace;

the source-drain metal layer 26 may include a third metal pattern layer and a second test sub-trace;

the embodiment of the utility model provides a display panel includes the display drive circuit, the display drive circuit includes thin film transistor and storage capacitor;

The embodiment of the utility model provides a display device include foretell display panel.

The embodiment of the utility model provides a display device can be any products or parts that have the display function such as cell-phone, panel computer, TV set, display, notebook computer, digital photo holder frame, navigator.

The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A display panel is characterized by comprising a substrate base plate and a test circuit arranged on the substrate base plate; the display panel further comprises a test circuit, wherein a first end of the test circuit is electrically connected with the first test pin, a second end of the test circuit is electrically connected with an input end of the test circuit, and the display panel further comprises a signal lead between the first end of the test circuit and the input end of the test circuit;

2. The display panel of claim 1, wherein the first test sub-trace and the second test sub-trace are located at different layers.

3. The display panel of claim 1, wherein the first test sub-trace and the second test sub-trace at least partially overlap between orthographic projections of the first test sub-trace and the second test sub-trace on the substrate base plate.

4. The display panel of claim 1, wherein the second test sub-line further includes a conversion sub-line and a connection sub-line; the conversion sub-wire is electrically connected with the third test sub-wire;

5. The display panel of claim 4, wherein the second sub-trace and the connecting sub-trace are an integral structure.

6. The display panel of claim 5, wherein an orthographic projection of the integrated structure on the substrate base plate covers an orthographic projection of the first sub-traces on the substrate base plate.

7. The display panel of claim 4, wherein an orthographic projection of the signal leads on the substrate base plate does not overlap with an orthographic projection of the connection sub-traces on the substrate base plate.

8. The display panel of claim 4, wherein the connection sub-trace is disposed in a same layer as the second test sub-trace.

9. The display panel of claim 8, wherein the connection sub-trace and the second test sub-trace are electrically connected to each other.

10. The display panel of claim 4, further comprising auxiliary test pins; the auxiliary test pin is electrically connected with the second sub-routing.

11. The display panel of claim 4, wherein the conversion sub-trace further comprises a third sub-trace; the third sub-wiring is electrically connected with the second sub-wiring;

12. The display panel according to claim 1, wherein the signal lead is a power supply voltage signal line.

13. The display panel of claim 1, wherein the first test sub-line further comprises a fourth test sub-trace;

14. The display panel of claim 13, wherein the fourth test sub-trace and the second test sub-trace at least partially overlap between orthographic projections of the fourth test sub-trace on the substrate base plate.

15. The display panel of claim 1, wherein the second test sub-line further comprises a fifth test sub-trace; the fifth test sub-trace is electrically connected with the third test sub-trace;

16. The display panel of claim 13, wherein the display panel comprises a first metal pattern layer, a second metal pattern layer, and a third metal pattern layer;

17. The display panel of claim 16, wherein the first test sub-trace, the third test sub-trace, and the first metal pattern layer are included in a first metal layer, the fourth test sub-trace and the second metal pattern layer are included in a second metal layer, and the second test sub-trace and the third metal pattern layer are included in a third metal layer;

18. The display panel of claim 17, wherein the second test sub-line further comprises a fifth test sub-trace; the fifth test sub-trace and the third test sub-trace are located at different layers;

the fifth test sub-trace is included in the second metal layer.

19. The display panel of claim 17, wherein the second test sub-line further includes a conversion sub-line and a connection sub-line; the conversion sub-wiring comprises a first sub-wiring and a second sub-wiring; the conversion sub-wire is electrically connected with the third test sub-wire; the first sub-wiring is electrically connected with the second sub-wiring; the second sub-routing is electrically connected with the input end of the test circuit;

the first sub-trace is included in the first metal layer.

20. The display panel of claim 19, wherein the conversion sub-trace further comprises a third sub-trace; the third sub-wiring is electrically connected with the second sub-wiring;

the third sub-trace is included in the second metal layer.

21. The display panel of claim 17, wherein the first metal layer is a first gate metal layer, the second metal layer is a second gate metal layer, and the third metal layer is a source drain metal layer.

22. The display panel according to claim 21, wherein the display panel comprises a display driver circuit;

23. A display device comprising the display panel according to any one of claims 1 to 22.