CN210572361U

CN210572361U - Passive radar signal processor of unmanned aerial vehicle anti-braking system

Info

Publication number: CN210572361U
Application number: CN201922004541.2U
Authority: CN
Inventors: 何文君; 何学江
Original assignee: Sichuan Hashsico Technology Co ltd
Current assignee: Sichuan Hashsico Technology Co ltd
Priority date: 2019-11-19
Filing date: 2019-11-19
Publication date: 2020-05-19
Anticipated expiration: 2029-11-19

Abstract

The utility model discloses a passive radar signal processor of unmanned aerial vehicle system of turning back mainly solves the easy distortion of the passive radar signal processor signal transmission of current unmanned aerial vehicle system of turning back, and signal processing speed is slow, leads to the radar to track the problem that the reliability is low. The processor comprises an FPGA controller, a DSP chip, an AD analog-to-digital conversion module, an SDRAM memory, an Ethernet chip, a power supply module, a DA digital-to-analog conversion module, a video interface module and a multi-channel acquisition module connected with the AD analog-to-digital conversion module. Through the design, the utility model discloses a multiunit signal reception sampling channel to carry out the comparison to the digital signal after every way conversion, unify the integration by the output result of signal modulation unit to the digital signal of each passageway and data comparison unit, compensate the decay among the signal transmission process, ensure the high fidelity of DSP chip input signal, promote the reliability that the passive radar of unmanned aerial vehicle anti-system tracked. Therefore, the method is suitable for popularization and application.

Description

Passive radar signal processor of unmanned aerial vehicle anti-braking system

Technical Field

The utility model relates to a signal processor, specifically speaking relates to a passive radar signal processor of unmanned aerial vehicle anti-system.

Background

Along with the revolution and development of unmanned aerial vehicle technology, people are increasing the use demand of unmanned aerial vehicles, and small-size commercial multiaxis unmanned aerial vehicle has become a popular consumer product with its self characteristics that the size is little, the noise is little, convenient to carry, the manipulation is simple and convenient. At present, the market development of unmanned aerial vehicles at home and abroad is rapid, more and more unmanned aerial vehicle fans own the unmanned aerial vehicles, but the problems caused by the unmanned aerial vehicle fans are also gradually outstanding.

In some specific areas, where the drone is prohibited from flying, the drone needs to be monitored and countered, and the drone countercheck system is mainly applied to the following aspects, such as protection of the no-fly area: airport, nuclear power facility, military management area, prison, satellite launching tower, national strategic resource project, government department etc. and for example protection of secret-involved area: national security agencies, important security places, large-scale sports events, large-scale performance events, archaeological excavation sites, commercial confidential information, illegal criminal behaviors with unmanned aerial vehicles as carriers, prevention and control, attack on transportation and drug delivery, smuggling, transportation of illegal articles, illegal information transfer border damage and the like.

When a tracked target is maneuvered, namely the speed and the direction of the target are changed, the conventional passive radar system generates a large error if a general tracking algorithm is used for tracking the maneuvered target. Due to the limitation of the processing capability of a Digital Signal Processor (DSP), the function of a radar signal processor is often completed by relaying a plurality of board-level subsystems, some operation function modules with large operation amount are needed, and meanwhile, there is a problem that signal transmission is easy to distort, for example, when Fast Fourier Transform (FFT) and complex multiplication are performed, a special chip is usually needed in the system to achieve the purpose of meeting the real-time requirement of the system.

At present, an urgent need develops a passive radar signal processor, can realize detecting and tracking moving target fast, in real time, strengthens the target identification performance of radar, promotes unmanned aerial vehicle anti-system's reliability, and need not to adopt special chip in addition.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a passive radar signal processor of unmanned aerial vehicle system of turning back mainly solves the easy distortion of the passive radar signal processor signal transmission of current unmanned aerial vehicle system of turning back, and signal processing speed is slow, leads to the radar to track the problem that the reliability is low.

In order to achieve the above object, the utility model adopts the following technical scheme:

a passive radar signal processor of an unmanned aerial vehicle anti-braking system comprises an FPGA controller, a DSP chip, an AD (analog-to-digital) conversion module, an SDRAM (synchronous dynamic random access memory) memory, an Ethernet chip and a power module, wherein the DSP chip and the AD conversion module are connected with the FPGA controller;

the multi-path acquisition module comprises a signal modulation unit connected with the AD analog-to-digital conversion module, a comparison input unit connected with the signal modulation, and a plurality of signal acquisition units connected with the comparison input unit.

Furthermore, the signal acquisition unit comprises a signal receiving antenna, a signal receiving subunit connected with the signal receiving antenna, a signal filtering amplifier connected with the signal receiving subunit, and an FIFO memory connected with the signal filtering amplifier; wherein the FIFO memory is connected with the comparison input unit.

Further, the signal modulation unit comprises a chip U1 with model number MC1596, a resistor R1 connected between the 2 nd and 3 rd pins of the chip U1, a resistor R2, a resistor R4 and a capacitor C2 which are connected with the 6 th pin of the chip U1 and are sequentially connected in series, a resistor R5 with one end connected with the joint of the resistor R4 and the capacitor C2 and the other end grounded, a resistor R6 connected between the 7 th pin and the 8 th pin of the chip U1, a capacitor C1 connected with the 8 th pin of the chip, resistors R7 and R8 which are connected with the 1 st pin of the chip U1 at one end and the 4 th pin of the chip U1 at the other end after being connected in series, a resistor R9, a slide rheostat RP1 and a resistor R10 which are connected with the 1 st pin of the chip U1 at one end and the 4 th pin of the chip U1 at the other end after being connected in series, a resistor R11 which is connected with the 5 th pin of the chip U1 at one end and the other end is grounded, and a resistor R3 with one end connected to the connection point of the resistors R2 and R4 and one end connected to the 9 th pin of the chip U1; the sliding end of the slide rheostat RP1 is connected with the 10 th pin of the chip U1, one ends of the resistors R7, R8 and the capacitor C2 are grounded, the 1 st pin of the chip U1 is connected with the AD analog-to-digital conversion module, and the other end of the capacitor C1 is connected with the comparison input unit.

Further, the comparison input unit comprises a comparator a1, a resistor R12 connected to the positive input end of the comparator a1, a resistor R13 connected to the output end of the comparator a1, a diode D1 having a cathode connected to the other end of the resistor R13, a resistor R14 connected to the anode of the diode D1, a capacitor C3 connected to the other end of the resistor R14, a diode D3 having an anode connected to the other end of the capacitor C3, a diode D2 having a cathode connected to the positive input end of the comparator a1, resistors R15 and R16 connected to the anodes of the diodes D2, a capacitor C4 having one end connected to the other end of the resistor R15 and the other end grounded, a comparator a2 having an anode input end connected to the other end of the resistor R16 and the anode of the diode D3, a resistor R17 having one end connected to the anode input end of the comparator a2 and the other end grounded, and a resistor R18 connected to the output end of the comparator a 2; the other end of the resistor R12 is connected with the other end of the capacitor C1, and the other end of the resistor R18 is connected with the FIFO memory.

Further, the signal receiving antenna comprises an antenna body ANT, a resistor R19, a capacitor C5 and an inductor L1 which are connected in series and then sequentially connected with the antenna body ANT, an inductor L2 and an inductor L3 which are connected with the other end of the inductor L1, a capacitor C6 connected in parallel with two ends of the inductor L2, a capacitor C7 connected in parallel with two ends of the inductor L3, a resistor R20 connected in parallel with two ends of the capacitor C6, a resistor R7 connected in parallel with two ends of the capacitor C7, a resistor R7 connected with the connection ends of the inductors L7, L7 and L7, a comparator a 7 with a positive input end connected with the other end of the resistor R7, a triode Q7 connected with the connection ends of a base electrode and an emitter electrode, the inductor L7, the capacitor C7 and the resistor R7, a resistor R7 connected with a collector of the triode Q7, and a capacitor C7 with one end connected with the other end of the comparator a 7; wherein, the output end of the comparator A3 is connected with the signal receiving subunit.

Compared with the prior art, the utility model discloses following beneficial effect has:

(1) the utility model discloses a multiunit signal reception sampling channel to digital signal after every way conversion carries out the comparison, is unified to the digital signal of each passageway and the output result of data comparison unit by the signal modulation unit and integrates, compensaties the decay among the signal transmission process, ensures the high fidelity of DSP chip input signal, promotes the reliability that the passive radar of unmanned aerial vehicle anti-system tracked.

(2) The utility model discloses a FPGA controller and DSP chip synergism can realize detecting and tracking the moving target fast, in real time, strengthens the target identification performance of radar, and need not to adopt special chip in addition, is favorable to reduction in production cost, is suitable for popularization and application.

Drawings

Fig. 1 is a block diagram of the overall system of the present invention.

Fig. 2 is a schematic circuit diagram of the signal modulation unit of the present invention.

Fig. 3 is a schematic diagram of a circuit of the comparison input unit of the present invention.

Fig. 4 is a schematic diagram of the signal receiving antenna circuit of the present invention.

Detailed Description

The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.

Examples

As shown in fig. 1, the utility model discloses a passive radar signal processor of unmanned aerial vehicle anti-system, including the FPGA controller, DSP chip, AD analog-to-digital conversion module that link to each other with the FPGA controller, the SDRAM memory that links to each other with the DSP chip, ethernet chip, power module, the DA digital analog conversion module that links to each other with the SDRAM memory, the video interface module that links to each other with AD analog-to-digital conversion module and DA digital analog conversion module, and the multichannel collection module that links to each other with AD analog-to-digital conversion module; the model of the FPGA controller is EP4CE115F29C7N, and the DSP chip adopts TMS320 series of TI company.

The signal acquisition unit comprises a signal receiving antenna, a signal receiving subunit connected with the signal receiving antenna, a signal filtering amplifier connected with the signal receiving subunit, and an FIFO memory connected with the signal filtering amplifier; wherein the FIFO memory is connected with the comparison input unit.

Firstly, multipath signal is received by the multipath signal acquisition unit, the received signal strength is enhanced, the received signals are processed by the signal receiving subunit and the signal filter amplifier and then enter the FIFO memory for storage, the digital signals of all channels and the output results of the data comparison unit are integrated uniformly by the signal modulation unit, the attenuation in the signal transmission process is compensated, the high fidelity of the signals at the input end of the DSP chip is ensured, and the reliability of passive radar tracking of the unmanned aerial vehicle anti-braking system is improved. The video interface module is used for receiving and transmitting video data for analysis and processing, then utilizes the AD analog-to-digital conversion module to carry out analog-to-digital conversion on the received signal, and the synergistic effect of the FPGA controller and the DSP chip is achieved, so that the moving target can be rapidly and timely detected and tracked, the target identification performance of the radar is enhanced, and the stability of the unmanned aerial vehicle anti-braking system is improved.

Specifically, as shown in fig. 2, the signal modulation unit of the present invention includes a chip U1 with a model MC1596, a resistor R1 connected between the 2 nd and 3 rd pins of the chip U1, resistors R2, R4 and a capacitor C2 connected in series with the 6 th pin of the chip U1 in turn, a resistor R5 connected at one end to the junction of the resistor R4 and the capacitor C2 and connected at the other end to ground, a resistor R6 connected between the 7 th and 8 th pins of the chip U1, a capacitor C1 connected to the 8 th pin of the chip, resistors R7 and R8 connected at one end to the 1 st pin of the chip U1 and connected at the other end to the 4 th pin of the chip U1 after being connected in series, a resistor R9 connected at one end to the 1 st pin of the chip U1 and connected at the other end to the 4 th pin of the chip U1, a sliding RP1 and a resistor R10, a resistor R11 connected at one end to the first pin 5 of the chip U1 and connected at the other end to ground, and a, The resistor R3 is connected with the R4 connection point, and one end of the resistor R3 is connected with the 9 th pin of the chip U1; the sliding end of the slide rheostat RP1 is connected with the 10 th pin of the chip U1, one ends of the resistors R7, R8 and the capacitor C2 are grounded, the 1 st pin of the chip U1 is connected with the AD analog-to-digital conversion module, and the other end of the capacitor C1 is connected with the comparison input unit.

Specifically, as shown in fig. 3, the comparison input unit of the present invention includes a comparator a1, a resistor R12 connected to the positive input terminal of the comparator a1, a resistor R13 connected to the output terminal of the comparator A1, a diode D1 having its cathode connected to the other end of the resistor R13, a resistor R14 connected with the anode of the diode D1, a capacitor C3 connected with the other end of the resistor R14, a diode D3 connected with the other end of the capacitor C3 at the anode, a diode D2 connected with the anode input end of a comparator A1 at the cathode, resistors R15 and R16 connected with the anode of the diode D2 at the anode, a capacitor C4 connected with the other end of the resistor R15 at one end and grounded at the other end, a comparator A2 connected with the other end of the resistor R16 and the anode of the diode D3 at the anode input end, a resistor R17 connected with the anode input end of the comparator A2 at one end and grounded at the other end, and a resistor R18 connected with the output end of the comparator A2; the other end of the resistor R12 is connected with the other end of the capacitor C1, and the other end of the resistor R18 is connected with the FIFO memory.

Specifically, as shown in fig. 4, the signal receiving antenna of the present invention includes an antenna body ANT, a resistor R19, a capacitor C5, an inductor L1 connected to the antenna body ANT in series, an inductor L2, an inductor L3 both connected to the other end of the inductor L1, a capacitor C6 connected to both ends of the inductor L2 in parallel, a capacitor C7 connected to both ends of the inductor L3 in parallel, a resistor R20 connected to both ends of the capacitor C6 in parallel, a resistor R7 connected to both ends of the capacitor C7 in parallel, a resistor R7 connected to a connection end of the inductors L7, a comparator a 7 having a positive input end connected to the other end of the resistor R7, a base, an emitter connected to the inductor L7, a triode Q7 connected to a connection end of the resistor C7, a resistor R7 connected to a collector of the triode Q7, and a capacitor C7 having one end connected to the other end of the resistor R7 and the other end connected to an output end of the comparator a 7; wherein, the output end of the comparator A3 is connected with the signal receiving subunit.

Through the design, the utility model discloses a multiunit signal reception sampling channel to carry out the comparison to the digital signal after every way conversion, unify the integration by the output result of signal modulation unit to the digital signal of each passageway and data comparison unit, compensate the decay among the signal transmission process, ensure the high fidelity of DSP chip input signal, promote the reliability that the passive radar of unmanned aerial vehicle anti-system tracked. Therefore, the method has high use value and popularization value.

The above embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the protection scope of the present invention, but all the insubstantial changes or modifications made in the spirit and the idea of the main design of the present invention, the technical problems solved by the embodiment are still consistent with the present invention, and all should be included in the protection scope of the present invention.

Claims

1. A passive radar signal processor of an unmanned aerial vehicle anti-braking system is characterized by comprising an FPGA controller, a DSP chip and an AD (analog-to-digital) conversion module which are connected with the FPGA controller, an SDRAM (synchronous dynamic random access memory) memory, an Ethernet chip and a power module which are connected with the DSP chip, a DA (digital-to-analog) conversion module which is connected with the SDRAM memory, a video interface module which is connected with the AD conversion module and the DA conversion module, and a multi-path acquisition module which is connected with the AD conversion module;

2. The passive radar signal processor of the unmanned aerial vehicle anti-jamming system according to claim 1, wherein the signal acquisition unit comprises a signal receiving antenna, a signal receiving subunit connected with the signal receiving antenna, a signal filtering amplifier connected with the signal receiving subunit, and a FIFO memory connected with the signal filtering amplifier; wherein the FIFO memory is connected with the comparison input unit.

3. The passive radar signal processor of the unmanned aerial vehicle countermeasure system of claim 2, wherein the signal modulation unit comprises a chip U1 with the model number MC1596, a resistor R1 connected between the 2 nd and 3 rd pins of the chip U1, resistors R2, R4 and a capacitor C2 connected in series with the 6 th pin of the chip U1 in turn, a resistor R5 connected with the junction of the resistor R4 and the capacitor C2 at one end and grounded at the other end, a resistor R6 connected between the 7 th and 8 th pins of the chip U1, a capacitor C1 connected with the 8 th pin of the chip, resistors R7 and R8 connected with one end to the 1 st pin of the chip U1 and connected with the other end to the 4 th pin of the chip U1, a resistor R9 connected with the 1 st pin of the chip U1 at one end and connected with the other end to the 4 th pin of the chip U1 at the other end, a slide RP 2 and a resistor R8269553 connected with the first pin 11 and the other end connected with the first pin of the chip U1 and grounded, the resistor R3 is connected with the connection point of the resistors R2 and R4 at one end and is connected with the 9 th pin of the chip U1 at the other end; the sliding end of the slide rheostat RP1 is connected with the 10 th pin of the chip U1, one ends of the resistors R7, R8 and the capacitor C2 are grounded, the 1 st pin of the chip U1 is connected with the AD analog-to-digital conversion module, and the other end of the capacitor C1 is connected with the comparison input unit.

4. The passive radar signal processor of claim 3, wherein the comparison input unit comprises a comparator A1, a resistor R12 connected to an anode input terminal of the comparator A1, a resistor R13 connected to an output terminal of the comparator A1, a diode D1 having a cathode connected to the other terminal of the resistor R13, a resistor R14 connected to an anode of the diode D1, a capacitor C3 connected to the other terminal of the resistor R14, a diode D3 having an anode connected to the other terminal of the capacitor C3, a diode D2 having a cathode connected to an anode input terminal of the comparator A1, resistors R15 and R16 connected to an anode of the diode D2, a capacitor C4 connected to the other terminal of the resistor R15 and the other terminal is grounded, a comparator A2 connected to the other terminal of the resistor R16 and the anode of the diode D3, a resistor R17 connected to an anode input terminal of the comparator A2 and the other terminal is grounded, and a resistor R18 connected to the output of comparator a 2; the other end of the resistor R12 is connected with the other end of the capacitor C1, and the other end of the resistor R18 is connected with the FIFO memory.

5. The passive radar signal processor of claim 4, it is characterized in that the signal receiving antenna comprises an antenna body ANT, a resistor R19, a capacitor C5 and an inductor L1 which are connected in series and then sequentially connected with the antenna body ANT, an inductor L2 and an inductor L3 which are connected with the other end of the inductor L1, a capacitor C6 connected in parallel with the two ends of the inductor L2, a capacitor C7 connected in parallel with the two ends of the inductor L3, a resistor R20 connected in parallel with the two ends of the capacitor C6, a resistor R21 connected in parallel with the two ends of the capacitor C7, a resistor R22 connected with the connecting ends of the inductors L1, L2 and L3, a comparator A3 with the positive pole input end connected with the other end of the resistor R22, a triode Q1 with the base and the emitter connected with the connecting ends of the inductor L2, the capacitor C6 and the resistor R20, a resistor R23 connected with the collector of the triode Q1, and a capacitor C8 having one end connected to the other end of the resistor R23 and the other end connected to the output terminal of the comparator A3; wherein, the output end of the comparator A3 is connected with the signal receiving subunit.