CN210536599U - Multi-path high-speed broadband overcurrent detection circuit for load switch - Google Patents
Multi-path high-speed broadband overcurrent detection circuit for load switch Download PDFInfo
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Abstract
The utility model provides a high-speed broadband of multichannel overflows detection circuitry for load switch, the drive circuit module passes through the switch of control switch pipe behind the inside conversion of drive circuit to the break-make of control whole circuit realizes the circuit method that multichannel control overflows the detection, makes in the circuit more effective to load current's detection. The utility model discloses whole circuit design is simple, can adopt the CMOS technology to accomplish, and the fast bandwidth of circuit response speed is big, can respond in the time within 1 us. The circuit can set different current limiting values at different temperatures, and the reduction of the current limiting value when the temperature rises can be realized, so that the whole circuit is more effectively protected, and the phenomenon that the power tube is burnt down due to overlarge current to damage the whole chip is avoided. A plurality of overcurrent detection points can be set according to the actual condition in the circuit, and only corresponding detection circuits need to be added, so that the simple and reliable circuit is realized.
Description
Technical Field
The invention relates to the field of circuits, in particular to a broadband over-current detection circuit.
Background
Most of the current power supply products employ load switches to protect the power supply equipment, which requires the load switches to have associated functional requirements and good protection performance. When the power supply works, no matter the working environment of the chip or other reasons, the current of the power supply generates great change, the use of the power supply is influenced when the current is too large, the power supply product is possibly damaged more seriously, a plurality of overcurrent detection points are required to be arranged according to the requirement, and the design difficulty is increased. In order to solve the above problems, the current conventional method employs an over-current detection circuit to detect a large current or voltage flowing through the power tube to monitor the operating state of the chip. The traditional method has the disadvantages of complex circuit realization, low response speed of circuit detection, narrow bandwidth, incapability of effectively protecting the whole circuit in real time, overlarge chip area occupied by the adopted traditional process and high cost.
Therefore, a safe and reliable multi-path high-speed broadband overcurrent detection circuit with simple circuit design, high response speed and small area needs to be developed.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a multi-path high-speed broadband overcurrent detection circuit for a load switch and a control method thereof, which are used for solving the technical problems in the related field and are mainly used in the field of related protection circuits.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a multi-path high-speed broadband overcurrent detection circuit for a load switch comprises P-channel enhanced high-voltage MOS tubes PM1, PM2, PM3, PM4, PM5, P-channel enhanced MOS tubes PM6, PM7, N-channel enhanced MOS tubes NM1, NM2, NM3, NM4, NM5 and NM6, N-channel enhanced high-voltage power switch tubes NM7, resistors R1, R2, R3, R4, R5, R6, R7 and R8, a current source 1, a control circuit module, a logic circuit module, a driving circuit module, an input VCC port and an output IDC VOUT port;
the VCC port is connected with an external input power supply end, and the VOUT port is an output port of the whole circuit.
One end of the current source IDC1 is connected with an input VCC port, and the other end of the current source IDC1 is connected with the grid drain of an N-channel enhancement type MOS tube NM1 and the grids of NM2, NM3, NM4, NM5 and NM 6; the drain electrode of the grid electrode of the N-channel enhancement type MOS tube NM1 is connected with the other end of the current source IDC1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM3, NM4, NM5 and NM6, and the source electrode of the N-channel enhancement type MOS tube NM1 is grounded; the grid electrode of the N-channel enhancement type MOS transistor NM2 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS transistor NM1, the grid electrodes of NM3, NM4, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the grid electrode drain electrode of the P-channel enhancement type high-voltage MOS transistor PM1 and the grid electrodes of PM2 and PM3, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM3 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM4, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM2 and the grid electrode of the P-channel enhancement type high-voltage MOS tube PM4, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM4 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM3 and the grid electrode of the P-channel enhancement type high-voltage MOS tube PM5, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM5 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM4 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM4, the source electrode of the P-channel enhancement type MOS tube PM6 and the other input end of the logic circuit, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM6 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM4 and NM5 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM5, the source electrode of the P-channel enhancement type MOS tube PM7 and the input end of the logic circuit, and the source electrode is grounded. The current source IDC1 and the N-channel enhancement type MOS transistors NM1, NM2, NM3, NM4, NM5 and NM6 jointly form a current mirror circuit, and mirror currents are provided for branches where the N-channel enhancement type MOS transistors NM1, NM2, NM3, NM4, NM5 and NM6 are located.
The drain electrode of the grid electrode of the P-channel enhanced high-voltage MOS tube PM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM2 and the grid electrodes of the P-channel enhanced high-voltage MOS tubes PM2 and PM3, and the source electrode of the P-channel enhanced high-voltage MOS tube PM1 is connected with the other end of the resistor R3; the grid electrode of the P-channel enhanced high-voltage MOS tube PM2 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode drain electrode of the P-channel enhanced high-voltage MOS tube PM1 and the grid electrode of the PM3, the drain electrode is connected with the drain electrode of the N-channel enhanced MOS tube NM3 and the grid electrode of the P-channel enhanced high-voltage MOS tube PM4, and the source electrode is connected with the other end of the resistor R4; the grid electrode of the P-channel enhanced high-voltage MOS tube PM3 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode drain electrode of the P-channel enhanced high-voltage MOS tube PM1 and the grid electrode of the PM2, the drain electrode is connected with the drain electrode of the N-channel enhanced MOS tube NM4 and the grid electrode of the P-channel enhanced high-voltage MOS tube PM5, and the source electrode is connected with the other end of the resistor R5; the grid electrode of the P-channel enhanced high-voltage MOS tube PM4 is connected with the drain electrode of the P-channel enhanced high-voltage MOS tube PM2 and the drain electrode of the N-channel enhanced MOS tube NM3, the drain electrode is connected with the source electrode of the P-channel enhanced MOS tube PM6, the drain electrode of the N-channel enhanced MOS tube NM5 and the other input end of the logic circuit module, and the source electrode is connected with the other end of the resistor R6; the grid electrode of the P-channel enhanced high-voltage MOS tube PM5 is connected with the drain electrode of the P-channel enhanced high-voltage MOS tube PM3 and the drain electrode of the N-channel enhanced MOS tube NM4, the drain electrode is connected with the source electrode of the P-channel enhanced MOS tube PM7, the drain electrode of the N-channel enhanced MOS tube NM6 and one input end of the logic circuit module, and the source electrode is connected with the other end of the resistor R7; the grid electrode of the P-channel enhanced MOS tube PM6 is connected with the output end of the control circuit and the grid electrode of the P-channel enhanced MOS tube PM7, the drain electrode of the P-channel enhanced MOS tube PM7 is connected with the drain electrode of the P-channel enhanced MOS tube PM 8 and one end of a resistor R8, and the source electrode of the P-channel enhanced high-voltage MOS tube PM4 is connected with the drain electrode of the N-channel enhanced MOS tube NM5 and the other input end of the logic circuit module; the grid electrode of the P-channel enhanced type MOS tube PM7 is connected with the output end of the control circuit and the grid electrode of the P-channel enhanced type MOS tube PM6, the drain electrode of the P-channel enhanced type MOS tube PM6 is connected with one end of a resistor R8, and the source electrode of the P-channel enhanced type MOS tube PM5 is connected with the drain electrode of the P-channel enhanced type high-voltage MOS tube PM6, the drain electrode of the N-channel enhanced type MOS tube NM6 and one input. The P-channel enhanced high-voltage MOS tubes PM1, PM2 and PM3 form a voltage comparator circuit, the P-channel enhanced high-voltage MOS tubes PM4 and PM5 form output circuits of PM2 and PM3 drain branches respectively, and the P-channel enhanced MOS tubes PM6 and PM7 are used as switching tubes.
One end of the resistor R1 is connected with the input VCC port, the input end of the current source IDC1, one end of the resistor R3, one end of the resistor R6 and one end of the resistor R7, and the other end of the resistor R1 is connected with one end of the resistor R2 and one end of the resistor R4; one end of the resistor R2 is connected with the other end of the resistor R1 and one end of the resistor R4, and the other end of the resistor R2 is connected with one end of the resistor R5 and the drain electrode of the N-channel enhanced high-voltage power switch tube NM 7; one end of the resistor R3 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R6 and one end of the resistor R7, and the other end of the resistor R3 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 1; one end of the resistor R4 is connected with the other end of the resistor R1 and one end of the resistor R2, and the other end of the resistor R4 is connected with the source electrode of the P-channel enhanced high-voltage MOS transistor PM 2; one end of the resistor R5 is connected with the other end of the resistor R2 and the drain electrode of the N-channel enhanced high-voltage power switch tube NM7, and the other end of the resistor R5 is connected with the source electrode of the P-channel enhanced high-voltage MOS tube PM 3; one end of the resistor R6 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R3 and one end of the resistor R7, and the other end of the resistor R6 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 4; one end of the resistor R7 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R3 and one end of the resistor R6, and the other end of the resistor R7 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 5; one end of the resistor R8 is connected with the drains of the P-channel enhancement type MOS tube PM6 and the PM7, and the other end of the resistor R8 is connected with the ground; the resistors R1 and R2 adopt metal resistors with negative temperature coefficients, work in a linear region, and effectively sample the current of the source electrode and the drain electrode of the NM7 of the N-channel enhanced high-voltage power switching tube in time; the resistors R3, R4, R5, R6 and R7 are used as loads of respective branches of the P-channel enhancement type high-voltage MOS transistors PM1, PM2, PM3, PM4 and PM5 and play a role in voltage division, the resistances and the sizes of the resistors R4, R5, R6 and R7 are the same, and the resistor R8 is used as a load of a drain branch of the P-channel enhancement type MOS transistors PM6 and PM7 and plays a role in voltage division.
The output end of the control circuit module is connected with the gates of the P-channel enhancement type MOS tubes PM6 and PM 7; one input end of the logic circuit module is connected with a drain electrode of a P-channel enhanced high-voltage MOS (metal oxide semiconductor) transistor PM5 and a drain electrode of an N-channel enhanced MOS transistor NM6, the other input end of the logic circuit module is connected with a drain electrode of a P-channel enhanced high-voltage MOS transistor PM4 and a drain electrode of an N-channel enhanced MOS transistor NM5, and the output end of the logic circuit module is connected with the input end of the driving circuit;
the input end of the drive circuit module is connected with the output end of the logic circuit module, and the output end of the drive circuit module is connected with the grid electrode of an N-channel enhanced high-voltage power switch tube NM 7;
the grid electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the output end of the drive circuit module, the drain electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the other end of the resistor R2, and the source electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the.
When a VCC end is connected to a voltage VIN circuit to work, because the source and the drain of the resistors R1 and R2 and the power tube NM7 are in series connection, the current passing through the source and the drain of the power tube NM7 is equal to the current passing through the resistors R1 and R2, and after the voltage VIN passes through the other end of the resistor R1, the voltage is reduced to VR1RAfter the voltage at the two ends of the resistor R1 passes through the resistors R3 and R4 respectively, the voltage transmitted to the source end of the P-channel enhanced high-voltage MOS transistor PM1 is compared with the voltage at the source end of the P-channel enhanced high-voltage MOS transistor PM2, and as the resistors R3 and R4 have the same size and resistance, the voltage drops generated by the resistors R3 and R4 cancel each other out, that is, the voltage at the two ends of the resistor R1 is compared by the voltage comparator circuit formed by the P-channel enhanced high-voltage MOS transistors PM1 and PM2, and the current passing through the R1 end is determined to be:
I1＝(VIN-VR1R)/R1 (1)
the drain electrode of the P-channel enhanced high-voltage MOS tube PM2 transmits the comparison result of the voltage to the grid electrode of the P-channel enhanced high-voltage MOS tube PM4, and the P-channel enhanced high-voltage MOS tube PM4 converts the voltage signal on the grid electrode into a digital signal for switching on and off the grid drain electrode; similarly, the voltage from VIN passing through resistors R1 and R2 to the other end of resistor R2 is denoted as VR2RThe voltage V at the other end of the resistor R2R2RCompared with the voltage transmitted to the source end of the P-channel enhanced high-voltage MOS tube PM3 through the resistor R5 and the voltage VIN at the VCC input end transmitted to the source end of the P-channel enhanced high-voltage MOS tube PM1 after passing through the resistor R3, because the sizes and the resistances of the resistor R3 and the resistor R5 are the same, the voltage drops generated by the resistor R3 and the resistor R5 are mutually counteracted, namely the P-channel enhancement is realizedThe voltage comparator circuit formed by the type high-voltage MOS tubes PM1 and PM3 compares the voltage VCC at the input end with the voltage V at the other end of the resistor R2R2RThe magnitude of the current through the terminal R2 is determined as:
I2＝(VIN-VR2R)/R2 (2)
the drain electrode of the P-channel enhanced high-voltage MOS tube PM3 transmits the comparison result of the voltage to the grid electrode of the P-channel enhanced high-voltage MOS tube PM5, and the P-channel enhanced high-voltage MOS tube PM5 converts the voltage signal on the grid electrode into a digital signal for switching on and off the grid drain electrode; the control circuit module controls the on-off of the gates of the P-channel enhancement type MOS switching tubes PM6 and PM7 according to the chip logic judgment relation, and the on-off of the over-current detection circuit is controlled.
When the control circuit module turns off the switching tubes PM6 and PM7, the whole circuit judges whether the current passing through the resistors R1 and R2 exceeds the maximum current set value set by the circuit or not through the logic circuit module, and transmits the comparison result to the driving circuit module in a high level or low level mode, and the driving circuit module controls the switching of the grid electrode of the N-channel enhanced high-voltage power switching tube NM7 after internal conversion through the driving circuit according to the result transmitted by the logic circuit module, so that the on-off of the whole circuit is controlled, the circuit method for multi-path control over-current detection is realized, and the detection of load current in the circuit is more effective.
The invention has the beneficial effects that:
1. the whole circuit is simple in design, can be completed by adopting a CMOS (complementary metal oxide semiconductor) process, is high in response speed and bandwidth, and can respond within 1 us.
2. The circuit can set different current limiting values at different temperatures, and the reduction of the current limiting value when the temperature rises can be realized, so that the whole circuit is more effectively protected, and the phenomenon that the power tube is burnt down due to overlarge current to damage the whole chip is avoided.
3. A plurality of overcurrent detection points can be set according to the actual condition in the circuit, and only corresponding detection circuits need to be added, so that the simple and reliable circuit is realized.
Drawings
Fig. 1 is a schematic diagram of a multi-path high-speed broadband overcurrent detection circuit for a load switch according to the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples. A multi-path high-speed broadband overcurrent detection circuit for a load switch comprises P-channel enhanced high-voltage MOS tubes PM1, PM2, PM3, PM4, PM5, P-channel enhanced MOS tubes PM6, PM7, N-channel enhanced MOS tubes NM1, NM2, NM3, NM4, NM5 and NM6, N-channel enhanced high-voltage power switch tubes NM7, resistors R1, R2, R3, R4, R5, R6, R7 and R8, a current source 1, a control circuit module, a logic circuit module, a driving circuit module, an input VCC port and an output IDC VOUT port;
the VCC port is connected with an external input power supply end, and the VOUT port is an output port of the whole circuit.
One end of the current source IDC1 is connected with an input VCC port, and the other end of the current source IDC1 is connected with the grid drain of an N-channel enhancement type MOS tube NM1 and the grids of NM2, NM3, NM4, NM5 and NM 6; the drain electrode of the grid electrode of the N-channel enhancement type MOS tube NM1 is connected with the other end of the current source IDC1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM3, NM4, NM5 and NM6, and the source electrode of the N-channel enhancement type MOS tube NM1 is grounded; the grid electrode of the N-channel enhancement type MOS transistor NM2 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS transistor NM1, the grid electrodes of NM3, NM4, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the grid electrode drain electrode of the P-channel enhancement type high-voltage MOS transistor PM1 and the grid electrodes of PM2 and PM3, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM3 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM4, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM2 and the grid electrode of the P-channel enhancement type high-voltage MOS tube PM4, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM4 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM3 and the grid electrode of the P-channel enhancement type high-voltage MOS tube PM5, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM5 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM4 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM4, the source electrode of the P-channel enhancement type MOS tube PM6 and the other input end of the logic circuit, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM6 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM4 and NM5 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM5, the source electrode of the P-channel enhancement type MOS tube PM7 and the input end of the logic circuit, and the source electrode is grounded. The current source IDC1 and the N-channel enhancement type MOS transistors NM1, NM2, NM3, NM4, NM5 and NM6 jointly form a current mirror circuit, and mirror currents are provided for branches where the N-channel enhancement type MOS transistors NM1, NM2, NM3, NM4, NM5 and NM6 are located.
The drain electrode of the grid electrode of the P-channel enhanced high-voltage MOS tube PM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM2 and the grid electrodes of the P-channel enhanced high-voltage MOS tubes PM2 and PM3, and the source electrode of the P-channel enhanced high-voltage MOS tube PM1 is connected with the other end of the resistor R3; the grid electrode of the P-channel enhanced high-voltage MOS tube PM2 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode drain electrode of the P-channel enhanced high-voltage MOS tube PM1 and the grid electrode of the PM3, the drain electrode is connected with the drain electrode of the N-channel enhanced MOS tube NM3 and the grid electrode of the P-channel enhanced high-voltage MOS tube PM4, and the source electrode is connected with the other end of the resistor R4; the grid electrode of the P-channel enhanced high-voltage MOS tube PM3 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode drain electrode of the P-channel enhanced high-voltage MOS tube PM1 and the grid electrode of the PM2, the drain electrode is connected with the drain electrode of the N-channel enhanced MOS tube NM4 and the grid electrode of the P-channel enhanced high-voltage MOS tube PM5, and the source electrode is connected with the other end of the resistor R5; the grid electrode of the P-channel enhanced high-voltage MOS tube PM4 is connected with the drain electrode of the P-channel enhanced high-voltage MOS tube PM2 and the drain electrode of the N-channel enhanced MOS tube NM3, the drain electrode is connected with the source electrode of the P-channel enhanced MOS tube PM6, the drain electrode of the N-channel enhanced MOS tube NM5 and the other input end of the logic circuit module, and the source electrode is connected with the other end of the resistor R6; the grid electrode of the P-channel enhanced high-voltage MOS tube PM5 is connected with the drain electrode of the P-channel enhanced high-voltage MOS tube PM3 and the drain electrode of the N-channel enhanced MOS tube NM4, the drain electrode is connected with the source electrode of the P-channel enhanced MOS tube PM7, the drain electrode of the N-channel enhanced MOS tube NM6 and one input end of the logic circuit module, and the source electrode is connected with the other end of the resistor R7; the grid electrode of the P-channel enhanced MOS tube PM6 is connected with the output end of the control circuit and the grid electrode of the P-channel enhanced MOS tube PM7, the drain electrode of the P-channel enhanced MOS tube PM7 is connected with the drain electrode of the P-channel enhanced MOS tube PM 8 and one end of a resistor R8, and the source electrode of the P-channel enhanced high-voltage MOS tube PM4 is connected with the drain electrode of the N-channel enhanced MOS tube NM5 and the other input end of the logic circuit module; the grid electrode of the P-channel enhanced type MOS tube PM7 is connected with the output end of the control circuit and the grid electrode of the P-channel enhanced type MOS tube PM6, the drain electrode of the P-channel enhanced type MOS tube PM6 is connected with one end of a resistor R8, and the source electrode of the P-channel enhanced type MOS tube PM5 is connected with the drain electrode of the P-channel enhanced type high-voltage MOS tube PM6, the drain electrode of the N-channel enhanced type MOS tube NM6 and one input. The P-channel enhanced high-voltage MOS tubes PM1, PM2 and PM3 form a voltage comparator circuit, the P-channel enhanced high-voltage MOS tubes PM4 and PM5 form output circuits of PM2 and PM3 drain branches respectively, and the P-channel enhanced MOS tubes PM6 and PM7 are used as switching tubes.
One end of the resistor R1 is connected with the input VCC port, the input end of the current source IDC1, one end of the resistor R3, one end of the resistor R6 and one end of the resistor R7, and the other end of the resistor R1 is connected with one end of the resistor R2 and one end of the resistor R4; one end of the resistor R2 is connected with the other end of the resistor R1 and one end of the resistor R4, and the other end of the resistor R2 is connected with one end of the resistor R5 and the drain electrode of the N-channel enhanced high-voltage power switch tube NM 7; one end of the resistor R3 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R6 and one end of the resistor R7, and the other end of the resistor R3 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 1; one end of the resistor R4 is connected with the other end of the resistor R1 and one end of the resistor R2, and the other end of the resistor R4 is connected with the source electrode of the P-channel enhanced high-voltage MOS transistor PM 2; one end of the resistor R5 is connected with the other end of the resistor R2 and the drain electrode of the N-channel enhanced high-voltage power switch tube NM7, and the other end of the resistor R5 is connected with the source electrode of the P-channel enhanced high-voltage MOS tube PM 3; one end of the resistor R6 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R3 and one end of the resistor R7, and the other end of the resistor R6 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 4; one end of the resistor R7 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R3 and one end of the resistor R6, and the other end of the resistor R7 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 5; one end of the resistor R8 is connected with the drains of the P-channel enhancement type MOS tube PM6 and the PM7, and the other end of the resistor R8 is connected with the ground; the resistors R1 and R2 adopt metal resistors with negative temperature coefficients, work in a linear region, and effectively sample the current of the source electrode and the drain electrode of the NM7 of the N-channel enhanced high-voltage power switching tube in time; the resistors R3, R4, R5, R6 and R7 are used as loads of respective branches of the P-channel enhancement type high-voltage MOS transistors PM1, PM2, PM3, PM4 and PM5 and play a role in voltage division, the resistances and the sizes of the resistors R4, R5, R6 and R7 are the same, and the resistor R8 is used as a load of a drain branch of the P-channel enhancement type MOS transistors PM6 and PM7 and plays a role in voltage division.
The output end of the control circuit module is connected with the gates of the P-channel enhancement type MOS tubes PM6 and PM 7; one input end of the logic circuit module is connected with a drain electrode of a P-channel enhanced high-voltage MOS (metal oxide semiconductor) transistor PM5 and a drain electrode of an N-channel enhanced MOS transistor NM6, the other input end of the logic circuit module is connected with a drain electrode of a P-channel enhanced high-voltage MOS transistor PM4 and a drain electrode of an N-channel enhanced MOS transistor NM5, and the output end of the logic circuit module is connected with the input end of the driving circuit;
the input end of the drive circuit module is connected with the output end of the logic circuit module, and the output end of the drive circuit module is connected with the grid electrode of an N-channel enhanced high-voltage power switch tube NM 7;
the grid electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the output end of the drive circuit module, the drain electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the other end of the resistor R2, and the source electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the.
When a VCC end is connected to a voltage VIN circuit to work, because the source and the drain of the resistors R1 and R2 and the power tube NM7 are in series connection, the current passing through the source and the drain of the power tube NM7 is equal to the current passing through the resistors R1 and R2, and after the voltage VIN passes through the other end of the resistor R1, the voltage is reduced to VR1RAfter the voltage at the two ends of the resistor R1 passes through the resistors R3 and R4 respectively, the voltage transmitted to the source end of the P-channel enhanced high-voltage MOS transistor PM1 is compared with the voltage at the source end of the P-channel enhanced high-voltage MOS transistor PM2, and as the resistors R3 and R4 have the same size and resistance, the voltage drops generated by the resistors R3 and R4 cancel each other out, that is, the voltage at the two ends of the resistor R1 is compared by the voltage comparator circuit formed by the P-channel enhanced high-voltage MOS transistors PM1 and PM2, and the current passing through the R1 end is determined to be:
I1＝(VIN-VR1R)/R1 (1)
the drain electrode of the P-channel enhanced high-voltage MOS tube PM2 transmits the comparison result of the voltage to the grid electrode of the P-channel enhanced high-voltage MOS tube PM4, and the P-channel enhanced high-voltage MOS tube PM4 converts the voltage signal on the grid electrode into a digital signal for switching on and off the grid drain electrode; similarly, the voltage from VIN passing through resistors R1 and R2 to the other end of resistor R2 is denoted as VR2RThe voltage V at the other end of the resistor R2R2RThe voltage is transmitted to the source end of a P-channel enhanced high-voltage MOS tube PM3 through a resistor R5, and compared with the voltage transmitted to the source end of a P-channel enhanced high-voltage MOS tube PM1 after a voltage VIN at a VCC input end passes through a resistor R3, as the sizes and the resistance values of the resistors R3 and R5 are the same, voltage drops generated by the resistors R3 and R5 are mutually offset, namely the P-channel enhanced high-voltage MOS tubes PM1 and PM3 form a voltage comparator circuit for comparing the voltage VCC at the input end with the voltage V at the other end of the resistor R2R2RThe magnitude of the current through the terminal R2 is determined as:
I2＝(VIN-VR2R)/R2 (2)
the drain electrode of the P-channel enhanced high-voltage MOS tube PM3 transmits the comparison result of the voltage to the grid electrode of the P-channel enhanced high-voltage MOS tube PM5, and the P-channel enhanced high-voltage MOS tube PM5 converts the voltage signal on the grid electrode into a digital signal for switching on and off the grid drain electrode; the control circuit module controls the on-off of the gates of the P-channel enhancement type MOS switching tubes PM6 and PM7 according to the chip logic judgment relation, and the on-off of the over-current detection circuit is controlled.
When the control circuit module turns off the switching tubes PM6 and PM7, the whole circuit judges whether the current passing through the resistors R1 and R2 exceeds the maximum current set value set by the circuit or not through the logic circuit module, and transmits the comparison result to the driving circuit module in a high level or low level mode, and the driving circuit module controls the switching of the grid electrode of the N-channel enhanced high-voltage power switching tube NM7 after internal conversion through the driving circuit according to the result transmitted by the logic circuit module, so that the on-off of the whole circuit is controlled, the circuit method for multi-path control over-current detection is realized, and the detection of load current in the circuit is more effective.
In summary, the invention provides a multi-path high-speed broadband overcurrent detection circuit for a load switch, which can effectively perform overcurrent detection and ensure the safety and reliability of the circuit. Compared with the prior overcurrent detection circuit, the method has the advantages that the whole circuit design is simple, the overcurrent of the circuit is well protected, the internal power consumption of the circuit is low, and the overcurrent protection effect on other circuits is good.
Claims (1)
1. A multi-path high-speed broadband overcurrent detection circuit for a load switch comprises P-channel enhanced high-voltage MOS tubes PM1, PM2, PM3, PM4, PM5, P-channel enhanced MOS tubes PM6, PM7, N-channel enhanced MOS tubes NM1, NM2, NM3, NM4, NM5 and NM6, N-channel enhanced high-voltage power switch tubes NM7, resistors R1, R2, R3, R4, R5, R6, R7 and R8, a current source 1, a control circuit module, a logic circuit module, a driving circuit module, an input VCC port and an output IDC VOUT port, and is characterized in that:
the VCC port is connected with an external input power supply end, and the VOUT port is an output port of the whole circuit;
one end of the current source IDC1 is connected with an input VCC port, and the other end of the current source IDC1 is connected with the grid drain of an N-channel enhancement type MOS tube NM1 and the grids of NM2, NM3, NM4, NM5 and NM 6; the drain electrode of the grid electrode of the N-channel enhancement type MOS tube NM1 is connected with the other end of the current source IDC1 and the grid electrodes of the N-channel enhancement type MOS tubes NM2, NM3, NM4, NM5 and NM6, and the source electrode of the N-channel enhancement type MOS tube NM1 is grounded; the grid electrode of the N-channel enhancement type MOS transistor NM2 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS transistor NM1, the grid electrodes of NM3, NM4, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the grid electrode drain electrode of the P-channel enhancement type high-voltage MOS transistor PM1 and the grid electrodes of PM2 and PM3, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM3 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM4, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM2 and the grid electrode of the P-channel enhancement type high-voltage MOS tube PM4, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM4 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM5 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM3 and the grid electrode of the P-channel enhancement type high-voltage MOS tube PM5, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM5 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM4 and NM6 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM4, the source electrode of the P-channel enhancement type MOS tube PM6 and the other input end of the logic circuit, and the source electrode is grounded; the grid electrode of the N-channel enhancement type MOS tube NM6 is connected with the grid electrode drain electrode of the N-channel enhancement type MOS tube NM1, the grid electrodes of NM2, NM3, NM4 and NM5 and the output end of the current source IDC1, the drain electrode is connected with the drain electrode of the P-channel enhancement type high-voltage MOS tube PM5, the source electrode of the P-channel enhancement type MOS tube PM7 and the input end of the logic circuit, and the source electrode is grounded; the current source IDC1 and the N-channel enhancement type MOS transistors NM1, NM2, NM3, NM4, NM5 and NM6 jointly form a current mirror circuit, and mirror currents are provided for branches where the N-channel enhancement type MOS transistors NM1, NM2, NM3, NM4, NM5 and NM6 are located;
the drain electrode of the grid electrode of the P-channel enhanced high-voltage MOS tube PM1 is connected with the drain electrode of the N-channel enhanced MOS tube NM2 and the grid electrodes of the P-channel enhanced high-voltage MOS tubes PM2 and PM3, and the source electrode of the P-channel enhanced high-voltage MOS tube PM1 is connected with the other end of the resistor R3; the grid electrode of the P-channel enhanced high-voltage MOS tube PM2 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode drain electrode of the P-channel enhanced high-voltage MOS tube PM1 and the grid electrode of the PM3, the drain electrode is connected with the drain electrode of the N-channel enhanced MOS tube NM3 and the grid electrode of the P-channel enhanced high-voltage MOS tube PM4, and the source electrode is connected with the other end of the resistor R4; the grid electrode of the P-channel enhanced high-voltage MOS tube PM3 is connected with the drain electrode of the N-channel enhanced MOS tube NM2, the grid electrode drain electrode of the P-channel enhanced high-voltage MOS tube PM1 and the grid electrode of the PM2, the drain electrode is connected with the drain electrode of the N-channel enhanced MOS tube NM4 and the grid electrode of the P-channel enhanced high-voltage MOS tube PM5, and the source electrode is connected with the other end of the resistor R5; the grid electrode of the P-channel enhanced high-voltage MOS tube PM4 is connected with the drain electrode of the P-channel enhanced high-voltage MOS tube PM2 and the drain electrode of the N-channel enhanced MOS tube NM3, the drain electrode is connected with the source electrode of the P-channel enhanced MOS tube PM6, the drain electrode of the N-channel enhanced MOS tube NM5 and the other input end of the logic circuit module, and the source electrode is connected with the other end of the resistor R6; the grid electrode of the P-channel enhanced high-voltage MOS tube PM5 is connected with the drain electrode of the P-channel enhanced high-voltage MOS tube PM3 and the drain electrode of the N-channel enhanced MOS tube NM4, the drain electrode is connected with the source electrode of the P-channel enhanced MOS tube PM7, the drain electrode of the N-channel enhanced MOS tube NM6 and one input end of the logic circuit module, and the source electrode is connected with the other end of the resistor R7; the grid electrode of the P-channel enhanced MOS tube PM6 is connected with the output end of the control circuit and the grid electrode of the P-channel enhanced MOS tube PM7, the drain electrode of the P-channel enhanced MOS tube PM7 is connected with the drain electrode of the P-channel enhanced MOS tube PM 8 and one end of a resistor R8, and the source electrode of the P-channel enhanced high-voltage MOS tube PM4 is connected with the drain electrode of the N-channel enhanced MOS tube NM5 and the other input end of the logic circuit module; the grid electrode of the P-channel enhanced type MOS tube PM7 is connected with the output end of the control circuit and the grid electrode of the P-channel enhanced type MOS tube PM6, the drain electrode of the P-channel enhanced type MOS tube PM6 is connected with the drain electrode of the P-channel enhanced type MOS tube PM 8 and one end of a resistor R8, and the source electrode of the P-channel enhanced type MOS tube PM5 is connected with the drain electrode of the N-channel enhanced type MOS tube NM6 and one input end of the; the P-channel enhanced high-voltage MOS tubes PM1, PM2 and PM3 form a voltage comparator circuit, the P-channel enhanced high-voltage MOS tubes PM4 and PM5 form an output circuit of a PM2 drain branch circuit and a PM3 drain branch circuit respectively, and the P-channel enhanced MOS tubes PM6 and PM7 are used as switching tubes;
one end of the resistor R1 is connected with the input VCC port, the input end of the current source IDC1, one end of the resistor R3, one end of the resistor R6 and one end of the resistor R7, and the other end of the resistor R1 is connected with one end of the resistor R2 and one end of the resistor R4; one end of the resistor R2 is connected with the other end of the resistor R1 and one end of the resistor R4, and the other end of the resistor R2 is connected with one end of the resistor R5 and the drain electrode of the N-channel enhanced high-voltage power switch tube NM 7; one end of the resistor R3 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R6 and one end of the resistor R7, and the other end of the resistor R3 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 1; one end of the resistor R4 is connected with the other end of the resistor R1 and one end of the resistor R2, and the other end of the resistor R4 is connected with the source electrode of the P-channel enhanced high-voltage MOS transistor PM 2; one end of the resistor R5 is connected with the other end of the resistor R2 and the drain electrode of the N-channel enhanced high-voltage power switch tube NM7, and the other end of the resistor R5 is connected with the source electrode of the P-channel enhanced high-voltage MOS tube PM 3; one end of the resistor R6 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R3 and one end of the resistor R7, and the other end of the resistor R6 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 4; one end of the resistor R7 is connected with an input VCC port and one end of the resistor R1, one end of the resistor R3 and one end of the resistor R6, and the other end of the resistor R7 is connected with the source electrode of the P-channel enhancement type high-voltage MOS transistor PM 5; one end of the resistor R8 is connected with the drains of the P-channel enhancement type MOS tube PM6 and the PM7, and the other end of the resistor R8 is connected with the ground; the resistors R1 and R2 adopt metal resistors with negative temperature coefficients, work in a linear region, and effectively sample the current of the source electrode and the drain electrode of the NM7 of the N-channel enhanced high-voltage power switching tube in time; resistors R3, R4, R5, R6 and R7 are used as loads of respective branches of P-channel enhancement type high-voltage MOS transistors PM1, PM2, PM3, PM4 and PM5 to play a role of voltage division, the resistances and the sizes of the resistors R4, R5, R6 and R7 are the same, and the resistor R8 is used as a load of a drain branch of the P-channel enhancement type MOS transistors PM6 and PM7 to play a role of voltage division;
the output end of the control circuit module is connected with the gates of the P-channel enhancement type MOS tubes PM6 and PM 7; one input end of the logic circuit module is connected with a drain electrode of a P-channel enhanced high-voltage MOS (metal oxide semiconductor) transistor PM5 and a drain electrode of an N-channel enhanced MOS transistor NM6, the other input end of the logic circuit module is connected with a drain electrode of a P-channel enhanced high-voltage MOS transistor PM4 and a drain electrode of an N-channel enhanced MOS transistor NM5, and the output end of the logic circuit module is connected with the input end of the driving circuit;
the input end of the drive circuit module is connected with the output end of the logic circuit module, and the output end of the drive circuit module is connected with the grid electrode of an N-channel enhanced high-voltage power switch tube NM 7;
the grid electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the output end of the drive circuit module, the drain electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the other end of the resistor R2, and the source electrode of the N-channel enhanced high-voltage power switch tube NM7 is connected with the.
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| CN201921673329.9U CN210536599U (en) | 2019-10-08 | 2019-10-08 | Multi-path high-speed broadband overcurrent detection circuit for load switch |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110719093A (en) * | 2019-10-08 | 2020-01-21 | 西安拓尔微电子有限责任公司 | Multi-path high-speed broadband overcurrent detection circuit for load switch and control method |
| CN113466538A (en) * | 2021-07-06 | 2021-10-01 | 上海泰矽微电子有限公司 | Small current detection circuit in load switch and detection method thereof |
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2019
- 2019-10-08 CN CN201921673329.9U patent/CN210536599U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110719093A (en) * | 2019-10-08 | 2020-01-21 | 西安拓尔微电子有限责任公司 | Multi-path high-speed broadband overcurrent detection circuit for load switch and control method |
| CN110719093B (en) * | 2019-10-08 | 2024-05-24 | 拓尔微电子股份有限公司 | Multipath high-speed broadband overcurrent detection circuit for load switch and control method |
| CN113466538A (en) * | 2021-07-06 | 2021-10-01 | 上海泰矽微电子有限公司 | Small current detection circuit in load switch and detection method thereof |
| CN113466538B (en) * | 2021-07-06 | 2022-03-22 | 上海泰矽微电子有限公司 | Small current detection circuit in load switch and detection method thereof |
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Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: Xi'an Tuoer Microelectronics Co.,Ltd. Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Xi'an Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: XI'AN TUOER MICROELECTRONICS Co.,Ltd. |