CN211377998U

CN211377998U - Drive circuit and battery protection system

Info

Publication number: CN211377998U
Application number: CN201922205528.3U
Authority: CN
Inventors: 常星; 王钊; 尹航
Original assignee: Wuxi Vimicro Corp
Current assignee: Wuxi Vimicro Corp
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2020-08-28
Anticipated expiration: 2029-12-11

Abstract

The utility model discloses a drive circuit and battery protection system, drive circuit includes the control unit, establish ties first switching element and first resistance between first electrode and second electrode and with first resistance parallelly connected and have the second switching element than the resistance that first resistance is little when switching on, the protection pin of the control end of connecting the third switching element is located between first switching element and first resistance, under the first state, the control unit control second switching element ends, first switching element switches on and forms the route, protection pin output enables the first electrode voltage that third switching element switched on; in the second state, the control unit controls the first switching device to be cut off, and the second switching device to be turned on for a set time to enable the protection pin to output a second electrode voltage which can enable the third switching device to be cut off and then to be cut off. The utility model discloses a drive circuit and battery protection system can avoid the strong drive that produces negative effect and can realize guaranteeing the switching speed of outside third switch device to electromagnetic interference.

Description

Drive circuit and battery protection system

Technical Field

The utility model relates to an electronic circuit technical field especially relates to a drive circuit and battery protection system.

Background

Currently, a battery protection circuit includes a driving circuit for driving an external MOSFET (a MOSFET is a MOS-Metal oxide semiconductor, FET-Field Effect Transistor, or a Field Effect Transistor in which a gate of a Metal layer M controls a semiconductor S by an electric Field Effect through an oxide layer O). Under the condition of over-strong driving (namely, the equivalent resistance in the circuit is small, and the current is strong), the EMI (Electro magnetic interference) of the chip has certain negative influence; under the condition of over-weak driving (namely large equivalent resistance and weak current in the circuit), the switching speed of the MOSFET is greatly reduced.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming above-mentioned technical problem, provide a drive circuit, this drive circuit can avoid the drive too strong and produce negative effect to electromagnetic interference and can realize the strong drive in order to guarantee to outside such as MOSFET's switching device's switching speed.

Another object of the present invention is to provide a battery protection system including the above driving circuit.

In order to achieve the above object, the present invention provides a driving circuit, including a control unit, a first switching device and a first resistor connected in series between a first electrode and a second electrode, and a second switching device connected in parallel with the first resistor, the second switching device having a resistance smaller than the first resistor when turned on, a protection pin for connecting with a control terminal of a third switching device being provided between the first switching device and the first resistor, wherein: in a first state, the control unit controls the second switching device to be turned off and simultaneously controls the first switching device to be turned on to form a path between the first electrode and the second electrode through a first resistor, so that a protection pin outputs a voltage of the first electrode capable of turning on the third switching device; in a second state, the control unit controls the first switching device to be turned off and simultaneously controls the second switching device to be turned on for a set time so that the protection pin outputs a voltage of the second electrode which can turn off the third switching device and then turns off.

In some embodiments, the first switching device is a first PMOS transistor, the drain of which is connected to the first resistor, the source of which is connected to the first electrode, and the gate of which is connected to the output terminal of the control unit.

In some embodiments, the second switch device is a first NMOS transistor, a drain thereof is connected to one end of the first resistor connected to the first switch device, a source thereof is connected to the other end of the first resistor, and a gate thereof is coupled to the output terminal of the control unit.

In some embodiments, the second switching device is a second PMOS transistor, the source thereof is connected to one end of the first resistor connected to the first switching device, the drain thereof is connected to the other end of the first resistor, and the gate thereof is coupled to the output terminal of the control unit.

In some embodiments, the driving circuit further includes a second NMOS transistor, a current mirror unit, and a second resistor, wherein a substrate of the second NMOS transistor is connected to a third electrode, a source thereof is connected to a current bias source, a gate thereof is connected to an output terminal of the control unit, and a drain thereof is connected to an input terminal of the current mirror unit, a voltage of the third electrode is smaller than a voltage of the first electrode and a voltage of the second electrode, an output terminal of the current mirror unit is coupled to one end of the second resistor, the other end of the second resistor is connected to the second electrode, and a control terminal of the second switching device is coupled between the output terminal of the current mirror unit and the second resistor.

In some embodiments, the driving circuit includes a third NMOS transistor having a drain and a gate connected to the other end of the second resistor, and a source connected to the second electrode.

In some embodiments, the current mirror unit includes a third PMOS transistor and a fourth PMOS transistor, a source of the third PMOS transistor and a source of the fourth PMOS transistor are connected to the first electrode, a drain and a gate of the third PMOS transistor and a gate of the fourth PMOS transistor are connected to a drain of the second NMOS transistor, and a drain of the fourth PMOS transistor is coupled to one end of the second resistor.

In some embodiments, the driving circuit includes a fifth PMOS transistor, a source of which is connected to a drain of the fourth PMOS transistor, a drain of which is connected to one end of the second resistor, a gate of which is connected to the third electrode, and a control terminal of the second switching device is connected between the fifth PMOS transistor and the second resistor.

In some embodiments, the third switching device is a MOS transistor, and the first electrode is a cell positive electrode of a battery, and the second electrode is a negative electrode of the battery; or, the first electrode is a battery cell cathode of the battery, and the second electrode is a battery anode.

The utility model discloses the second aspect provides a battery protection system, including the battery, be used for switching on or turn-off the discharge protection switch of discharge path and be used for switching on or turn-off the charge protection switch and the foretell drive circuit of charge path, the third switch device includes discharge protection switch with charge protection switch, the protection pin including charge protection pin with discharge protection pin, discharge protection pin with discharge protection switch's control end links to each other, charge protection pin with charge protection switch's control end links to each other.

In the above technical solution, since in a first state such as normal charging or discharging, the control unit controls the second switching device to be turned off and simultaneously controls the first switching device to be turned on, a path is formed between the first electrode and the second electrode through the first resistor, so that the protection pin outputs a voltage of the first electrode capable of turning on the third switching device, a resistor with a large resistance value is selected as the first resistor as required, the current in the circuit is weak, and negative influence on electromagnetic interference of electrical components such as a chip is avoided when the driving is too strong, and in a second state such as abnormal charging or discharging, the control unit controls the first switching device to be turned off and simultaneously controls the second switching device to be turned on for a set time so that the protection pin outputs a voltage of the second electrode capable of turning off the third switching device and then turns off, the second switch device has a resistance smaller than the first resistance when being turned on, so that the equivalent resistance in the circuit is smaller, the current is larger, strong driving can be realized, the voltage of the protection pin can be quickly changed from the voltage of the first electrode to the voltage of the second electrode within the set time so as to quickly turn off the third switch device, and the switching speed of the external third switch device such as a MOSFET is ensured. That is, this driving scheme ensures both that the driving of the protection pin in the first state is a weak driving determined by the first resistance, which is advantageous for electromagnetic interference, and a strong driving determined by the second switching device, which is fast off, when the external third switching device is required to be turned off to open the circuit such as the charge-discharge tube.

Other features and advantages of the present invention will be described in detail in the detailed description which follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a battery protection system;

fig. 2 is a schematic structural diagram of a driving circuit according to a first embodiment of the present invention;

FIG. 3 is a diagram of drive signals output by a control unit of the drive circuit of FIG. 2;

fig. 4 is a schematic structural diagram of a driving circuit according to a second embodiment of the present invention;

FIG. 5 is a diagram of drive signals output by a control unit of the drive circuit of FIG. 4;

fig. 6 is a schematic structural diagram of a driving circuit according to a third embodiment of the present invention;

fig. 7 is a view of driving signals output by a control unit of the driving circuit in fig. 6.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

An aspect of the present invention provides a driving circuit, including the control unit, series connection first switching device and first resistance R1 between first electrode and second electrode and with the parallelly connected second switching device of first resistance, the second switching device has when switching on and is less than first resistance R1's resistance for the protection pin of being connected with the control end of third switching device is located first switching device with between the first resistance R1, wherein: in a first state, the control unit controls the second switching device to be turned off and simultaneously controls the first switching device to be turned on to form a path between the first electrode and the second electrode through a first resistor R1, so that a protection pin outputs a voltage of the first electrode capable of turning on the third switching device; in a second state, the control unit controls the first switching device to be turned off and simultaneously controls the second switching device to be turned on for a set time so that the protection pin outputs a voltage of the second electrode which can turn off the third switching device and then turns off.

In the above technical solution, since the control unit controls the second switching device to be turned off and simultaneously controls the first switching device to be turned on in a first state such as normal charging or discharging, a path is formed between the first electrode and the second electrode through the first resistor R1, so that the protection pin outputs a voltage of the first electrode capable of turning on the third switching device, a resistor with a large resistance value is selected as the first resistor R1 as required, the current in the circuit is weak, and negative influence on electromagnetic interference of an electrical component such as a chip is avoided in the case of excessively strong driving, and in a second state such as abnormal charging or discharging, the control unit controls the first switching device to be turned off and simultaneously controls the second switching device to be turned on for a set time so that the protection pin outputs a voltage of the second electrode capable of turning off the third switching device to be turned off, because the second switch device has a resistance smaller than the first resistance R1 when being turned on, the equivalent resistance in the circuit is smaller, the current is larger, strong driving can be realized, the voltage of the protection pin can be quickly changed from the voltage of the first electrode to the voltage of the second electrode within a set time so as to quickly turn off the third switch device, and therefore the switching speed of the external third switch device such as a MOSFET is ensured. That is, this driving scheme ensures both that the driving of the protection pin in the first state is a weak driving favorable to electromagnetic interference determined by the first resistor R1 and a strong driving of a fast turn-off determined by the second switching device when the external third switching device is required to be turned off to open the circuit such as the charge and discharge tube.

The third switching device is an MOS transistor, specifically, a PMOS transistor or an NMOS transistor, and the first electrode is a positive electrode of a battery cell, and the second electrode is a negative electrode of the battery; or, the first electrode is a battery cell cathode of the battery, and the second electrode is a battery anode.

Fig. 1 is a schematic structural diagram of a battery protection system. As shown in fig. 1, the battery protection system includes a battery, a discharge protection switch 200 for turning on or off a discharge path, and a charge protection switch 300 for turning on or off a charge path, and the above-described driving circuit 100. The third switching device includes a discharge protection switch 200 and a charge protection switch 300, wherein two N-channel MOSFETs may be respectively used as the discharge protection switch 200 and the charge protection switch 300 to provide protection for the battery. The protection pins include a charge protection pin COUT and a discharge protection pin DOUT, the discharge protection pin DOUT is connected with the control end of the discharge protection switch 200, and the charge protection pin COUT is connected with the control end of the charge protection switch 300.

The first state can be when normal charging or discharging, and the second state can be when charging or discharging is abnormal, such as charging overvoltage or overcurrent, and discharging overvoltage or overcurrent. When the charging is over-voltage and/or over-current, the charging protection pin COUT outputs an effective charging protection signal to cut off the charging protection switch 300 and disconnect the charging path of the battery, thereby preventing the battery from being damaged due to over-charging; when the discharge overvoltage and/or the discharge overcurrent occur, the discharge protection pin DOUT outputs an effective discharge protection signal to turn off the discharge protection switch 200, so that the discharge path of the battery is cut off, thereby preventing the battery from being damaged by overdischarge.

As shown in fig. 1, when the first electrode is a cell positive electrode of the battery, and the second electrode is a negative electrode of the battery, a VCC pin connected to the cell positive electrode of the battery, a VSS pin connected to the cell negative electrode of the battery, and a VM pin connected to the negative electrode BP-of the battery may be provided, and the first switching device and the first resistor R1 of the driving circuit may be connected in series between the VCC pin and the VM pin.

The driving circuit may be provided with a charge protection pin COUT or a discharge protection pin DOUT, and the following description will take a pull-down driving of the charge protection pin COUT as an example.

Fig. 2 is a schematic structural diagram of a driving circuit according to a first embodiment of the present invention. As shown in fig. 2, the first switching device is a first PMOS transistor PM1, which is connected in series with a first resistor R1 between a VCC pin and a VM pin, specifically, the drain thereof is connected to the first resistor R1, the source thereof is connected to the first electrode, that is, to the VCC pin connected to the positive electrode of the battery cell, and the gate thereof is connected to the output terminal of the control unit. In addition, preferably, the second switching device is a first NMOS transistor NM1, a drain thereof is connected to the first resistor R1 at one end thereof, a source thereof is connected to the other end of the first resistor R1, and a gate thereof is coupled to the output terminal of the control unit.

Fig. 3 is a view of a driving signal output by a control unit of the driving circuit in fig. 2. As shown in fig. 3, during normal charging, CDRV and CDRV _ P are low level VM, at this time, PM1 is turned on, NM1 is turned off, a path is formed between the positive electrode of the battery cell (i.e., VCC pin) and the negative electrode BP of the battery (i.e., VM pin) through the first resistor R1, the first resistor R1 selects a large resistance resistor, so that the charge protection pin COUT outputs high level VCC, i.e., the control terminal of the charge protection switch 300 is high level, the charge protection switch 300 is turned on, and the external charging path is turned on. Because the resistance value of the first resistor R1 is large, the current in the circuit is weak, and the negative influence on the EMI of the battery protection chip under the condition of over-strong driving is avoided. With reference to fig. 3, when the charging is over-voltage and/or over-current, CDRV jumps to high VCC and maintains this state, PM1 is turned off, CDRV _ P also jumps to high VCC and jumps to low VM again after time T, CDRV _ P jumps to high VCC, NM1 is turned on, NM1 has a resistance smaller than the first resistance R1 when turned on, at this time, the equivalent resistance in the circuit is small, the current is large, strong driving can be achieved, the voltage of the charge protection pin COUT can be quickly pulled down from high VCC to low VM within a set time T, so that the charge protection switch 300 is turned off to turn off the charge path, and the switching speed of the external MOSFET is increased.

Fig. 4 is a schematic structural diagram of a driving circuit according to a second embodiment of the present invention. As shown in fig. 4, the second switching device is a second PMOS transistor, the source thereof is connected to the first resistor R1 and one end of the first switching device, the drain thereof is connected to the other end of the first resistor R1, and the gate thereof is coupled to the output terminal of the control unit.

Fig. 5 is a view of a driving signal output by a control unit of the driving circuit in fig. 4. As shown in fig. 5, during normal charging, CDRV is at a low level VM, PM1 is turned on, CDRV _ P is at a high level VCC, PM2 is turned off, a path is formed between a positive electrode of a battery cell (i.e., VCC pin) and a negative electrode BP of the battery (i.e., VM pin) through a first resistor R1, the first resistor R1 selects a large-resistance resistor, the charge protection pin COUT outputs the high level VCC, i.e., the control terminal of the charge protection switch 300 is at a high level, the charge protection switch 300 is turned on, and the external charging path is turned on. Because the resistance value of the first resistor R1 is large, the current in the circuit is weak, and the negative influence on the EMI of the battery protection chip under the condition of over-strong driving is avoided. With reference to fig. 5, when the charging is over-voltage and/or over-current, CDRV jumps to high VCC and maintains this state, PM1 is turned off, CDRV _ P also jumps to low VM and jumps to high VCC again after a time T, when CDRV _ P jumps to low VM, PM2 is turned on, since PM2 has a resistance smaller than the first resistance R1 when turned on, the equivalent resistance in the circuit is small, the current is large, strong driving can be achieved, the voltage of the charge protection pin COUT can be quickly pulled down from high VCC to low VM within a set time T, so that the charge protection switch 300 is turned off to turn off the charge path, and the switching speed of the external MOSFET is increased.

Fig. 6 is a schematic structural diagram of a driving circuit according to a third embodiment of the present invention. As shown in fig. 6, the driving circuit further includes a second NMOS transistor NM2, a current mirror unit 10 and a second resistor R2, wherein the substrate of the second NMOS transistor is connected to the third electrode, its source is connected to the current bias source IB, its gate is connected to the output terminal of the control unit, and its drain is connected to the input terminal of the current mirror unit 10, the voltage of the third electrode is less than the voltage of the first electrode and the voltage of the second electrode, wherein the third electrode may be a cell cathode of the battery, the substrate of the second NMOS transistor may be connected to a VSS pin connected to the cell cathode of the battery, the output terminal of the current mirror unit 10 is coupled to one terminal of the second resistor R2, the other terminal of the second resistor R2 is connected to the second electrode, i.e. to the VM pin connected to the negative pole of the battery, and the control terminal of the second switching device is coupled between the output terminal of the current mirror unit 10 and the second resistor R2.

Fig. 7 is a view of driving signals output by a control unit of the driving circuit in fig. 6. As shown in fig. 7, during normal charging, CDRV and CDRV _ P are low level VSS, at this time, PM1 is turned on, NM3 is turned off, the gate of NM1 is low level, NM1 is turned off, a path is formed between the positive electrode of the battery cell (i.e., VCC pin) and the negative electrode BP- (i.e., VM pin) of the battery through the first resistor R1, the first resistor R1 selects a high resistance resistor, so that the charge protection pin COUT outputs high level VCC, the charge protection switch 300 is turned on, and the external charging path is turned on. The resistance value of the first resistor R1 is large, so that the current in the circuit is weak, and the negative influence on the EMI of the battery protection chip under the condition of over-strong driving is avoided. With reference to fig. 7, when the charging is over-voltage and/or over-current, CDRV jumps to high VCC and maintains this state, PM1 is turned off, CDRV _ P also jumps to high VCC and jumps to low VCC again after time T, CDRV _ P jumps to high VCC, NM3 is turned on, NM1 has a gate of high level, NM1 is turned on, NM1 has a resistance smaller than the first resistance R1 when turned on, at this time, the equivalent resistance in the circuit is small, the current is large, strong driving can be achieved, the voltage of the charge protection pin COUT can be quickly pulled down from high VCC to low VM within a set time T, so that the charge protection switch 300 is turned off to turn off the charge path, and the switching speed to the external MOSFET is increased.

Further, as shown in fig. 6, the driving circuit includes a third NMOS transistor, whose drain and gate are connected to the other end of the second resistor R2, and whose source is connected to the second electrode, i.e., to the VM pin connected to the negative electrode of the battery. This allows the second switching device to be turned on even when the second resistor R2 is selected to have a small resistance. Specifically, when the second switching device is the first NMOS transistor NM1 and CDRV _ P is a high level VCC, the gate voltage of NM1 is greater than the source, and NM1 is turned on.

In addition, preferably, the current mirror unit 10 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4, a source of the third PMOS transistor PM3 and a source of the fourth PMOS transistor PM4 are connected to the first electrode, that is, to a VCC pin connected to a positive cell pole of a battery, a drain and a gate of the third PMOS transistor PM3 and a gate of the fourth PMOS transistor PM4 are connected to a drain of the second NMOS transistor NM2, and a drain of the fourth PMOS transistor PM4 is coupled to one end of the second resistor R2. The fourth PMOS transistor PM4 is thus able to replicate the current of the third PMOS transistor PM3 in a certain proportion.

In order to enable the third PMOS transistor PM3 and the fourth PMOS transistor PM4 to be low-voltage transistors for cost reduction, preferably, the driving circuit includes a fifth PMOS transistor PM5, a source of which is connected to the drain of the fourth PMOS transistor PM4, a drain of which is connected to one end of the second resistor R2, a gate of which is connected to the third electrode, i.e., to the VSS pin connected to the negative electrode of the battery cell, and a control terminal of the second switching device is connected between the fifth PMOS transistor PM5 and the second resistor R2.

In summary, the sizes of R2, NM1 and NM3 and the set time T of high level of CDRV _ P can be selected according to specific working requirements, when CDRV _ P is high level, the switching tube NM2 is turned on, and the R of NM1 is ensured by the current bias IB, the current determined by PM3 and PM4 and the voltages acting on R2 and NM3_ONThe drive requirement is met, and the COUT can be pulled down to the VM within the set time T; r of NM1 during CDRV _ P low level_ONAnd the resistance is far greater than R1, a path is formed between the positive electrode of the battery cell and the negative electrode of the battery through the first resistor R1, and the large resistor is selected as the first resistor R1 to enable the current in the circuit to be small. This driving scheme ensures both that the pull-down drive of COUT is a weak drive for EMI determined by R1 in most cases and a strong drive for fast turn-off determined by NM1 when external charging tube turn-off is required.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A drive circuit comprising a control unit, a first switching device and a first resistor connected in series between a first electrode and a second electrode, and a second switching device connected in parallel with the first resistor, the second switching device having a resistance less than the first resistor when turned on, a protection pin for connection with a control terminal of a third switching device being provided between the first switching device and the first resistor, wherein: in a first state, the control unit controls the second switching device to be turned off and simultaneously controls the first switching device to be turned on to form a path between the first electrode and the second electrode through a first resistor, so that a protection pin outputs a voltage of the first electrode capable of turning on the third switching device; in a second state, the control unit controls the first switching device to be turned off and simultaneously controls the second switching device to be turned on for a set time so that the protection pin outputs a voltage of the second electrode which can turn off the third switching device and then turns off.

2. The driving circuit of claim 1, wherein the first switching device is a first PMOS transistor, a drain thereof is connected to the first resistor, a source thereof is connected to the first electrode, and a gate thereof is connected to the output terminal of the control unit.

3. The driving circuit of claim 1, wherein the second switching device is a first NMOS transistor, a drain thereof is connected to one end of the first resistor connected to the first switching device, a source thereof is connected to the other end of the first resistor, and a gate thereof is coupled to the output terminal of the control unit.

4. The driving circuit of claim 1, wherein the second switching device is a second PMOS transistor, a source thereof is connected to one end of the first resistor connected to the first switching device, a drain thereof is connected to the other end of the first resistor, and a gate thereof is coupled to the output terminal of the control unit.

5. The driving circuit according to claim 1, further comprising a second NMOS transistor, a current mirror unit, and a second resistor, wherein the substrate of the second NMOS transistor is connected to a third electrode, the source thereof is connected to a current bias source, the gate thereof is connected to the output terminal of the control unit, and the drain thereof is connected to the input terminal of the current mirror unit, the voltage of the third electrode is smaller than the voltage of the first electrode and the voltage of the second electrode, the output terminal of the current mirror unit is coupled to one end of the second resistor, the other end of the second resistor is connected to the second electrode, and the control terminal of the second switching device is coupled between the output terminal of the current mirror unit and the second resistor.

6. The driving circuit according to claim 5, wherein the driving circuit comprises a third NMOS transistor having a drain and a gate connected to the other end of the second resistor, and a source connected to the second electrode.

7. The driving circuit of claim 5, wherein the current mirror unit comprises a third PMOS transistor and a fourth PMOS transistor, a source of the third PMOS transistor and a source of the fourth PMOS transistor are connected to the first electrode, a drain and a gate of the third PMOS transistor and a gate of the fourth PMOS transistor are connected to a drain of the second NMOS transistor, and a drain of the fourth PMOS transistor is coupled to one end of the second resistor.

8. The driving circuit of claim 7, wherein the driving circuit comprises a fifth PMOS transistor, a source of the fifth PMOS transistor is connected to a drain of the fourth PMOS transistor, a drain of the fifth PMOS transistor is connected to one end of the second resistor, a gate of the fifth PMOS transistor is connected to the third electrode, and a control terminal of the second switching device is connected between the fifth PMOS transistor and the second resistor.

9. The drive circuit according to any one of claims 1 to 8, wherein the third switching device is a MOS transistor, and,

the first electrode is a battery core anode of the battery, and the second electrode is a cathode of the battery; or the like, or, alternatively,

the first electrode is a battery core negative electrode of the battery, and the second electrode is a positive electrode of the battery.

10. A battery protection system comprising a battery, a discharge protection switch for turning on or off a discharge path and a charge protection switch for turning on or off a charge path, and a driving circuit according to any one of claims 1 to 9, wherein the third switching device comprises the discharge protection switch and the charge protection switch, the protection pin comprises a charge protection pin and the discharge protection pin, the discharge protection pin is connected to a control terminal of the discharge protection switch, and the charge protection pin is connected to a control terminal of the charge protection switch.