CN210467879U - Double-layer wafer plate - Google Patents

Abstract

The embodiment of the utility model provides a double-deck wafer board, include: a first wafer and a second wafer; the first wafer comprises a plurality of first chips which are arranged in a matrix manner; the second wafer comprises a plurality of second chips which are arranged in a matrix; the first chips are electrically connected with the second chips in a one-to-one correspondence manner to form a display chip module. The double-layer wafer plate can be cut to obtain a plurality of independent display chip modules, the process complexity of processing the display chip modules is reduced, and efficient processing of the display chip modules is facilitated.

Description

Double-layer wafer plate

Technical Field

The embodiment of the utility model provides a relate to reinforcing and show technical field, especially relate to a double-deck wafer board.

Background

With the development of display technology, people have higher and higher requirements on display devices, and in recent years, Micro-led display has attracted more and more attention as a new generation of display technology with the advantages of self-luminescence, simple structure, small volume and energy conservation. The Micro-LED is a display technology which is used for carrying out microminiaturization and matrixing on a traditional LED structure and manufacturing a driving circuit by adopting an integrated circuit process so as to realize addressing control and independent driving of each pixel point.

The existing process flow for manufacturing the Micro-LED display chip module is to cut a wafer with a plurality of Micro-LED driving chips and a wafer with a plurality of Micro-LED chips respectively to obtain single-grain Micro-LED driving chips and single-grain Micro-LED chips, and then bond the Micro-LED driving chips and the Micro-LED chips one by one to form the Micro-LED display chip module.

The processing method has the following defects: two cutting operations are needed in the process of manufacturing the Micro-LED display chip module, and the process is complicated; when the Micro-LED display chip module is manufactured, only single bonding is performed, and the bonding efficiency is low; and the consistency of different Micro-LED display chip modules is poor due to single bonding operation.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a double-deck wafer board for realize the high-efficient processing of display chip module.

The embodiment of the utility model provides a double-deck brilliant plectane, include: a first wafer and a second wafer;

the first wafer comprises a plurality of first chips which are arranged in a matrix manner;

the second wafer comprises a plurality of second chips which are arranged in a matrix;

the first chips are electrically connected with the second chips in a one-to-one correspondence manner to form a display chip module.

Preferably, the first wafer is made of a silicon wafer.

Preferably, the second wafer is made of a gallium nitride epitaxial wafer.

Preferably, the second chip is one of an LED chip, a small-pitch LED chip, a mini LED chip, and a Micro-LED chip.

Further, the first chip is one of an LED driving chip, a small-pitch LED driving chip, a mini LED driving chip, and a Micro-LED driving chip.

Preferably, alignment marks are arranged on the first wafer and the second wafer, and the first wafer and the second wafer are bonded after being aligned according to the alignment marks, so that the first chips are electrically connected to the second chips in a one-to-one correspondence manner, and a display chip module is formed.

Further, the alignment mark includes: a first alignment mark and a second alignment mark;

the first alignment mark is arranged on the first wafer;

the second alignment mark is arranged on the second wafer;

the number of the first alignment marks and the number of the second alignment marks are at least two.

The embodiment of the utility model provides a double-deck brilliant plectane, include: the display device comprises a first wafer and a second wafer, wherein the first wafer comprises a plurality of first chips which are arranged in a matrix mode, the second wafer comprises a plurality of second chips which are arranged in a matrix mode, and the first chips are electrically connected with the second chips in a one-to-one correspondence mode to form a display chip module. The double-layer wafer plate is cut, so that a plurality of independent display chip modules can be obtained, the process complexity of processing the display chip modules is reduced, and the efficient processing of the display chip modules is realized.

Drawings

Fig. 1 is a schematic structural diagram of a double-layer wafer plate according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a first wafer according to a first embodiment of the present invention;

fig. 3 is a schematic structural diagram of a second wafer according to a first embodiment of the present invention;

fig. 4 is a schematic structural diagram of a double-layer wafer plate according to a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of a first wafer according to a second embodiment of the present invention;

fig. 6 is a schematic structural diagram of a second wafer according to a second embodiment of the present invention;

fig. 7 is a schematic structural diagram of a first wafer in a single square region according to a second embodiment of the present invention;

fig. 8 is a schematic structural diagram of a second wafer in a single square region according to a second embodiment of the present invention;

fig. 9 is a schematic structural diagram of an independent display chip module according to a second embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

It is also noted that, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. And to avoid obscuring the invention with unnecessary details, only the structures and/or process steps closely related to the solution according to the invention are shown in the drawings, while other details not relevant to the invention are omitted.

Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, the first alignment mark may be referred to as the second alignment mark, and similarly, the second alignment mark may be referred to as the first alignment mark, without departing from the scope of the present invention. The first alignment mark and the second alignment mark are both alignment marks, but they are not the same alignment mark. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Example one

The embodiment of the utility model provides a double-deck wafer board is provided, as shown in FIG. 1 be the utility model provides a structural schematic diagram of double-deck brilliant plectane among the first, include: a first wafer 10 and a second wafer 20.

Specifically, as shown in fig. 2, the first wafer 10 includes a plurality of first chips 11 arranged in a matrix.

Specifically, as shown in fig. 3, the second wafer 20 includes a plurality of second chips 21 arranged in a matrix.

Preferably, the second chip 21 is one of a conventional LED chip, a small-pitch LED chip, a mini LED chip, and a Micro-LED chip, and correspondingly, the first chip 11 is one of a conventional LED driving chip, a small-pitch LED driving chip, a mini LED driving chip, and a Micro-LED driving chip. If the second chip 21 is a Micro-LED chip, the first chip 11 is a Micro-LED driving chip.

Preferably, the size and the number of the first chip 11 and the second chip 21 are the same, so that the first chip 11 and the second chip 21 are bonded, and the first chip 11 is electrically connected to the second chip 21 in a one-to-one correspondence, so as to form a display chip module.

It is further right the embodiment of the utility model provides a double-deck wafer board cuts, can obtain independent display chip module. The double-layer wafer plate can be cut by adopting a grinding wheel cutting technology, a diamond knife cutting technology or a laser cutting technology.

The embodiment of the utility model provides a double-deck brilliant plectane, including the first wafer and the second wafer of bonding, the second chip on the second wafer is connected to first chip one-to-one electricity on the first wafer, can further cut this double-deck wafer board in order to obtain a plurality of independent display chip modules, has reduced the technology complexity of display chip module processing, is favorable to the high-efficient processing of display chip module.

Example two

The embodiment two of the utility model provides a double-deck brilliant plectane, as shown in fig. 4 be the utility model discloses the structural schematic diagram of double-deck brilliant plectane in the embodiment two, include: a first wafer 30 and a second wafer 40.

Specifically, as shown in fig. 5, the first wafer 30 includes a plurality of first chips 31 arranged in a matrix.

Specifically, as shown in fig. 6, the second wafer 40 includes a plurality of second chips 41 arranged in a matrix.

Preferably, the second chip 41 is one of a conventional LED chip, a small-pitch LED chip, a mini LED chip, and a Micro-LED chip, and correspondingly, the first chip 31 is one of a conventional LED driving chip, a small-pitch LED driving chip, a mini LED driving chip, and a Micro-LED driving chip. If the second chip 41 is a Micro-LED chip, the first chip 31 is a Micro-LED driving chip.

Preferably, the first wafer 30 in the second embodiment of the present invention is made of a silicon wafer. Doping in a square area arranged in a matrix on the silicon wafer 300 according to a preset function to form a circuit element structure layer 310; a first electrode 320 and a second electrode 330 are formed on the circuit element structure layer 310. The first electrode 320 and the second electrode 330 may be made of the same or different materials, and include one or more of Ti (titanium), Al (aluminum), Au (gold), Cr (chromium), Pt (platinum), and Ni (nickel) for bonding with the second wafer. The first wafer 30 in the single square region as shown in fig. 7 can be obtained by filling the gap between the first electrode 320 and the second electrode 330 with an insulating material to form a first insulating layer 340. The preset function can be a Micro-LED switch driving function or a Micro-LED flicker driving function and the like.

Preferably, the second wafer 40 in the second embodiment of the present invention is made of a gallium nitride epitaxial wafer. The gallium nitride epitaxial wafer includes a sapphire substrate 400, a GaN (gallium nitride) -based buffer layer 410, and an N-type semiconductor layer 420, which are sequentially stacked. The N-type semiconductor layer 420 is made of N-type GaN. Dividing the gallium nitride epitaxial wafer into a plurality of square areas which are arranged in a matrix manner, and sequentially forming a multiple quantum well light-emitting layer 430, a P-type semiconductor layer 440 and a current expansion layer 450 on the gallium nitride epitaxial wafer in each area; etching the above structure to expose the N-type semiconductor layer 420 and form a through hole penetrating the current spreading layer 450, the P-type semiconductor layer 440 and the multiple quantum well light emitting layer 430; depositing the third electrode 460 in the via hole, depositing the fourth electrode 470 on the current spreading layer 450, and filling an insulating material between the third electrode 460 and the fourth electrode 470 to form an insulating layer 480, i.e. the second wafer 40 in a single square area as shown in fig. 8.

Wherein, the material of the multiple quantum well light emitting layer 430 is InGaN (indium gallium nitride) and/or GaN; the P-type semiconductor layer 440 is made of P-type GaN; the material of the current spreading layer 450 includes ITO (indium tin oxide), IZO (indium zinc oxide), and the like. The materials of the third electrode 460 and the fourth electrode 470 may be the same or different, and include: one or more of Ti, Al, Au, Cr, Pt and Ni.

Specifically, the size and the number of the first chip 31 and the second chip 41 are the same, so that the first chip 31 and the second chip 41 are bonded, and the first chip 31 is electrically connected to the second chip 41 in a one-to-one correspondence manner, so as to form a display chip module.

Preferably, alignment marks are disposed on the first wafer 30 and the second wafer 40, and are used for aligning the first wafer 30 and the second wafer 40 according to the alignment marks and then bonding the first chip 31 and the second chip 41.

Preferably, the alignment mark includes: the alignment marks include a first alignment mark 32 and a second alignment mark 42; the first alignment marks 32 are disposed on the first wafer 30, the second alignment marks 42 are disposed on the corresponding positions of the second wafer 40, and the number of the first alignment marks 32 and the number of the second alignment marks 42 are at least two. When the first wafer 30 and the second wafer 40 are bonded, only the first alignment mark 32 of the first wafer 30 needs to be aligned with the corresponding second alignment mark 42 of the second wafer 40, and then the first electrode 320 of the first wafer 30 is bonded with the third electrode 460 of the second wafer 40, and the second electrode 330 of the first wafer 30 is bonded 470 with the fourth electrode of the second wafer 40, so that the first chips 31 are electrically connected to the second chips 41 in a one-to-one correspondence manner, thereby forming a display chip module and obtaining a double-layer wafer.

It is further right the embodiment of the utility model provides a double-deck wafer board cuts, can obtain independent display chip module. The double-layer wafer plate can be cut by adopting a grinding wheel cutting technology, a diamond knife cutting technology or a laser cutting technology. The embodiment of the utility model provides an in can adopt stealthy laser cutting technique to cut apart double-deck wafer board, reducible mar and the damage on double-deck wafer board surface that produces because of the cutting obtain as shown in figure 9 independent display chip module, every independent display chip module includes first chip 31 and second chip 41.

The embodiment of the utility model provides a double-deck brilliant plectane, include: the display device comprises a first wafer and a second wafer, wherein the first wafer comprises a plurality of first chips which are arranged in a matrix mode, the second wafer comprises a plurality of second chips which are arranged in a matrix mode, and the first chips are electrically connected with the second chips in a one-to-one correspondence mode to form a display chip module. Invisible laser cutting is carried out on the double-layer wafer plate, a plurality of independent display chip modules can be obtained, scratches and damage on the surface of the double-layer wafer plate are reduced, the process complexity of processing the display chip modules is reduced, and efficient processing of the display chip modules is realized.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims (7)

1. A dual layer wafer plate, comprising: a first wafer and a second wafer;

the first wafer comprises a plurality of first chips which are arranged in a matrix manner;

the second wafer comprises a plurality of second chips which are arranged in a matrix;

the first chips are electrically connected with the second chips in a one-to-one correspondence manner to form a display chip module.

2. The bi-layer wafer plate of claim 1, wherein the first wafer is made of a silicon wafer.

3. The bi-layer wafer plate of claim 1, wherein the second wafer is made of a gallium nitride epitaxial wafer.

4. The double-layered wafer plate of claim 1 or 3, wherein the second chip is one of an LED chip, a small pitch LED chip, a mini LED chip, and a Micro-LED chip.

5. The double-layered wafer board according to claim 1 or 2, wherein the first chip is one of an LED driving chip, a small pitch LED driving chip, a mini LED driving chip, and a Micro-LED driving chip.

6. The double-layered wafer plate as claimed in claim 1, wherein alignment marks are disposed on the first wafer and the second wafer for aligning and bonding the first wafer and the second wafer according to the alignment marks.

7. The bi-layer wafer sheet of claim 6, wherein the alignment marks comprise: a first alignment mark and a second alignment mark;

the first alignment mark is arranged on the first wafer;

the second alignment mark is arranged on the second wafer;

the number of the first alignment marks and the number of the second alignment marks are at least two.

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