CN210467852U - High-voltage-resistant high-electron-mobility transistor device - Google Patents
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Abstract
The utility model relates to a semiconductor power device particularly, relates to a high electron mobility transistor device of high withstand voltage. The high-voltage-resistant high-electron-mobility transistor device comprises a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer and a substrate; the channel layer is located between the barrier layer and the substrate and comprises a P-type III-V family semiconductor layer, wherein the nucleation layer and the projection of the drain electrode on the substrate are overlapped in at least partial area, the drain electrode is in electrical contact with two-dimensional electron gas of the channel layer, the source electrode is in electrical contact with the P-type III-V family semiconductor layer, and the gate electrode is located on the barrier layer.
Description
Technical Field
The present invention relates to a semiconductor power device, and particularly, to a high withstand voltage High Electron Mobility Transistor (HEMT).
Background
Group III-V compound semiconductors include at least one group III element and at least one group V element, including but not limited to gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), and the like, and group III nitride semiconductors include nitrogen and at least one group III element, including but not limited to GaN, AlGaN, InN, AlN, InGaN, InAlGaN, and the like.
High Electron Mobility Transistors (HEMTs) utilize group III-V heterojunction structures, such as group III nitride heterojunctions, to generate a two-dimensional electron gas (2DEG) at the heterojunction interface formed by the group III nitride material, which allows for high current density with relatively low resistive losses and a gradual increase in withstand voltage to 600V, even 1200V. Conventional group III nitride high electron mobility transistors are typically depletion mode devices and, due to the advantages of high breakdown voltage, high current density, and low on-resistance, group III nitride high electron mobility transistors need to avoid device turn-off without gate voltage control to protect the circuit and load. It is therefore desirable to provide group III nitride high electron mobility transistors that are normally-off, or enhancement mode transistors.
Thus, there is a need to overcome the disadvantages and shortcomings of the prior art for fabricating high voltage high electron mobility transistors, enhancement mode III-V high electron mobility transistors.
In the related patent application, we have proposed a description of realizing a normally-off device and/or a higher withstand voltage capability by a structure such as a P-type buried layer, and a detailed description is given of the structure of the related device. In a specific implementation, however, the nucleation region is located at the source position with selective area epitaxy. This is mainly because the high electron mobility transistor is a symmetrical structure with respect to the source, having a gate electrode and a drain electrode from the source to both sides. Meanwhile, the distance from the source electrode to the gate electrode is usually much smaller than the distance from the gate electrode to the drain electrode, and the distance from the source to the gate for lateral epitaxy is much shorter than the distance from the drain to the gate, which is beneficial to realizing the manufacturing precision of complex structures at the source and the gate through epitaxy. At the same time, the source region is at a low voltage, and the nucleation region is of relatively poor crystal quality, so that the effect of the low voltage is minimal when the source is in a low quality region.
In contrast, if nucleation and lateral epitaxy occurs from a gate or other region, the laterally-epitaxial two-sided structure is substantially symmetric, which is detrimental to the formation of many asymmetric structures. And if the lateral extension is started from the gate electrode region, the distance between the gate source and the gate drain is large, which is not beneficial to utilizing the chip area.
However, nucleation and lateral epitaxy from the projected corresponding region of the drain region on the substrate may also be achieved. It is also advantageous to form special structures in the drain region to improve certain performance. While the crystal quality of the epitaxial layer can be optimized prior to forming the complex structures at the source and at the gate. Thus, the complex structure at the source and the grid can obtain better crystal quality and obtain good electrical characteristics. Whether nucleation is from the source or drain region, the desired stacked layout structure can be formed sequentially from source to gate to drain or drain to gate to source.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the rationale of application is through introducing P-type III-V clan semiconductor layer, adjusts high electron mobility transistor device electric field distribution and improves its withstand voltage ability and realize the enhancement device through doping modulation technique.
The utility model discloses the application provides a high electron mobility transistor basic structure is from the drain electrode corresponding region begin the epitaxial growth III-V clan semiconductor layer in district, through the modulation doping technique, forms the different semiconductor layer region of doping concentration to finally form high electron mobility transistor structure. The local high electric field of the channel layer is reduced, the electric field distribution is improved, and the performance and the reliability of the device are improved.
The utility model provides a high withstand voltage high electron mobility transistor contains device structures such as gate electrode, source electrode, drain electrode, barrier layer, channel layer, nucleation layer, basement; a channel layer is disposed between the barrier layer and the substrate, the channel layer comprising a P-type group iii-v semiconductor layer at least partially between the drain electrode and the gate electrode insufficient to substantially deplete two-dimensional electron gas in the channel except for the gate electrode stack, wherein the nucleation layer corresponds to a region of the drain electrode, the drain electrode is in electrical contact with the channel layer over the nucleation layer, and the source electrode is in electrical contact with the P-type group iii-v semiconductor layer.
On the other hand, the above-described device electrode structure may be configured as follows: the source electrode and the drain electrode are both in electrical contact with the two-dimensional electron gas, the gate electrode is located above the barrier layer, and the independent body electrode is in electrical contact with the P-type group III-V semiconductor layer near the source electrode.
On the other hand, a low-doped or unintentionally doped group iii-v semiconductor layer may also be interposed between the barrier layer and the P-type group iii-v semiconductor layer.
On the other hand, a SiNx passivation layer can be grown in situ on the barrier layer.
On the other hand, a gate dielectric layer may be formed on the barrier layer.
On the other hand, an insulating layer is arranged on the substrate, after the insulating layer is provided with an opening through the processes of masking, etching and the like, a forming nucleus layer is formed at the opening, and then an epitaxial layer structure containing a P-type III-V family semiconductor layer grows in a lateral epitaxial mode; or growing a nucleation layer on the substrate, forming an insulating layer on the nucleation layer, forming an opening in the insulating layer by masking, etching, etc. to expose the nucleation layer, and growing an epitaxial layer structure including a P-type III-V semiconductor layer by lateral epitaxy.
On the other hand, an epitaxial layer structure grows on the substrate in a lateral epitaxial mode, and the epitaxial layer structure is expanded outwards by taking the region where the drain electrode is located as the center, so that a symmetrical high-electron-mobility transistor structure taking the drain electrode region as the center is formed.
On the other hand, when the epitaxial layer structure grows in a lateral epitaxial mode on the substrate, a first doping region of a lightly doped III-V family semiconductor layer, a first doping region of a strong P-type III-V family semiconductor layer and a first doping region of a P-type III-V family semiconductor layer are formed on the nucleation layer in an epitaxial mode, partial regions in the height direction of the III-V family semiconductor layer are removed through a flattening or etching process, the first doping region of the lightly doped III-V family semiconductor layer, the first doping region of the strong P-type III-V family semiconductor layer and the modulation P-type III-V family semiconductor layer of the first doping region of the P-type III-V family semiconductor layer are exposed; and a drain electrode is formed above the first doped region of the lightly doped III-V family semiconductor layer, a gate stack structure is correspondingly formed above the first doped region of the strong P-type III-V family semiconductor layer, and a source electrode is formed above the first doped region of the P-type III-V family semiconductor layer.
On the other hand, when the epitaxial layer structure grows in a lateral epitaxial mode on the substrate, a first doping region of a lightly doped III-V family semiconductor layer is formed on the nucleation layer in an epitaxial mode, then a first doping region of a P-type III-V family semiconductor layer and a second doping region of the P-type III-V family semiconductor layer are formed in an epitaxial mode, partial regions of the III-V family semiconductor layer in the height direction are removed through a flattening or etching process, and the modulated P-type III-V family semiconductor layer of the first doping region of the lightly doped III-V family semiconductor layer, the first doping region of the P-type III-V family semiconductor layer and the second doping region of the P-type III-V family semiconductor layer are exposed; a drain electrode is formed above the first doped region of the lightly doped III-V family semiconductor layer, a grid laminated structure is formed at the part, close to the first doped region of the P-type III-V family semiconductor layer, of the second doped region of the P-type III-V family semiconductor layer, namely the first doped region of the P-type III-V family semiconductor layer is positioned between the drain electrode and the grid electrode, the doping concentration of the first doped region of the P-type III-V family semiconductor layer is adjustable, the electric field distribution close to the drain side edge below the grid electrode can be improved, and a source electrode and/or a body electrode is formed above the second doped region of the P-type III-V family semiconductor layer.
On the other hand, when the epitaxial layer structure grows on the substrate in a lateral epitaxial mode, a first doping region of a lightly doped III-V family semiconductor layer is formed on the nucleation layer in an epitaxial mode, then a first doping region of a P-type III-V family semiconductor layer, a first doping region of a strong P-type III-V family semiconductor layer and a second doping region of the P-type III-V family semiconductor layer are formed in an epitaxial mode, removing partial area on the III-V family semiconductor layer in the height direction by a planarization or etching process to expose the modulation P-type III-V family semiconductor layer of the lightly doped III-V family semiconductor layer first doping area, the P-type III-V family semiconductor layer first doping area, the strong P-type III-V family semiconductor layer first doping area and the P-type III-V family semiconductor layer second doping area; a drain electrode is formed above the first doped region of the lightly doped III-V family semiconductor layer, a grid laminated structure is correspondingly formed above the first doped region of the strong P-type III-V family semiconductor layer, the first doped region of the P-type III-V family semiconductor layer is positioned between the first doped region of the lightly doped III-V family semiconductor layer and the first doped region of the strong P-type III-V family semiconductor layer, the doping concentration of the first doped region of the P-type III-V family semiconductor layer is adjustable, the electric field distribution close to the drain side below a grid electrode can be improved, and a source electrode and/or a body electrode is formed above the second doped region of the P-type III-V family semiconductor layer.
On the other hand, a low doped or unintentionally doped group iii-v semiconductor layer may be inserted over the modulated P-type group iii-v semiconductor layer.
On the other hand, the barrier layer above the P-type group iii-v semiconductor layer may further cover the passivation layer.
The lightly doped group iii-v semiconductor layer first doped region, on the other hand, is lightly doped or undoped.
The utility model discloses a P-type III-V family semiconductor layer adopts and begins to carry out the epitaxial growth of side direction from the drain electrode correspondence region, and P-type doping concentration can be as required adjusts the carrier gas atmosphere proportion of doping in the growth process, adjusts electric field distribution through P-type doping, can obtain high-quality P-type doping and to the space adjustment of AlGaN/GaN heterojunction interface department two-dimensional electron gas 2 DEG; and the doping concentration of the semiconductor layer below the drain electrode, the gate electrode and the source electrode is modulated, and the potential of the P-type III-V group semiconductor layer is controlled and modulated by using the source electrode or the body electrode, so that the voltage endurance capability of the high electron mobility transistor can be improved, and functions such as normally-off operation and the like are realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments of the present invention will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from these drawings without inventive efforts.
Fig. 1 is a basic structure of a high withstand voltage high electron mobility transistor according to an embodiment of the present invention;
fig. 2-4 are diagrams illustrating exemplary processes for forming high electron mobility transistors according to embodiments of the present invention;
fig. 5 is a diagram illustrating another exemplary process for forming high electron mobility transistors according to an embodiment of the present invention;
fig. 6-13 are diagrams of several other complex hemts and formation processes provided in embodiments of the present invention.
Detailed Description
The technical solution of the present invention in the application embodiment will be described below with reference to the accompanying drawings in the application embodiment of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance. "Upper and lower" and the like indicate relative positional relationships and do not indicate that they are directly adjacent to each other.
The utility model discloses a basic idea of high withstand voltage high electron mobility transistor is from the regional epitaxial growth of beginning side direction of drain electrode correspondence, because the epitaxial higher crystal quality that can realize of district selection, this has certain advantage than current planar growth.
On the basis of the basic structure described above, by doping and modulating the doping concentration in the lateral epitaxy, the following structures and their combinations can be formed: forming a strong P-type area at the gate electrode stack and exhausting two-dimensional electron gas at the strong P-type area to realize normally-off enhancement of the device; in addition to forming a strong P-type region at the gate electrode stack, a P-type layer is formed near the source electrode that does not significantly deplete the two-dimensional electron gas between the source and gate electrodes, but may connect the strong P-type region at the gate electrode stack and to the electrodes. The electrode may be a source electrode or a separate bulk electrode. A P-type region is formed between the gate electrode and the drain electrode, and the P-type region does not significantly deplete the two-dimensional electron gas but improves the electric field distribution and reduces the maximum electric field intensity.
In the high electron mobility transistor of the present invention, the doping concentration of the strong doping is usually 5E18/cm3Above, the doping concentration of the light doping is generally 5E18/cm3The following. In high electron mobility transistors, strong doping or light doping is opposed, depending on the two-dimensional electron gas concentration at the channel layer/barrier layer interface. In general, the higher the intrinsic (meaning the absence of doping) two-dimensional electron gas concentration at the channel layer/barrier layer interface, the higher the doping concentration corresponding to a strong doping, and the higher the doping concentration of a light doping can be. Conversely, the lower the intrinsic two-dimensional electron gas concentration, the lower the doping concentration corresponding to a strong doping, and therefore a light doping with a relatively lower doping concentration.
Referring to fig. 1, fig. 1 is a basic structure of a high withstand voltage high electron mobility transistor according to an embodiment of the present invention. The basic structure is an insulating layer 102 and a nucleation layer 103 on a substrate 101, a channel layer 104 on the insulating layer 102 and the nucleation layer 103, the channel layer 104 may be a P-type semiconductor layer, more specifically, a P-type group iii-v semiconductor layer, a barrier layer 105 on the P-type group iii-v semiconductor layer, a two-dimensional electron gas 2DEG formed at an interface of a heterojunction of the barrier layer 105, the channel layer 104 and the barrier layer 105, a source electrode 107 and a drain electrode 106 connected with the two-dimensional electron gas and forming an ohmic contact, and a gate electrode 108 located on the barrier layer 105; wherein the nucleation layer 103 is overlapped with the projection of the drain electrode 106 on the substrate 101 at least in partial region, so as to form a high electron mobility transistor structure with the drain electrode extending outwards. The P-type III-V family semiconductor layer has low doping concentration, the two-dimensional electron gas at the interface of the barrier layer and the P-type III-V family semiconductor layer can not be seriously exhausted by the P-type III-V family semiconductor layer, and the two-dimensional electron gas with high concentration still exists at the heterojunction interface. The iii-v semiconductor layer is typically a nitride semiconductor layer and the P-type iii-v semiconductor layer is at least partially located below the two-dimensional electron gas region between the gate electrode and the drain electrode and between the gate electrode and the source electrode, except for the gate electrode stack region, where the P-type iii-v semiconductor layer depletes the channel 2DEG concentration less than 80% of the channel 2DEG concentration without the P-type iii-v semiconductor layer, i.e., at least 20% of the two-dimensional electron gas is retained. The P-type iii-v semiconductor layer in the region between the gate and drain electrodes is also partially depleted under the influence of the electric field, exposing the negative background charge. The negative charges can effectively offset the influence of positive charges at the channel and positive charges at the drain, adjust the distribution of the electric field, reduce the intensity of the peak value of the local electric field and improve the voltage-resisting capability of the device.
The high voltage high electron mobility transistor provided in the embodiment of fig. 1 may be formed through the steps shown in fig. 2-4, etc. As shown in fig. 2, an insulating layer 202 is formed on a substrate 201, an opening region is formed on the insulating layer through processes such as masking and etching, a nucleation layer 203 is epitaxially grown on the opening region of the insulating layer, and a P-type iii-v semiconductor layer is grown in a lateral epitaxial manner; or as shown in fig. 3, a nucleation layer 302 is epitaxially grown on a substrate 301, then an insulating layer 303 is formed, an opening region 304 is formed on the insulating layer through masking, etching and other processes to expose the nucleation layer 302, and then a P-type iii-v semiconductor layer is epitaxially grown on the nucleation layer at the opening region of the insulating layer by means of lateral epitaxy.
Under certain substrate (e.g., Al2O3 substrate) and process conditions, the nucleation layer may be selectively grown on the exposed substrate without growing on the insulating layer. However, when a silicon substrate is used, AlN is generally required to be used as a nucleation layer, but the growth selectivity is poor when AlN is used as the nucleation layer. In this case, AlN on the insulating layer may be etched/removed after the nucleation layer is grown, but deposition of AlN on the insulating layer is rare under certain growth conditions, and the nucleation growth substrate for the subsequent nitride epitaxial layer cannot be formed on the insulating layer. The growth of the P-type group iii-v semiconductor layer is not significantly followed in other regions than the nucleation region, and the subsequent growth can be performed directly without removing AlN on the insulating layer.
Since AlN on the insulating layer is polycrystalline or amorphous, under appropriate process conditions, nucleation growth may occur only on the single-crystal AlN in the opening region, and not on the polycrystalline AlN on the insulating layer. At this time, the AlN layer of the polycrystalline structure largely functions as an insulator.
As shown in fig. 4, an insulating layer 402 is formed on a substrate 401, an opening region is formed on the insulating layer through a mask, etching, and other processes, a nucleation layer 403 is epitaxially grown in the opening region of the insulating layer, a buffer layer 404 is formed, and then a P-type iii-v semiconductor layer 405 with high crystal quality is formed as a channel layer.
As shown in fig. 5, an insulating layer 502 is formed on a substrate 501, an opening region is formed on the insulating layer through processes such as masking and etching, a nucleation layer 503 is epitaxially grown at the opening region of the insulating layer, a P-type iii-v semiconductor layer 504 is grown on the nucleation layer through lateral epitaxy, a barrier layer 505 is formed, and a SiNx passivation layer (not shown) is deposited in situ in the same deposition equipment to obtain the barrier layer/SiNx layer with low interface defect state density. The in-situ SiNx layer may be subjected to a mask etching process, and then only the SiNx layer below the gate electrode 508 is reserved as a gate dielectric layer 509 for use, as shown in fig. 5, that is, a channel layer, a barrier layer, and the in-situ SiNx layer are sequentially grown in the same growth apparatus, so that the apparatus utilization rate is improved, the growth quality is improved, the drain electrode 506 and the source electrode 507 are formed in the barrier layer, and the drain electrode 506 and the source electrode 507 are in ohmic contact with two-dimensional electron gas. The resulting high electron mobility transistor structure may be formed as shown in fig. 5.
Fig. 1 and 5 and the application of the present invention to the basic device structure of the P-type iii-v semiconductor layer formed by lateral epitaxial modulation of doping concentration in the corresponding region of the drain electrode in the high electron mobility transistor structure shown in the following embodiments may further include a low doped or undoped iii-v semiconductor layer such as a P-GaN layer interposed between the P-type iii-v semiconductor layer and the barrier layer, a cap layer, a field plate, a back barrier layer, an additional electrode for controlling a channel electric field, and the like; the presence of a gate dielectric layer and/or a p-GaN layer, etc. under the gate electrode, either of the above-described structures or other structures disclosed in the prior art, is not excluded from embodiments of the present invention.
As shown in fig. 6-9, an insulating layer 602-.
As shown in fig. 7, a first doped region (704-1) of a lightly doped iii-v semiconductor layer is first formed on a nucleation layer by lateral epitaxy using a doping modulation technique during lateral epitaxial growth of a P-type iii-v semiconductor layer; forming a P-type layer-1 (704-2), wherein the P-type layer-1 (704-2) is a strong P-type III-V semiconductor layer, which is beneficial to exhausting two-dimensional electron gas in a corresponding channel layer and realizing a normally-off device; epitaxially growing a second doped region (704-3) of the III-V semiconductor layer laterally; then removing partial area on the III-V family semiconductor layer in the height direction by a planarization or etching process to expose the modulation P-type III-V family semiconductor layer of the first doping area (704-1) of the lightly doped III-V family semiconductor layer, the strong P-type III-V family semiconductor layer (704-2) and the second doping area (704-3) of the III-V family semiconductor layer; then, a laminated structure of a channel layer 705, a barrier layer 706 and an in-situ SiNx layer 707 is formed; forming a source electrode 709, a drain electrode 708 and a gate electrode 710, wherein the gate electrode 710 corresponds to the strong P-type group iii-v semiconductor layer region, the source electrode 709 is substantially located above the second doped region (704-3) of the group iii-v semiconductor layer and in ohmic contact with the two-dimensional electron gas, and the drain electrode is substantially located above the first doped region (704-1) of the lightly doped group iii-v semiconductor layer, and finally forming the high-voltage-resistance normally-off high-electron-mobility transistor structure as shown in fig. 7.
The strong P-type III-V semiconductor layer arranged below the gate electrode can ensure that more than 95% of two-dimensional electron gas below the gate electrode stack can be exhausted under the gate voltage of 0 or ensure that the concentration of the two-dimensional electron gas below the gate electrode stack under the gate voltage of 0 is less than 5E11/cm2。
In addition, in order to enhance the control of the source electrode to the second doping region of the III-V family semiconductor layer, the potential of the strong P-type III-V family semiconductor layer is further controlled through the layer, so that the stable threshold voltage of the high electron mobility transistor is obtained. As shown in fig. 8, when the second doping region (804-3) of the iii-v semiconductor layer is epitaxially grown laterally, P-type doping growth is performed to form a P-type iii-v semiconductor layer, and finally a modulated P-type iii-v semiconductor layer 804 structure layer of the lightly doped iii-v semiconductor layer first doping region (804-1), the strong P-type iii-v semiconductor layer (804-2), and the P-type iii-v semiconductor layer (804-3) is formed, and the drain electrode 808 is in ohmic contact with two-dimensional electron gas above the lightly doped iii-v semiconductor layer first doping region (804-1); the P-type III-V family semiconductor layer (804-3) and the barrier layer 806 are exposed in a step-type mode through the processes of masking, etching and the like, and then a source electrode 809 is formed through deposition, so that part of the region of the source electrode 809 is in contact with two-dimensional electron gas, part of the region of the source electrode 809 passes through the channel layer 805 to be in direct contact with the P-type III-V family semiconductor layer 804-3, and the potential of the strong P-type III-V family semiconductor layer 804-2 can be better controlled through good electric contact of the source electrode and the P-type III-V family semiconductor layer, so that stable threshold voltage of the high electron mobility transistor can be obtained. Alternatively, a portion of the source electrode 809 that is in contact with the P-type group iii-v semiconductor layer 804-3 is physically connected to a portion of the source electrode 809 that is in contact with the two-dimensional electron gas (i.e., collectively constitutes the source electrode); or the source electrode 809 is in contact with the two-dimensional electron gas, and the metal material in contact with the P-type III-V group semiconductor layer 804-3 is electrically connected with the source electrode 809 so as to be integrally controlled with the source electrode potential.
A gate dielectric layer 807, which may be in-situ SiNx or other dielectric such as SiO2, high-k, etc., may also be disposed below the gate electrode 810 to completely cover the barrier layer 806.
The difference from the embodiment shown in fig. 8 is that in the embodiment shown in fig. 9, the electrode in contact with the P-type iii-v group semiconductor layer 904-3 is an independent body electrode 911 not connected to the source electrode 909, the body electrode is electrically connected to the P-type iii-v group semiconductor layer 904-3 through the passivation layer, the barrier layer and the channel layer, and the source electrode 909 is located on the channel layer, which facilitates independent control of the source electrode potential and the operating potential of the P-type iii-v group semiconductor layer 904-3, and particularly when the source potential is fixed at a 0 potential point, the potential of the body electrode can be independently controlled according to the operating voltage or stable operating voltage required for channel shutdown, which facilitates stable and efficient operation of the enhancement mode device.
As shown in fig. 10, an insulating layer 1002 is formed on a substrate 1001, an opening region is formed on the insulating layer through processes such as masking and etching, a nucleation layer 1003 is epitaxially grown at the opening region of the insulating layer, a P-type iii-v semiconductor layer 1004 is grown on the nucleation layer through lateral epitaxy, and a first doped region (1004-1) of a lightly doped iii-v semiconductor layer is first formed on the nucleation layer through lateral epitaxy by using a doping modulation technique when the P-type iii-v semiconductor layer is laterally epitaxially grown; forming a first doped region (1004-2) of the P-type III-V semiconductor layer, wherein the epitaxial growth time of the first doped region (1004-2) of the P-type III-V semiconductor layer is shorter than that of the first doped region (604-2) of the P-type III-V semiconductor layer shown in FIG. 6, and the first doped region of the P-type III-V semiconductor layer formed as shown in FIG. 10 is narrower; epitaxially growing a second doped region (1004-3) of the P-type III-V semiconductor layer laterally; then removing partial area on the III-V family semiconductor layer in the height direction by a planarization or etching process to expose the modulation P-type III-V family semiconductor layer of the lightly doped III-V family semiconductor layer first doping area (1004-1), the P-type III-V family semiconductor layer first doping area (1004-2) and the P-type III-V family semiconductor layer second doping area (1004-3); then, as shown in fig. 11, a stacked structure of a channel layer 1105, a barrier layer 1106, and an in-situ SiNx layer 1107 is formed; a source electrode 1109, a drain electrode 1108 and a gate electrode 1110 are formed, wherein the gate electrode 1110 is offset from the P-type group iii-v semiconductor layer first doped region (1104-2) in the lateral direction, the drain electrode 1108 is located substantially on the channel layer 1105 above the lightly doped group iii-v semiconductor layer first doped region (1104-1), the source electrode 1109 is in contact with the lightly doped group iii-v semiconductor layer first doped region (the source electrode is formed in the same manner as in the embodiment shown in fig. 8), and finally the high withstand voltage high electron mobility transistor structure as shown in fig. 11 is formed.
In the high withstand voltage high electron mobility transistor shown in fig. 11, the drain electrode corresponds to the nucleation region, and the first doping region of the P-type iii-v semiconductor layer is located in the region between the gate electrode and the drain electrode, so that high electric field distribution near the side region of the drain electrode below the gate electrode can be improved, and device failure caused by excessive local electric field strength can be avoided. The channel layer, in-situ SiN passivation layer, and gate insulator layer, etc. are optional and not required.
As shown in fig. 12, the electrode in contact with the second doped region of the P-type iii-v semiconductor layer is an independent body electrode, so that the source potential and the operating potential of the P-type iii-v semiconductor layer can be independently controlled, especially when the source potential is fixed at a 0 potential point, according to the operating voltage or the stable operating voltage required for turning off the channel.
The difference from the embodiment shown in fig. 11 is that in the embodiment shown in fig. 12, the electrode in contact with the P-type group iii-v semiconductor layer 1204-3 is an independent body electrode 1211 which is not connected to the source electrode 1209, the body electrode is electrically connected to the P-type group iii-v semiconductor layer 1204-3 through the passivation layer, the barrier layer and the channel layer, and the source electrode 1209 is located on the channel layer, so that the potential of the source electrode and the working potential of the P-type group iii-v semiconductor layer 1204-3 can be independently controlled, especially when the source potential is fixed at a 0-potential point, the potential of the body electrode can be independently controlled according to the working voltage or the stable working voltage required for turning off the channel, and the enhancement mode high electron mobility transistor can stably and efficiently operate.
While the leakage electric field strength under the gate electrode is reduced to enhance the withstand voltage capability of the hemt, the hemts shown in fig. 11-12 can be combined with the enhancement type hemt structures shown in fig. 7-9 by doping modulation technology to form the enhancement type hemt with higher withstand voltage as shown in fig. 13. As shown in fig. 13, in the hemt, an insulating layer 1302 is formed on a substrate 1301, an opening region is formed on the insulating layer through processes of masking, etching and the like, a nucleation layer 1303 is epitaxially grown at the opening region of the insulating layer, and a P-type iii-v semiconductor layer 1304 is grown on the nucleation layer by lateral epitaxy, and in the lateral epitaxial growth process of the P-type iii-v semiconductor layer, a lightly doped iii-v semiconductor layer first doped region (1304-1), a P-type iii-v semiconductor layer first doped region (1304-2), a strong P-type iii-v semiconductor layer (1304-3), and a P-type iii-v semiconductor layer second doped region (1304-4) are sequentially grown by using a doping modulation technique, a strong P-type iii-v semiconductor layer (1304-3) is located at the gate electrode stack and a normally-off device is obtained by depleting a portion or all of the two-dimensional electron gas at the gate electrode stack.
Exposing the P-type III-V group semiconductor layer (1304-4) and the barrier layer 1306 in a step-type mode through the processes of masking, etching and the like, depositing to form a source electrode 1309, enabling a partial area of the source electrode 1309 to be in contact with two-dimensional electron gas, enabling a partial area of the source electrode 1309 to be in direct contact with the P-type III-V group semiconductor layer 804-3 through the channel layer 1305, enabling the source electrode 1309 to be in good electrical contact with the P-type III-V group semiconductor layer second doping area (1304-4), and controlling the potential of the strong P-type III-V group semiconductor layer (1304-3) through the P-type III-V group semiconductor layer second doping area (1304-4) to obtain stable threshold voltage. The first doped region (1304-2) of the P-type iii-v semiconductor layer is located in the region between the gate electrode 1310 and the drain electrode 1308, which can improve the high electric field distribution near the drain electrode side region below the gate electrode, and avoid the device failure caused by the local overlarge electric field strength. The channel layer, in-situ SiN passivation layer, and gate insulator layer, etc. are optional and not required.
In addition, in another embodiment having a different potential control manner from the embodiment shown in fig. 13, the electrode in contact with the second doped region of the P-type iii-v group semiconductor layer is an independent body electrode (the connection manner of the source electrode and the body electrode is the same as the connection manner shown in fig. 12), so as to facilitate the independent control of the source potential and the working potential of the second doped region of the P-type iii-v group semiconductor layer, and facilitate the stable and efficient working of the enhancement type device under high-voltage conditions.
The above description is only for the purpose of illustrating embodiments of the present invention and is not intended to limit the scope of the present invention, which will be apparent to those skilled in the art from this disclosure. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A high-voltage-resistant high-electron-mobility transistor device comprises a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer and a substrate; a channel layer including a P-type group III-V semiconductor layer is positioned between the barrier layer and the substrate, wherein the nucleation layer coincides with at least a partial region of a projection of the drain electrode on the substrate, the drain electrode is in electrical contact with the two-dimensional electron gas of the channel layer, the source electrode is in electrical contact with the P-type group III-V semiconductor layer, and the gate electrode is positioned on the barrier layer.
2. A high-voltage-resistant high-electron-mobility transistor device comprises a gate electrode, a source electrode, a drain electrode, a barrier layer, a channel layer, a nucleation layer and a substrate; wherein the nucleation layer and the drain electrode are at least partially coincident in projection onto the substrate, a channel layer comprising a P-type group iii-v semiconductor layer is located between the barrier layer and the substrate insufficient to substantially deplete the two-dimensional electron gas in the channel except for the gate stack, and both the source electrode and the drain electrode are in electrical contact with the two-dimensional electron gas, the gate electrode is located above the barrier layer, and a separate body electrode is in electrical contact with the P-type group iii-v semiconductor layer near the source electrode.
3. The hemt device of claim 1 or 2, wherein a further layer of lowly doped or unintentionally doped group iii-v semiconductor is disposed between the barrier layer and the P-type group iii-v semiconductor layer.
4. The hemt device of claim 1 or 2, wherein a SiNx passivation layer is grown in situ on the barrier layer and a gate dielectric layer is disposed under the gate electrode.
5. The hemt device of claim 1 or 2, wherein the P-type iii-v semiconductor layer comprises modulation regions of different doping concentrations, and a lightly doped iii-v semiconductor layer first doping region, a strongly P-type iii-v semiconductor layer first doping region, and a P-type iii-v semiconductor layer first doping region are sequentially disposed outward from the nucleation layer region as a center, wherein a drain electrode is formed above the lightly doped iii-v semiconductor layer first doping region, a gate stack structure is correspondingly formed above the strongly P-type iii-v semiconductor layer first doping region, and a source electrode is formed above the P-type iii-v semiconductor layer first doping region.
6. The hemt device of claim 5, wherein said first doped region of said strong P-type group iii-v semiconductor layer under said gate electrode is such that more than 95% of the two-dimensional electron gas under said gate electrode stack is depleted at 0 gate voltage or such that the concentration of said two-dimensional electron gas under said gate electrode stack is less than 5E11/cm at 0 gate voltage2。
7. The hemt device of claim 5, wherein said first doped region of said lightly doped group iii-v semiconductor layer has a doping concentration of less than 5E17/cm3。
8. The hemt device of claim 1 or 2, wherein the P-type iii-v semiconductor layer comprises modulation regions of different doping concentrations, a lightly doped iii-v semiconductor layer first doping region, a P-type iii-v semiconductor layer second doping region are sequentially disposed outward from the nucleation layer region as a center, a drain electrode is formed above the lightly doped iii-v semiconductor layer first doping region, a gate stack structure is formed at a portion of the P-type iii-v semiconductor layer second doping region close to the P-type iii-v semiconductor layer first doping region, that is, the P-type iii-v semiconductor layer first doping region is located between the drain electrode and the gate electrode, the doping concentration of the first doping region of the P-type III-V family semiconductor layer is adjustable, the electric field distribution close to the drain side edge below the gate electrode can be improved, and a source electrode is formed above the second doping region of the P-type III-V family semiconductor layer.
9. The hemt device of claim 1 or 2, wherein the P-type iii-v semiconductor layer comprises modulation regions of different doping concentrations, and a lightly doped iii-v semiconductor layer first doping region, a P-type iii-v semiconductor layer first doping region, a strongly P-type iii-v semiconductor layer first doping region, and a P-type iii-v semiconductor layer second doping region are sequentially disposed outward from the nucleation layer region; a drain electrode is arranged above the first doping region of the lightly doped III-V family semiconductor layer, a grid laminated structure is correspondingly formed above the first doping region of the strong P-type III-V family semiconductor layer, the first doping region of the P-type III-V family semiconductor layer is positioned between the first doping region of the lightly doped III-V family semiconductor layer and the first doping region of the strong P-type III-V family semiconductor layer, the doping concentration of the first doping region of the P-type III-V family semiconductor layer is adjustable, the electric field distribution close to the drain side below a grid electrode can be improved, and a source electrode is formed above the second doping region of the P-type III-V family semiconductor layer.
10. The hemt device of claim 1, wherein when the source electrode is in electrical contact with the P-type group iii-v semiconductor layer, a portion of the region of the source electrode is in contact with the two-dimensional electron gas and a portion of the region of the source electrode is in direct contact with the P-type group iii-v semiconductor layer through the channel layer.
11. The hemt device of claim 1, wherein the metal material in contact with the P-type group iii-v semiconductor layer is electrically connected to the source electrode when the source electrode is in electrical contact with the two-dimensional electron gas, thereby facilitating integral control of the potential of the source electrode.
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| CN113838935A (en) * | 2020-06-24 | 2021-12-24 | 广东致能科技有限公司 | Semiconductor device, manufacturing method and application thereof |
| TWI787879B (en) * | 2020-06-24 | 2022-12-21 | 大陸商廣東致能科技有限公司 | Semiconductor device, manufacturing method and application thereof |
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| CN113838935A (en) * | 2020-06-24 | 2021-12-24 | 广东致能科技有限公司 | Semiconductor device, manufacturing method and application thereof |
| WO2021258732A1 (en) * | 2020-06-24 | 2021-12-30 | 广东致能科技有限公司 | Normally-off device and manufacturing method therefor |
| TWI787879B (en) * | 2020-06-24 | 2022-12-21 | 大陸商廣東致能科技有限公司 | Semiconductor device, manufacturing method and application thereof |
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