CN116314311A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN116314311A CN116314311A CN202111569929.2A CN202111569929A CN116314311A CN 116314311 A CN116314311 A CN 116314311A CN 202111569929 A CN202111569929 A CN 202111569929A CN 116314311 A CN116314311 A CN 116314311A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 150000004767 nitrides Chemical class 0.000 claims abstract description 152
- 230000004888 barrier function Effects 0.000 claims abstract description 139
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 34
- 230000006911 nucleation Effects 0.000 claims description 24
- 238000010899 nucleation Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 abstract description 9
- 238000003475 lamination Methods 0.000 abstract description 6
- 238000002425 crystallisation Methods 0.000 abstract description 3
- 230000008025 crystallization Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 2
- 229910002601 GaN Inorganic materials 0.000 description 36
- 230000005684 electric field Effects 0.000 description 21
- 239000013078 crystal Substances 0.000 description 15
- 229910002704 AlGaN Inorganic materials 0.000 description 14
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 12
- 230000037230 mobility Effects 0.000 description 11
- 238000000407 epitaxy Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 6
- 238000003780 insertion Methods 0.000 description 6
- 230000037431 insertion Effects 0.000 description 6
- 229910052742 iron Inorganic materials 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- -1 GaAs Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The application provides a semiconductor device and a preparation method thereof. The high electron mobility transistor includes a gate structure with a special design. The gate structure includes a high-resistance nitride epitaxial layer and a p-cap layer which are stacked, and a first gate insulating layer disposed on a surface of the first barrier layer away from the channel layer. The projection length of the p-cap layer in the lamination direction of the lamination structure is larger than that of the high-resistance nitride epitaxial layer in the lamination structure. The thickness of the first gate insulating layer is smaller than that of the high-resistance nitride epitaxial layer. The arrangement of the high-resistance nitride epitaxial layer can improve the crystallization quality of the p-cap layer. The provision of the high-resistance nitride epitaxial layer can prevent Mg diffusion to degrade the channel. The arrangement of the high-resistance nitride epitaxial layer can effectively reduce the leakage current of the gate electrode. According to the method, the grid leakage is reduced by arranging the special grid structure, so that the device has a larger grid voltage working range, and the reliability of the device is greatly improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device and a preparation method thereof.
Background
Group III nitride semiconductors are an important new semiconductor material, mainly comprising AlN, gaN, inN and compounds of these materials such as AlGaN, inGaN, alInGaN. Because of the advantages of direct band gap, wide band gap, high breakdown field strength and the like, the III-nitride semiconductor represented by GaN has wide application prospect in the fields of light emitting devices, power electronics, radio frequency devices and the like. For example, gaN-based LED devices have become the main electrical devices for emitting green and blue light, and have found great application in the fields of lighting, backlight, display screens, and the like.
Another important device type for group III nitride semiconductors is the High Electron Mobility Transistor (HEMT), which has great promise in the field of power semiconductors. Due to the existence of spontaneous polarization and piezoelectric polarization effects, gaN on the (0001) plane has strong polarized positive charges at the interface with AlGaN. The presence of these polarized positive charges attracts and results in the generation of two-dimensional electron gas at the interface. These two-dimensional electron gases have very high carrier concentrations and very high carrier mobilities, which are the core components in the fabrication of High Electron Mobility Transistors (HEMTs).
When the HEMT device with the traditional AlGaN/GaN heterojunction structure is applied to a power switch, the key problem is the normally-on characteristic of the HEMT device. That is, when the grid is not applied with any bias voltage, the device is in a conducting state, and the device can be turned off only when the grid is applied with negative bias voltage, which means that the device is out of control under the condition that the grid is powered off, so that electric leakage or short circuit is caused, and serious potential safety hazards exist in practical application.
Therefore, chang Guantai of the implementation device is one of the core problems of the study of GaN-based HEMT power devices. I.e., devices that are rendered conductive when the gate is biased, are often referred to as normally-off devices or enhancement-mode devices. There are various methods for implementing the normally-off GaN-based HEMT device, such as a recessed gate structure, a MIS structure, a cascade structure, and a p-type gate structure, where the p-type gate structure is the most favored solution for the normally-off device. One of the major problems with p-type gate structures, however, is: the P-GaN is in direct contact with the AlGaN barrier layer, resulting in serious gate leakage problems. Also, due to the gate leakage problem, the device has a smaller gate voltage operating range, and the device is likely to be damaged beyond a certain voltage, so that serious reliability problems are caused.
Therefore, the inventor provides a solution to the technical problem that the normally-off device has serious gate leakage.
Disclosure of Invention
In view of this, the present application provides a semiconductor device with high threshold voltage and a method for manufacturing the same, which can alleviate gate leakage, expand the gate voltage operating range, and improve the reliability of the device.
The present application provides a high electron mobility transistor comprising:
A stacked structure including at least a channel layer and a first barrier layer;
the grid structure comprises a high-resistance nitride epitaxial layer and a p-cap layer which are arranged in a stacked mode, wherein the projection length of the p-cap layer in the stacking direction of the stacked structure is larger than that of the high-resistance nitride epitaxial layer in the stacked structure; and
the gate structure further comprises a first gate insulating layer which is arranged on the surface of the first barrier layer far away from the channel layer, and the thickness of the first gate insulating layer is smaller than that of the high-resistance nitride epitaxial layer.
In one embodiment, the gate structure has: a first gate stack and a second gate stack;
the first gate stack comprises a gate stack formed by the p-cap layer, the high-resistance nitride epitaxial layer, the first barrier layer and the channel layer from top to bottom; the p-cap layer and the first barrier layer are separated by the high-resistance nitride epitaxial layer in the first gate stack, the p-cap layer cannot deplete two-dimensional electron gas at the interface of the first barrier layer and the channel layer, and the first gate stack has two-dimensional electron gas when the gate voltage is 0V;
The second gate stack comprises a gate stack formed by the p-cap layer, the first gate insulating layer, the first barrier layer and the channel layer from top to bottom; the p-cap layer in the second gate stack can deplete the two-dimensional electron gas at the interface of the first barrier layer and the channel layer, and the second gate stack depletes the two-dimensional electron gas when the gate voltage is 0V.
In one embodiment, the p-cap layer comprises: a first cap layer with high doping concentration and a second cap layer with low doping concentration;
the second cap layer wraps the first cap layer;
wherein the first cap layer is in contact with the high-resistance nitride epitaxial layer;
the second cap layer is remote from the high resistance nitride epitaxial layer.
In one embodiment, the high electron mobility transistor further comprises:
a second barrier layer comprising two portions;
a first portion of the second barrier layer is formed between the first barrier layer and the high-resistance nitride epitaxial layer;
the second barrier layer of the second part is formed on the surface of the first gate insulating layer far away from the first barrier layer; and, a part of the surface of the p-cap layer covers the second barrier layer.
In one embodiment, the high electron mobility transistor further comprises:
the second gate insulating layer is arranged on the surface, far away from the first barrier layer, of the first gate insulating layer, the thickness of the second gate insulating layer is smaller than that of the p-cap layer, and part of the p-cap layer covers the second gate insulating layer.
In one embodiment, the gate structure further has: a third gate stack;
the third gate stack comprises a gate stack formed by the p-cap layer, the second gate insulating layer, the first barrier layer and the channel layer from top to bottom; the p-cap layer in the third gate stack cannot deplete the two-dimensional electron gas at the interface of the first barrier layer and the channel layer, and the third gate stack has the two-dimensional electron gas when the gate voltage is 0V.
In one embodiment, the high resistance nitride epitaxial layer is an unintentionally doped nitride, a carbon doped nitride, or an iron doped nitride.
In one embodiment, the high resistance nitride epitaxial layer has a thickness greater than 20nm.
The application also provides a preparation method of the high electron mobility transistor, which comprises the following steps:
s10, sequentially preparing a laminated structure at least comprising a channel layer and a first barrier layer on a first surface of a substrate;
S20, forming a first gate insulating layer on the first barrier layer, and etching the first gate insulating layer to form a first groove exposing the first barrier layer, wherein the first barrier layer is made of a nitride semiconductor;
s30, epitaxially growing a high-resistance nitride epitaxial layer to a selected region of the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer is larger than that of the first gate insulating layer;
and S40, using the high-resistance nitride epitaxial layer as a nucleation layer, and laterally epitaxially growing a p-cap layer, wherein the projection length of the p-cap layer on the laminated structure is larger than that of the high-resistance nitride epitaxial layer on the laminated structure.
In one embodiment, the p-cap layer comprises: a first cap layer with high doping concentration and a second cap layer with low doping concentration, wherein the step of further depositing a p-cap layer in S40 comprises:
s41, depositing a first cap layer with high doping concentration by taking the high-resistance nitride epitaxial layer as a nucleation layer;
s42, depositing the second cap layer outside the first cap layer, wherein the second cap layer wraps the first cap layer.
In one embodiment, the high electron mobility transistor further includes a second barrier layer, and the S30 includes:
S31, depositing the second barrier layer into the first groove and the first gate insulating layer, wherein the material of the second barrier layer is nitride semiconductor;
and S32, depositing the high-resistance nitride epitaxial layer into the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer is larger than that of the first gate insulating layer.
The application also provides a preparation method of the high electron mobility transistor, which comprises the following steps:
s101, sequentially preparing a laminated structure at least comprising a channel layer and a first barrier layer on a first surface of a substrate;
s102, forming a first gate insulating layer and a second gate insulating layer on the first barrier layer, and performing first etching on the first gate insulating layer and the second gate insulating layer to form a first groove exposing the first barrier layer, wherein the first barrier layer is made of a nitride semiconductor;
s103, performing second etching on the second gate insulating layer to form a second groove exposing the first gate insulating layer;
s104, epitaxially growing a high-resistance nitride epitaxial layer to a selected region of the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer is larger than that of the first gate insulating layer;
S105, using the high-resistance nitride epitaxial layer as a nucleation layer, laterally epitaxially growing a p-cap layer into the second groove, and covering the second gate insulating layer by a part of the p-cap layer, wherein the projection length of the p-cap layer on the laminated structure is larger than that of the high-resistance nitride epitaxial layer on the laminated structure.
The embodiment of the invention has the beneficial effects that: the high electron mobility transistor includes a gate structure with a special design. The gate structure comprises a high-resistance nitride epitaxial layer and a p-cap layer which are stacked, and a first gate insulating layer which is arranged on the surface of the first barrier layer, which is far away from the channel layer. The projection length of the p-cap layer in the lamination direction of the lamination structure is larger than that of the high-resistance nitride epitaxial layer in the lamination structure. The thickness of the first gate insulating layer is smaller than that of the high-resistance nitride epitaxial layer. The arrangement of the high-resistance nitride epitaxial layer in the gate structure can improve the crystallization quality of the p-cap layer. The provision of the high-resistance nitride epitaxial layer can prevent Mg diffusion to degrade the channel. The arrangement of the high-resistance nitride epitaxial layer can effectively reduce the leakage current of the gate electrode. According to the method, the grid leakage is reduced by arranging the special grid structure, so that the device has a larger grid voltage working range, and the reliability of the device is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present application;
fig. 2 is a schematic structural view of a semiconductor device according to a first embodiment of the present invention, which is different from the structure of the high-resistance nitride epitaxial layer in fig. 1;
fig. 3 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present application;
fig. 5 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present application;
fig. 6 is a schematic structural diagram of a semiconductor device according to a fifth embodiment of the present application;
fig. 7 is a schematic flowchart of a step of a semiconductor device according to a first embodiment of the present application;
fig. 8 is a schematic process flow diagram of a semiconductor device according to a first embodiment of the present application;
Fig. 9 is a schematic flowchart of a semiconductor device according to a fourth embodiment of the present application;
fig. 10 is a schematic view of a part of a process flow of a semiconductor device according to a fourth embodiment of the present application;
fig. 11 is a schematic process flow diagram of the remaining part of the semiconductor device according to the fourth embodiment of the present application;
fig. 12 is a graph comparing performance of a conventional p-type gate structure semiconductor device with that provided in the embodiments of the present application.
Reference numerals illustrate:
the semiconductor device 10:
laminated structure 100: a substrate 101, an insertion layer 102, a buffer layer 103, a channel layer 104, a first barrier layer 105, and a second barrier layer 106;
gate structure 200: a high-resistance nitride epitaxial layer 201, a p-cap layer 202, a first gate insulating layer 203, a second gate insulating layer 204, and a gate electrode 205; first gate stack 210, second gate stack 220, and third gate stack 230; fourth gate stack 240; first cap layer 212, second cap layer 222;
a source electrode 300; drain electrode 400.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
The inventor provides a solution to the technical problem that the normally-off device has serious gate leakage.
The inventors have tried to first form SiO on AlGaN barrier layer 2 Insulating layers such as SiN and the like, and then p-GaN is directly grown on the insulating layers, but the crystal quality and the electrical property of the p-GaN are poor. This is mainly due to SiO 2 Insulating layers such as SiN and the like are amorphous materials, and it is difficult to grow high-quality p-GaN thereon. It is difficult to form p-GaN of crystal quality in the conventional art.
Referring to fig. 1, in a first embodiment of the present application, the inventors provide a semiconductor device 10 having a high threshold voltage. The semiconductor device 10 may be provided as a high electron mobility transistor. The p-cap layer in the semiconductor device 10 has a higher crystal quality.
The semiconductor device 10 includes: a stacked structure 100 and a gate structure 200.
The laminated structure 100 includes at least a channel layer 104 and a first barrier layer 105. In one embodiment, the stacked structure 100 may include a substrate 101, an insertion layer 102, a buffer layer 103, a channel layer 104, and a first barrier layer 105 stacked in this order from bottom to top. The substrate 101 may be a silicon substrate. In one embodiment, the stacked structure 100 may include a substrate 101, a channel layer 104, and a first barrier layer 105 stacked in this order from bottom to top. The substrate 101 may be a sapphire substrate, a GaN substrate, or a SiC substrate. After the semiconductor device is fabricated, the substrate 101 may be stripped.
The buffer layer 103 may be one or more layers, and the buffer layer 103 may be a GaN buffer layer, an AlGaN buffer layer, or a carbon-doped GaN buffer layer. In one embodiment, the buffer layer 103 may have one or more layers, such as a multi-layer AlGaN, in which the concentration of Al gradually changes.
In addition, the laminated structure 100 may further include: a pad layer for improving channel quality is provided between the channel layer 104 and the first barrier layer 105. The laminated structure 100 may further include: a cap layer of gallium nitride of about 2nm is provided on the first barrier layer 105 to ensure the quality of the barrier layer 105. In addition, the laminate structure 100 may include other structural layers for improving film properties.
The gate structure 200 includes a high-resistance nitride epitaxial layer 201 and a p-cap layer 202 that are stacked, wherein a projection length of the p-cap layer 202 in a stacking direction of the stacked structure 100 is greater than a projection length of the high-resistance nitride epitaxial layer 201 in the stacking direction of the stacked structure 100.
The gate structure 200 further includes a first gate insulating layer 203. The first gate insulating layer 203 is disposed on a surface of the first barrier layer 105 away from the channel layer 104, and a thickness of the first gate insulating layer 203 is smaller than a thickness of the high-resistance nitride epitaxial layer 201.
Specifically, for example, the p-cap layer 202 wraps the high-resistance nitride epitaxial layer 201 exposed outside the first gate insulating layer 203. When the high-resistance nitride epitaxial layer 201 and the p-cap layer 202 are projected in the stacking direction of the stacked structure 100, the projection length of the p-cap layer 202 is longer than the projection length of the high-resistance nitride epitaxial layer 201. And, the positions of the p-cap layer 202 having a projection length longer than the projection length of the high-resistance nitride epitaxial layer 201 are respectively located at the left and right sides of the high-resistance nitride epitaxial layer 201. Specifically, the region of the p-cap layer 202 that is longer than the high-resistance nitride epitaxial layer 201 may be set to be longer in the left side region, longer in the right side region, or the length of the left side region may be equal to the length of the right side region, which is not particularly limited herein. Specifically, the adjustment of the position between the p-cap layer 202 and the high-resistance nitride epitaxial layer 201 can be achieved by controlling experimental parameters in the growth process.
The semiconductor device 10 further includes a source electrode 300 and a drain electrode 400 disposed on the channel layer 104 at intervals.
A gate structure 200 formed between the source electrode 300 and the drain electrode 400 and disposed on the first barrier layer 105. A gate electrode 205 is disposed on a surface of the p-cap layer 202 remote from the high-resistance nitride epitaxial layer 201.
The semiconductor device 10 provided in this embodiment has a high threshold voltage, and can alleviate gate leakage, expand the gate voltage operating range, and improve the reliability of the device. Specifically, the high-resistance nitride epitaxial layer 201 in the gate structure 200 may be used as a nucleation layer of the p-cap layer 202 to improve the crystallization quality of the p-cap layer 202. The high resistance nitride epitaxial layer 201 is provided to prevent Mg diffusion from degrading the channel. The high-resistance nitride epitaxial layer 201 is provided to effectively reduce the leakage current of the gate electrode 205. Therefore, by arranging the special gate structure 200 in this embodiment, the gate leakage is reduced, so that the device has a larger gate voltage working range, and the reliability of the device is greatly improved.
Referring to fig. 1, in a first embodiment of the present application, the gate structure 200 has: a first gate stack 210 and a second gate stack 220.
The first gate stack 210 includes a gate stack formed by the p-cap layer 202, the high-resistance nitride epitaxial layer 201, the first barrier layer 105, and the channel layer 104 from top to bottom; the p-cap layer 202 and the first barrier layer 105 are separated by the high-resistance nitride epitaxial layer 201 in the first gate stack 210, the p-cap layer 202 cannot deplete the two-dimensional electron gas at the interface between the first barrier layer 105 and the channel layer 104, and the first gate stack 210 has the two-dimensional electron gas at the gate voltage of 0V;
the second gate stack 220 includes a gate stack formed by the p-cap layer 202, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104 from top to bottom; the p-cap layer 202 in the second gate stack 220 can deplete the two-dimensional electron gas at the interface of the first barrier layer 105 and the channel layer 104, and the second gate stack 220 can deplete the two-dimensional electron gas at a gate voltage of 0V.
In this embodiment, when no bias voltage is applied to the gate electrode 205, the high-resistance nitride epitaxial layer 201 is located between the p-cap layer 202 and the first barrier layer 105 in the portion of the first gate stack 210, and the two-dimensional electron gas of the projection region at the interface of the channel layer 104/the first barrier layer 105 is not consumed by the p-cap layer 202 because the p-cap layer 202 and the first barrier layer 105 are separated by the high-resistance nitride epitaxial layer 201, so that the two-dimensional electron gas at the interface of the first barrier layer 105/the channel layer 104 cannot be consumed by the p-cap layer 202, and the two-dimensional electron gas at the interface of the first gate stack 210 is continuous.
When no bias voltage is applied to the gate electrode 205, the second gate stack 220 may cause the two-dimensional electron gas of the projection region at the channel layer 104/first barrier layer 105 interface to be depleted by the P-cap layer 202 due in part to the presence of only the first gate insulating layer 203 between the P-cap layer 202 and the first barrier layer 105, such that the two-dimensional electron gas of the second gate stack 220 at the channel layer 104/first barrier layer 105 interface is discontinuous.
Upon application of a bias voltage greater than a threshold voltage to the gate electrode 205, the second gate stack 220 partially recovers the two-dimensional electron gas at the channel layer 104/first barrier layer 105 interface such that the two-dimensional electron gas at the channel layer 104/first barrier layer 105 interface forms a continuous integral body between the source electrode 300 and the drain electrode 400.
In this way, by controlling the bias voltage supplied from the gate electrode 205, it is possible to control whether or not the two-dimensional electron gas is a continuous whole between the source electrode 300 and the drain electrode 400, thereby controlling whether or not the semiconductor device 10 is turned on by controlling the voltage applied to the gate electrode 205.
In this embodiment, the gate structure 200 includes the first gate stack 210 and the second gate stack 220 by adding the high-resistance nitride epitaxial layer 201 to the gate structure 200. And, when no bias voltage is applied to the gate electrode 205, the two-dimensional electron gas at the channel layer 104/first barrier layer 105 interface by the first gate stack 210 is continuous; the second gate stack 220 is partially discontinuous in two-dimensional electron gas at the channel layer 104/first barrier layer 105 interface. The high-resistance nitride epitaxial layer 201 is disposed between the first barrier layer 105 and the p-cap layer 202, and the on-resistance of the PN junction formed by the first barrier layer 105 and the p-cap layer 202 can be increased, so that after the bias voltage is applied to the gate electrode 205, the leakage current of the gate electrode 205 can be effectively reduced due to the increase of the on-resistance.
Referring now to fig. 2, fig. 2 illustrates a first embodiment of the present invention of a semiconductor device 10 having a structure different from that of the high-resistance nitride epitaxial layer 201 illustrated in fig. 1. The different structures of the high-resistance nitride epitaxial layer 201 depicted in fig. 1 and 2 are two forms that are unavoidable during the growth process, and are explicitly illustrated herein. It will be appreciated that the structure of the high-resistance nitride epitaxial layer 201 in the second, third, fourth and fifth embodiments described below may also be the structure shown in fig. 2.
Referring to fig. 3, in a second embodiment of the present application, the p-cap layer 202 includes: a first cap layer 212 of high doping concentration and a second cap layer 222 of low doping concentration.
The second cap layer 222 encapsulates the first cap layer 212. The first cap layer 212 is in contact with the high-resistance nitride epitaxial layer 201. The second cap layer 222 is remote from the high-resistance nitride epitaxial layer 201.
The p-cap layer 202 in the first embodiment is replaced in this embodiment by a layer containing a high doping concentration + GaN (the first cap layer 212) and p of low doping concentration - Two parts of GaN (the second cap layer 222), and relative to p + -GaN，p - GaN is closer to the gate electrode 205. Wherein p of high doping concentration + The GaN doping concentration can range from 10 18 -10 22 cm -3 P of low doping concentration - The GaN doping concentration can range from 10 16 -10 20 cm -3 . Such as: p of high doping concentration + GaN doping concentration of 5X 10 19 cm -3 P of low doping concentration - GaN doping concentration 5X 10 17 cm -3 . In this embodiment, p - GaN (second cap layer 222) is depleted due to its lower doping concentrationUnder the condition that the internal electric field and the external electric field are relatively smaller, the structure is similar to a field plate structure, and the internal peak electric field can be effectively reduced.
Referring to fig. 4, in a third embodiment of the present application, the semiconductor device 10 further includes a second barrier layer 106.
The second barrier layer 106 comprises two parts. A first portion of the second barrier layer 106 is formed between the first barrier layer 105 and the high-resistance nitride epitaxial layer 201. A second portion of the second barrier layer 106 is formed on a surface of the first gate insulating layer 203 remote from the first barrier layer 105. And, a portion of the surface of the p-cap layer 202 covers the second barrier layer 106.
In this embodiment, after the stacked structure 100 and the first gate insulating layer 203 are prepared, the second barrier layer 106 with a certain thickness is grown after the first gate insulating layer 203 (and the passivation layer) is etched away at the future gate electrode position to expose the first barrier layer 105. In the region where the first barrier layer 105 is exposed (without the first gate insulating layer 203), since the crystal structure between the second barrier layer 106 and the first barrier layer 105 is similar, single crystal growth can be achieved in this region, i.e., the thickness of the barrier layer is increased, so that the underlying 2DEG has a higher areal charge density. In the region where the first gate insulating layer 203 remains, since the first gate insulating layer 203 (e.g., siN) has a crystal structure different from that of the second barrier layer 106 (e.g., alGaN) and is even amorphous, single crystal growth of the second barrier layer 106 or only polycrystalline or amorphous growth cannot be achieved thereon. Therefore, in this embodiment, the second barrier layer 106 is provided to improve the 2DEG performance of the opening area, and at the same time, to improve the on-resistance of the PN junction and reduce the leakage current.
Referring to fig. 5, in a fourth embodiment of the present application, the semiconductor device 10 further includes a second gate insulating layer 204.
The second gate insulating layer 204 is disposed on a surface of the first gate insulating layer 203 away from the first barrier layer 105. The thickness of the second gate insulating layer 204 is smaller than the thickness of the p-cap layer 202, and a portion of the p-cap layer 202 covers the second gate insulating layer 204. It will be appreciated that in further embodiments a third gate insulation layer or more insulation layer structures may also be included to form a multi-layer field plate structure.
In this embodiment, a thick second gate insulating layer 204 is formed on the basis of the first gate insulating layer 203 provided in the first embodiment. The presence of the second gate insulation layer 204 allows the p-cap layer 202 located thereon to have a large distance from the underlying two-dimensional electron gas channel. Such a structure can improve the electric field distribution, avoid the excessive electric field intensity at the edge of the p-cap layer 202 (the arrow pointing in fig. 5), avoid the electric field spike at the edge of the p-cap layer 202, and make the electric field distribution more uniform and smooth.
In a fourth embodiment of the present application, the gate structure 200 further has: third gate stack 230.
The third gate stack 230 includes a gate stack formed from the p-cap layer 202, the second gate insulating layer 204, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104 from top to bottom. The p-cap layer 202 in the third gate stack 230 cannot deplete the two-dimensional electron gas at the interface of the first barrier layer 105 and the channel layer 104, and the third gate stack 230 has a two-dimensional electron gas at a gate voltage of 0V.
In this embodiment, the gate structure 200 further has the third gate stack 230. The third gate stack 230 expands the coverage of the p-cap layer 202, improves the electric field distribution, and avoids the excessive electric field strength at the edge of the p-cap layer 202. That is, the third gate stack 230 is arranged to avoid the occurrence of electric field spikes as much as possible, so that the electric field distribution is more uniform and smooth.
Referring to fig. 6, a fifth embodiment may be further included in the present application, where in the structure including the second gate insulating layer 204 in the fourth embodiment, further disposing the p-cap layer 202 includes: a first cap layer 212 of high doping concentration and a second cap layer 222 of low doping concentration. In this embodiment, the gate structure 200 further has a fourth gate stack structure 240. Fourth gate stack 240 in this embodiment is similar in structure and function to third gate stack 230 in the fourth embodiment.
In this embodiment, the third gate stack 230 includes a gate stack formed by the p-cap layer 202 (the second cap layer 222 with low doping concentration), the p-cap layer 202 (the first cap layer 212 with high doping concentration), the second gate insulating layer 204, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104 from top to bottom. The fourth gate stack 240 includes a gate stack formed by the p-cap layer 202 (the second cap layer 222 with low doping concentration), the second gate insulating layer 204, the first gate insulating layer 203, the first barrier layer 105, and the channel layer 104 from top to bottom.
The p-cap layer 202 in the third gate stack 230 and the fourth gate stack 240 cannot deplete the two-dimensional electron gas at the interface of the first barrier layer 105 and the channel layer 104, and the third gate stack 230 has a two-dimensional electron gas at a gate voltage of 0V.
In this embodiment, the gate structure 200 further has the third gate stack 230 and the fourth gate stack 240. The third gate stack 230 and the fourth gate stack 240 expand the coverage of the p-cap layer 202, improve the electric field distribution, and avoid the excessive electric field strength at the edge of the p-cap layer 202. That is, the arrangement of the third gate stack 230 and the fourth gate stack 240 avoids the occurrence of electric field spikes as much as possible, and makes the electric field distribution more uniform and smooth.
In the semiconductor device 10 mentioned above in this application, the optional materials and thickness ranges for the various film layers may be determined with reference to the following description:
the substrate 101 may be a silicon substrate, a SiC substrate, a sapphire substrate, or a GaN substrate.
The preparation methods of the insertion layer 102, the buffer layer 103, the channel layer 104, the first barrier layer 105, and the second barrier layer 106 may be performed by metal-organic chemical vapor deposition or molecular beam epitaxy.
The insertion layer 102 may be provided as an AlN material. The thickness of the interposer 102 may be 0.05um to 0.35um. In one embodiment, the thickness of the interposer 102 is set to 0.15um; in one embodiment, the thickness of the interposer 102 is set to 0.2um; in one embodiment, the thickness of the interposer 102 is set to 0.25um.
The buffer layer 103 may be provided as a GaN buffer layer, an AlGaN buffer layer, or a C-doped gallium nitride buffer layer. In one embodiment, the buffer layer 103 may be one or more layers of structure, such as one or more layers of AlGaN. The thickness of the buffer layer 103 may be 0.5um to 4.0um. For example, the thickness of the buffer layer 103 may be 0.1um, 0.2um, 0.25um, or 4.0um.
The channel layer 104 may be provided as GaN. The thickness of the channel layer 104 may be 1.0um to 5.0um. In one embodiment, the channel layer 104 may have a thickness of 1.5um, 2.0um, 2.5um, or 3um.
The first barrier layer 105 and the second barrier layer 106 may be provided as AlGaN, alInN, or AlInGaN. The thickness of the first barrier layer 105 may be set to 5nm to 40nm. For example, the first barrier layer 105 may have a thickness of 10nm, 15nm, 25nm, 30nm, or 35nm. The thickness of the second barrier layer 106 may be set to 0.5nm to 25nm. For example, the thickness of the second barrier layer 106 may be set to 1nm, 6nm, 15nm, 18nm, or 20nm.
In one embodiment, the high-resistance nitride epitaxial layer 201 may be provided as an unintentionally doped nitride, a carbon doped nitride, or an iron doped nitride. Specifically, for example, the high-resistance nitride epitaxial layer 201 may be unintentionally doped GaN, unintentionally doped AlN, unintentionally doped AlGaN, or other unintentionally doped nitride. The high-resistance nitride epitaxial layer 201 may also be carbon doped GaN, carbon doped AlN, carbon doped AlGaN, or other carbon doped nitride. The high-resistance nitride epitaxial layer 201 may also be iron doped GaN, iron doped AlN, iron doped AlGaN, or other iron doped nitride.
In one embodiment, the high resistance nitride epitaxial layer 201 has a thickness greater than 20nm. For example, the high resistance nitride epitaxial layer 201 may have a thickness of 22nm, 40nm, 50nm, 70nm, 100nm or more.
The p-cap layer 202 may be p-GaN, p-AlGaN, p-InGaN, p-AlInGaN, or other p-type material. In general, the p-cap layer 202 may be formed after GaN Mg-doped annealing. The thickness of the p-cap layer 202 may be 0.1um to 0.6um. In one embodiment, the thickness of the p-cap layer 202 is set to 0.2um; in one embodiment, the thickness of the p-cap layer 202 is set to 0.25um; in one embodiment, the thickness of the p-cap layer 202 is set to 0.5um.
A gate electrode 205, which may be an ohmic contact or a schottky contact, is also provided over the p-cap layer 202.
In other embodiments, the interposer 102, the buffer layer 103, the channel layer 104, the first barrier layer 105, and the second barrier layer 106 may be binary arsenides and nitrides such as GaAs, inP, alN, inN, gaN, ternary arsenides and nitrides such as InGaAs, alGaAs, alGaN or InGaN, or quaternary arsenides and nitrides such as InGaAsP and AlInGaN.
Referring to fig. 7 and 8, the present application provides a method for manufacturing the semiconductor device 10 according to the first embodiment, which includes the following steps:
s10, sequentially preparing an insertion layer 102, a buffer layer 103, a channel layer 104, and a first barrier layer 105 on a first surface of a substrate 101 to form a laminated structure 100;
s20, forming a first gate insulating layer 203 on the first barrier layer 105, and etching the first gate insulating layer 203 to form a first groove exposing the first barrier layer 105, where a material of the first barrier layer 105 is a nitride semiconductor;
s30, epitaxially growing a high-resistance nitride epitaxial layer 201 to a selected region of the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer 201 is larger than that of the first gate insulating layer 203;
and S40, using the high-resistance nitride epitaxial layer 201 as a nucleation layer, and laterally epitaxially growing a p-cap layer 202, wherein the projection length of the p-cap layer 202 on the laminated structure 100 is larger than the projection length of the high-resistance nitride epitaxial layer 201 on the laminated structure 100.
After S40, the preparation method may further include:
the first gate insulating layer 203 and the first barrier layer 105 are etched, and a source electrode 300 and a drain electrode 400 are respectively deposited, the source electrode 300 and the drain electrode 400 being disposed on the channel layer 104 at a spacing.
A gate electrode 205 is further deposited on the p-cap layer 202.
In this embodiment, the core of the preparation method is the steps of "epitaxially growing the high-resistance nitride epitaxial layer 201 from the nitride semiconductor exposed by the first recess to the selected region of the first recess by using the nitride semiconductor exposed by the first recess as a nucleation layer" and "laterally epitaxially growing the p-cap layer 202 by using the high-resistance nitride epitaxial layer 201 as a nucleation layer", wherein the selected region epitaxial growth can sufficiently block dislocation from extending upward. In this embodiment, selective epitaxy/lateral epitaxy is adopted, a high-quality nitride crystal (the first barrier layer 105) of a gate region is used as a nucleation layer, a nitride epitaxial layer (the high-resistance nitride epitaxial layer 201) is selectively grown, and an epitaxial layer (the p-cap layer 202) is directly formed on the first gate insulating layer 203 by a lateral epitaxy method. This approach can obtain the p-cap layer 202 (e.g., p-GaN) with good crystal quality over the first gate insulating layer 203.
During this lateral epitaxy, by controlling the growth morphology of the epitaxy, no nitride epitaxial layer (the p-cap layer 202) will grow in other areas than on the gate region and its adjacent insulating layer.
Another core feature of the present preparation method is that a layer of high-resistance nitride epitaxial layer (the high-resistance nitride epitaxial layer 201) is epitaxially grown as a gate insulating layer before the p-cap layer 202 is grown, and the high-resistance epitaxial layer (the high-resistance nitride epitaxial layer 201) can be implemented in various ways (for example, doping C, fe elements during epitaxy).
In one embodiment, the steps of preparing the semiconductor device 10 described in the second embodiment are provided that are different from those of the first embodiment:
the p-cap layer 202 includes: a first capping layer 212 with a high doping concentration and a second capping layer 222 with a low doping concentration, the step of further depositing the p-cap layer 202 in S40 includes:
s41, taking the high-resistance nitride epitaxial layer 201 as a nucleation layer, and depositing a first cap layer 212 with high doping concentration;
s42, depositing the second cap layer 222 outside the first cap layer 212, where the second cap layer 222 wraps the first cap layer 212.
In this embodiment, the p-cap layer 202 in the first embodiment is replaced by a p layer containing a high doping concentration + GaN (the first cap layer 212) and p of low doping concentration - Two parts of GaN (the second cap layer 222), and relative to p + -GaN，p - GaN is closer to the gate electrode 205.P is p - GaN (the second cap layer 222) has a relatively low doping concentration, so that the internal and external electric fields are relatively small when it is depleted, and the internal peak electric field can be effectively reduced, similar to the field plate structure.
In one embodiment, the steps of preparing the semiconductor device 10 described in the third embodiment are provided that are different from those of the first embodiment: the semiconductor device 10 further includes a second barrier layer 106, and the S30 includes:
s31 depositing the second barrier layer 106 into the first recess and the first gate insulating layer 203, where the material of the second barrier layer 106 is a nitride semiconductor;
and S32, depositing the high-resistance nitride epitaxial layer 201 into the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer 201 is larger than that of the first gate insulating layer 203.
In this embodiment, the thicker second barrier layer 106 is added, and because the crystal structure between the second barrier layer 106 and the first barrier layer 105 is similar, single crystal growth can be achieved in this region, so that the underlying 2DEG has a higher surface charge density. In the region where the first gate insulating layer 203 remains, since the first gate insulating layer 203 (e.g., siN) has a crystal structure different from that of the second barrier layer 106 (e.g., alGaN) and is even amorphous, single crystal growth of the second barrier layer 106 or only polycrystalline or amorphous growth cannot be achieved thereon. Thus, in this embodiment, a portion of the surface of the p-cap layer 202 covers the second barrier layer 106. The second barrier layer 106 is provided mainly to improve the 2DEG performance of the opening region.
Referring to fig. 9 to 11, the present application provides a method for manufacturing a semiconductor device 10 according to a fourth embodiment, including:
s101, sequentially preparing an insertion layer 102, a buffer layer 103, a channel layer 104, and a first barrier layer 105 on a first surface of a substrate 101 to form a laminated structure 100;
s102, forming a first gate insulating layer 203 and a second gate insulating layer 204 on the first barrier layer 105, and performing first etching on the first gate insulating layer 203 and the second gate insulating layer 204 to form a first groove exposing the first barrier layer 105, wherein the material of the first barrier layer 105 is a nitride semiconductor;
s103, performing second etching on the second gate insulating layer 204 to form a second groove exposing the first gate insulating layer 203;
s104, epitaxially growing a high-resistance nitride epitaxial layer 201 to a selected region of the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer 201 is larger than that of the first gate insulating layer 203;
s105, using the high-resistance nitride epitaxial layer 201 as a nucleation layer, laterally epitaxially growing a p-cap layer 202 into the second groove, wherein a part of the p-cap layer 202 covers the second gate insulating layer 204, and the projection length of the p-cap layer 202 on the laminated structure 100 is greater than the projection length of the high-resistance nitride epitaxial layer 201 on the laminated structure 100.
In this embodiment, the core of the preparation method is the steps of "epitaxially growing the high-resistance nitride epitaxial layer 201 from the nitride semiconductor exposed in the first recess to the selected region of the first recess with the nitride semiconductor exposed in the first recess as a nucleation layer" and "laterally epitaxially growing the p-cap layer 202 from the high-resistance nitride epitaxial layer 201 to the second recess with the selected region epitaxial growth being capable of sufficiently blocking dislocation upward extension. In this embodiment, selective epitaxy/lateral epitaxy is adopted, a high-quality nitride crystal (the first barrier layer 105) of a gate region is used as a nucleation layer, a nitride epitaxial layer (the high-resistance nitride epitaxial layer 201) is selectively grown, and an epitaxial layer (the p-cap layer 202) is directly formed on the first gate insulating layer 203 by a lateral epitaxy method. This approach can obtain the p-cap layer 202 (e.g., p-GaN) with good crystal quality over the first gate insulating layer 203.
In this method, a thick second gate insulating layer 204 is formed on the basis of the method of the first embodiment. The presence of the second gate insulation layer 204 allows the p-cap layer 202 located thereon to have a large distance from the underlying two-dimensional electron gas channel. Such a structure can improve the electric field distribution, avoid the excessive electric field intensity at the edge of the p-cap layer 202 (the arrow pointing in fig. 5), avoid the electric field spike at the edge of the p-cap layer 202, and make the electric field distribution more uniform and smooth.
Referring to fig. 12, fig. 12 is a graph comparing performance of the semiconductor device 10 according to the embodiment of the present application with that of a conventional p-type gate structure.
Fig. 12 is a graph showing gate leakage contrast of a semiconductor device of a conventional p-type gate structure, a semiconductor device of a first embodiment of the present application, and a semiconductor device of a second embodiment of the present application. The same gate voltage is applied to the three, and the gate leakage of the semiconductor device of the first embodiment of the application and the gate leakage of the semiconductor device of the second embodiment of the application are obviously reduced compared with the gate leakage of the traditional semiconductor device. Meanwhile, the gate breakdown voltage of the semiconductor device in the two embodiments of the present application is much larger than that of the conventional scheme.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. A semiconductor device, comprising:
a stacked structure including at least a channel layer and a first barrier layer;
the grid structure comprises a high-resistance nitride epitaxial layer and a p-cap layer which are arranged in a stacked mode, wherein the projection length of the p-cap layer in the stacking direction of the stacked structure is larger than that of the high-resistance nitride epitaxial layer in the stacked structure; and
the gate structure further comprises a first gate insulating layer which is arranged on the surface of the first barrier layer far away from the channel layer, and the thickness of the first gate insulating layer is smaller than that of the high-resistance nitride epitaxial layer.
2. The semiconductor device of claim 1, wherein the gate structure has: a first gate stack and a second gate stack;
The first gate stack comprises a gate stack formed by the p-cap layer, the high-resistance nitride epitaxial layer, the first barrier layer and the channel layer from top to bottom; the p-cap layer and the first barrier layer are separated by the high-resistance nitride epitaxial layer in the first gate stack, the p-cap layer cannot deplete two-dimensional electron gas at the interface of the first barrier layer and the channel layer, and the first gate stack has two-dimensional electron gas when the gate voltage is 0V;
the second gate stack comprises a gate stack formed by the p-cap layer, the first gate insulating layer, the first barrier layer and the channel layer from top to bottom; the p-cap layer in the second gate stack can deplete the two-dimensional electron gas at the interface of the first barrier layer and the channel layer, and the second gate stack depletes the two-dimensional electron gas when the gate voltage is 0V.
3. The semiconductor device of claim 2, wherein the p-cap layer comprises: a first cap layer with high doping concentration and a second cap layer with low doping concentration;
the second cap layer wraps the first cap layer;
wherein the first cap layer is in contact with the high-resistance nitride epitaxial layer;
The second cap layer is remote from the high resistance nitride epitaxial layer.
4. The semiconductor device according to claim 2, characterized in that the semiconductor device further comprises:
a second barrier layer comprising two portions;
a first portion of the second barrier layer is formed between the first barrier layer and the high-resistance nitride epitaxial layer;
the second barrier layer of the second part is formed on the surface of the first gate insulating layer far away from the first barrier layer; and, a part of the surface of the p-cap layer covers the second barrier layer.
5. The semiconductor device according to claim 2, characterized in that the semiconductor device further comprises:
the second gate insulating layer is arranged on the surface, far away from the first barrier layer, of the first gate insulating layer, the thickness of the second gate insulating layer is smaller than that of the p-cap layer, and part of the p-cap layer covers the second gate insulating layer.
6. The semiconductor device of claim 5, wherein the gate structure further has: a third gate stack;
the third gate stack comprises a gate stack formed by the p-cap layer, the second gate insulating layer, the first barrier layer and the channel layer from top to bottom; the p-cap layer in the third gate stack cannot deplete the two-dimensional electron gas at the interface of the first barrier layer and the channel layer, and the third gate stack has the two-dimensional electron gas when the gate voltage is 0V.
7. The semiconductor device according to any one of claims 1-6, wherein the high-resistance nitride epitaxial layer is an unintentionally doped nitride, a carbon-doped nitride, or an iron-doped nitride.
8. The semiconductor device of claim 7, wherein the high resistance nitride epitaxial layer has a thickness greater than 20nm.
9. A method of fabricating a semiconductor device, comprising:
s10, sequentially preparing a laminated structure at least comprising a channel layer and a first barrier layer on a first surface of a substrate;
s20, forming a first gate insulating layer on the first barrier layer, and etching the first gate insulating layer to form a first groove exposing the first barrier layer, wherein the first barrier layer is made of a nitride semiconductor;
s30, epitaxially growing a high-resistance nitride epitaxial layer to a selected region of the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer is larger than that of the first gate insulating layer;
and S40, using the high-resistance nitride epitaxial layer as a nucleation layer, and laterally epitaxially growing a p-cap layer, wherein the projection length of the p-cap layer on the laminated structure is larger than that of the high-resistance nitride epitaxial layer on the laminated structure.
10. The method of claim 9, wherein the p-cap layer comprises: a first cap layer with high doping concentration and a second cap layer with low doping concentration, wherein the step of further depositing a p-cap layer in S40 comprises:
s41, depositing a first cap layer with high doping concentration by taking the high-resistance nitride epitaxial layer as a nucleation layer;
s42, depositing the second cap layer outside the first cap layer, wherein the second cap layer wraps the first cap layer.
11. The method of manufacturing according to claim 9, wherein the semiconductor device further comprises a second barrier layer, and wherein S30 comprises:
s31, depositing the second barrier layer into the first groove and the first gate insulating layer, wherein the material of the second barrier layer is nitride semiconductor;
and S32, depositing the high-resistance nitride epitaxial layer into the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer is larger than that of the first gate insulating layer.
12. A method of fabricating a semiconductor device, comprising:
s101, sequentially preparing a laminated structure at least comprising a channel layer and a first barrier layer on a first surface of a substrate;
S102, forming a first gate insulating layer and a second gate insulating layer on the first barrier layer, and performing first etching on the first gate insulating layer and the second gate insulating layer to form a first groove exposing the first barrier layer, wherein the first barrier layer is made of a nitride semiconductor;
s103, performing second etching on the second gate insulating layer to form a second groove exposing the first gate insulating layer;
s104, epitaxially growing a high-resistance nitride epitaxial layer to a selected region of the first groove by taking the nitride semiconductor exposed by the first groove as a nucleation layer, wherein the thickness of the high-resistance nitride epitaxial layer is larger than that of the first gate insulating layer;
s105, using the high-resistance nitride epitaxial layer as a nucleation layer, laterally epitaxially growing a p-cap layer into the second groove, and covering the second gate insulating layer by a part of the p-cap layer, wherein the projection length of the p-cap layer on the laminated structure is larger than that of the high-resistance nitride epitaxial layer on the laminated structure.
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