CN210429813U - Display back plate and display device - Google Patents
Display back plate and display device Download PDFInfo
- Publication number
- CN210429813U CN210429813U CN201921941293.8U CN201921941293U CN210429813U CN 210429813 U CN210429813 U CN 210429813U CN 201921941293 U CN201921941293 U CN 201921941293U CN 210429813 U CN210429813 U CN 210429813U
- Authority
- CN
- China
- Prior art keywords
- electrode
- display
- thin film
- film transistor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model provides a show backplate and display device. The display back plate has a plurality of opening regions for emitting light, including: a substrate base plate; an active layer disposed on a portion of a surface of the base substrate; an interlayer insulating layer disposed on a portion of a surface of the active layer away from the base substrate; the storage capacitor comprises a first electrode and a second electrode which are oppositely arranged, the first electrode is arranged on part of the surface of the substrate base plate, the second electrode is arranged on one side, away from the substrate base plate, of the first electrode, the orthographic projection of the storage capacitor on the substrate base plate is at least partially overlapped with the orthographic projection of the opening area in the display back plate on the substrate base plate, the interlayer insulating layer is provided with a first hole, and the first electrode is arranged in the first hole. The storage capacitor which should occupy the non-opening area in the display back plate is arranged in the opening area, so that the area of the non-opening area is obviously reduced, the opening rate of the display back plate is obviously increased, the service life of the display back plate is long, and the reliability is good.
Description
Technical Field
The utility model relates to a show technical field, specifically, relate to show backplate and display device.
Background
Currently, Active Matrix Organic Light Emitting Diodes (AMOLEDs) are expected to replace liquid crystals as the mainstream choice for next generation display devices due to high contrast, wide viewing angle and fast response speed. However, the aperture ratio of the AMOLED display backplane still needs to be improved.
Thus, the related art of the existing display backplane still needs to be improved.
SUMMERY OF THE UTILITY MODEL
The present invention aims at solving at least one of the technical problems in the related art to a certain extent. Therefore, an object of the present invention is to provide a display back plate with a small non-opening area, a high opening ratio, a long service life, or a high reliability.
In one aspect of the present invention, the utility model provides a display back plate. According to the utility model discloses an embodiment, this show backplate has a plurality of open areas that are used for luminous, include: a substrate base plate; an active layer disposed on a portion of a surface of the base substrate; an interlayer insulating layer disposed on a portion of a surface of the active layer away from the base substrate; the storage capacitor comprises a first electrode and a second electrode which are oppositely arranged, the first electrode is arranged on part of the surface of the substrate base plate, the second electrode is arranged on one side, away from the substrate base plate, of the first electrode, the orthographic projection of the storage capacitor on the substrate base plate is at least partially overlapped with the orthographic projection of the opening area in the display back plate on the substrate base plate, the interlayer insulating layer is provided with a first hole, and the first electrode is arranged in the first hole. In the display back plate, the orthographic projection of the storage capacitor on the substrate base plate is at least partially overlapped with the orthographic projection of the opening area in the display back plate on the substrate base plate, so that the storage capacitor which should occupy the non-opening area is arranged in the opening area, the area of the non-opening area in the display back plate is obviously reduced, the opening ratio of the display back plate is obviously increased, the service life of the display back plate is further prolonged, and the reliability is good.
Optionally, the first hole is a through hole.
Optionally, the first hole is a blind hole.
Optionally, an orthographic projection of the storage capacitor on the substrate base plate overlaps with an orthographic projection of the opening region on the substrate base plate.
Optionally, the display backplane is a bottom emission display backplane, the first electrode and the second electrode are transparent electrodes, and a material forming at least one of the first electrode and the second electrode is indium tin oxide.
Optionally, the storage capacitor is disposed between the buffer layer of the display backplane and the anode of the pixel structure, and at least one insulating layer is disposed between the first electrode and the second electrode.
Optionally, the display backplane further includes: a planarization layer disposed on a surface of the first electrode remote from the substrate base plate; the pixel structure comprises an anode, and is arranged on one side, away from the substrate, of the planarization layer, wherein the second electrode is arranged on the surface, away from the substrate, of the planarization layer, and is connected with the anode.
Optionally, the display backplane further includes: a source electrode of the third thin film transistor is connected with a power bus of the display back plate, and a drain electrode of the third thin film transistor is connected with the second electrode and the anode; the light shielding layer is arranged on part of the surface of the substrate, the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the active layer of the third thin film transistor on the substrate, and the light shielding layer is connected with the source electrode or the drain electrode of the third thin film transistor in the display back plate through a third through hole in the active layer.
Optionally, the display back plate includes a first thin film transistor, a second thin film transistor, and a third thin film transistor, a gate of the first thin film transistor is connected to the first scan line of the display back plate, a source of the first thin film transistor is connected to the data line of the display back plate, and a drain of the first thin film transistor is connected to the first electrode and the gate of the third thin film transistor; the grid electrode of the second thin film transistor is connected with a second scanning line of the display back plate, the source electrode of the second thin film transistor is connected with the second electrode, the drain electrode of the third thin film transistor and the anode of the display back plate, and the drain electrode of the second thin film transistor is connected with a reference voltage signal line of the display back plate; and the source electrode of the third thin film transistor is connected with a power bus of the display backboard.
Optionally, the planarization layer has a first via hole thereon, and the second electrode is connected to the drain of the third tft in the display backplane through the first via hole.
In another aspect of the present invention, the present invention provides a display device. According to the utility model discloses an embodiment, this display device includes preceding demonstration backplate. The display device has long service life and good reliability, and has all the characteristics and advantages of the display back plate, which are not described in detail herein.
Drawings
Fig. 1 shows a schematic structural diagram of a pixel circuit in a display backplane of the present invention.
Fig. 2 is a schematic cross-sectional view of a display back plate according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a display back plate according to another embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a display back plate according to another embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a display back plate according to still another embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a display back plate according to still another embodiment of the present invention.
Fig. 7 is a schematic flow chart illustrating a method for manufacturing a display backplane according to an embodiment of the present invention.
Fig. 8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h, and 8i are schematic flow diagrams illustrating a method for manufacturing a display back plate according to another embodiment of the present invention.
Fig. 9 is a schematic plan view illustrating a first electrode formed in a method for manufacturing a display backplane according to an embodiment of the present invention.
Fig. 10 is a schematic plan view illustrating a halftone mask used in a method for manufacturing a display backplane according to an embodiment of the present invention.
Fig. 11 is a schematic plan view illustrating a second electrode formed in the method for manufacturing a display backplane according to an embodiment of the present invention.
Fig. 12 is a schematic diagram showing a planar structure of a single sub-pixel of the display backplane shown in fig. 5 according to the embodiment of the present invention.
Reference numerals:
2: a body 3: the hollow part 10: display backplane 100: substrate CST: the storage capacitor 210: first electrode 220: second electrode 300: buffer layer 310: light-shielding layer 400: anode 410:pixel defining layer EL: pixel structure 420: cathode 430: light-emitting layer 500: insulating layer 510: interlayer insulating layer 511: first hole 512: second hole 513: third hole 520: the planarization layer 521: first via 530: resin layer 531: second via 541: third via 600: active layer 610: channel region 700: gate electrode 710: the gate insulating layer 800: source 900: a drain electrode H: opening region Vref: reference voltage signal line T1: a first thin film transistor T2: a second thin film transistor T3: third thin film transistor Scan 1: first Scan line Scan 2: second scanning line VDD: power bus DL: data line
Detailed Description
Embodiments of the present invention are described in detail below. The following description of the embodiments is merely exemplary in nature and is in no way intended to limit the invention. The examples, where specific techniques or conditions are not indicated, are to be construed according to the techniques or conditions described in the literature in the art or according to the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products commercially available.
In one aspect of the present invention, the utility model provides a display back plate. According to the embodiment of the present invention, referring to fig. 2, 5 and 6 (to more clearly show the position relationship between the opening region H and the first and second electrodes 210 and 220, therefore, other structures in the display back plate 10 are omitted in fig. 2 and later fig. 3 and 4, and the detailed structure of the display back plate 10 may refer to fig. 5 and 6), the display back plate 10 has a plurality of opening regions H for emitting light, including: a base substrate 100; an active layer 600, the active layer 600 being disposed on a portion of a surface of the substrate base plate 100; an interlayer insulating layer 510, wherein the interlayer insulating layer 510 is disposed on a portion of the surface of the active layer 600 away from the substrate base plate 100; a storage capacitor including a first electrode 210 and a second electrode 220, the first electrode 210 being disposed on a portion of the surface of the substrate 100, the second electrode 220 being disposed on a side of the first electrode 210 away from the substrate 100, wherein an orthographic projection of the storage capacitor on the substrate 100 of the display backplane 10 at least partially overlaps an orthographic projection of an opening area in the display backplane 10 on the substrate, the interlayer insulating layer has a first hole 511, and the first electrode 210 is disposed in the first hole 511. In the display back plate 10, because the orthographic projection of the storage capacitor on the substrate base plate 100 is at least partially overlapped with the orthographic projection of the opening area H in the display back plate 10 on the substrate base plate 100, the storage capacitor which should occupy a non-opening area is arranged in the opening area H, the area of the non-opening area in the display back plate 10 is obviously reduced, the opening ratio of the display back plate 10 is obviously increased, and further, the display back plate 10 has long service life and good reliability.
According to the embodiment of the present invention, in the description herein, all the drawings are based on the circuit diagram shown in fig. 1, and the electrical connection relationship of all the layer structures herein conforms to the circuit connection relationship shown in fig. 1, and the description thereof is not repeated herein.
According to an embodiment of the present invention, further, referring to fig. 3, an orthographic projection of the storage capacitor on the substrate base plate 100 overlaps with an orthographic projection of the opening region H on the substrate base plate 100. Therefore, the storage capacitor which should occupy the non-opening area is arranged in the opening area H, the area of the non-opening area in the display backboard 10 is obviously reduced, the opening rate of the display backboard 10 is obviously increased, the service life of the display backboard 10 is prolonged, the area of the storage capacitor is reduced on the basis of good reliability, materials are further saved, and the cost is lower.
According to the embodiment of the present invention, when the display back plate 10 is a top emission display back plate, the material forming the first electrode 210 and the second electrode 210 is not particularly limited, and may be the material forming the electrodes in the conventional display back plate 10, for example, may be specifically silver or copper. Therefore, the material source is wide, the material is easy to obtain, and the cost is lower.
According to the embodiment of the present invention, when the display back plate 10 is a bottom emission display back plate, the material forming the first electrode 210 and the second electrode 220 should be a transparent material, and the first electrode 210 and the second electrode 220 are transparent electrodes. Specifically, in some embodiments of the present invention, the material forming the first electrode 210 and the second electrode 220 may be ITO (indium tin oxide) or the like. Therefore, when the first electrode 210 and the second electrode 220 are disposed at positions where their orthographic projections at least partially overlap with the orthographic projection of the opening region H on the substrate 100, the normal display of the display backplane is not affected because the first electrode 210 and the second electrode 220 are transparent electrodes.
According to the embodiment of the present invention, the specific location of the storage capacitor is not particularly limited as long as the normal function of the storage capacitor can be realized, for example, in some embodiments of the present invention, referring to fig. 4, the storage capacitor is disposed between the buffer layer 300 of the display back plate 10 and the anode 400 of the pixel structure, and there is at least one insulating layer 500 between the first electrode 210 and the second electrode 220. Therefore, the storage capacitor in the display back plate can normally realize the use function; meanwhile, the first electrode 210 and the second electrode 220 are flexible in arrangement position, convenient to produce, low in cost and easy to industrialize.
According to an embodiment of the present invention, the first hole 511 may be a through hole (fig. 5). Therefore, in the opening region of the display back plate 10, the interlayer insulating layer 510 is not present, so that the distance between the first electrode 210 and the second electrode 220 can be made smaller, so as to increase the capacitance between the first electrode 210 and the second electrode 220; meanwhile, since the orthographic projection of the storage capacitor on the substrate base plate 100 is at least partially overlapped with the orthographic projection of the opening region H in the display back plate 10 on the substrate base plate 100, the storage capacitor which should occupy a non-opening region is arranged in the opening region, the area of the non-opening region in the display back plate 10 is obviously reduced, and the opening ratio of the display back plate 10 is obviously increased; in addition, since the first electrode 210 is disposed in the first hole 511 and the opening portion of the display back plate 10 does not have an interlayer insulating layer, the display back plate 10 has high light transmittance and good display effect.
In other embodiments of the present invention, the first hole 511 may also be a blind hole (fig. 6 for a schematic structural diagram). Therefore, in the opening area of the display back plate 10, since the orthographic projection of the storage capacitor on the substrate 100 is at least partially overlapped with the orthographic projection of the opening area H in the display back plate 10 on the substrate 100, the storage capacitor which should occupy a non-opening area is arranged in the opening area, the area of the non-opening area in the display back plate 10 is significantly reduced, and the opening ratio of the display back plate 10 is significantly increased; in addition, since the first electrode 210 is disposed in the first hole 511 and the thinned interlayer insulating layer 510 is disposed at the opening of the display back plate 10, the display back plate 10 has high light transmittance and good display effect.
According to the embodiment of the present invention, in the display back plate shown in fig. 5 and 6, in addition to the second electrode disposed at the position described above, the second electrode may be disposed in the planarization layer of the display back plate, the resin layer of the display back plate, or on a portion of the surface of the resin layer away from the substrate base plate (not shown in the figure). The first electrode in the above embodiment is the same as the first electrode in fig. 5 or 6, and the position of the second electrode is changed, so that the same technical effects as those in the previous embodiment can be achieved, and redundant description is omitted.
According to the embodiment of the present invention, referring to fig. 5 and 6, the display back plate 10 may further include: a planarization layer 520, wherein the planarization layer 520 is disposed on the surface of the first electrode 210 away from the substrate 100; a pixel structure including an anode 400, the pixel structure 400 being disposed on a side of the planarization layer 520 away from the substrate 100, the second electrode 220 being disposed on a surface of the planarization layer 520 away from the substrate 100, and the second electrode 220 being connected to the anode 400. Therefore, the arrangement position of the storage capacitor in the display back plate is changed, but all structures in the display back plate can still be connected well, and a good display effect is achieved.
According to the utility model discloses an embodiment, in addition, when it is the bottom emission to show the backplate, refer to fig. 5 and fig. 6, it can also include to show the backplate: a third thin film transistor, a source of the third thin film transistor is connected to a power bus (not shown in the figure) of the display backplane, and a drain 900 of the third thin film transistor is connected to the second electrode 220 and the anode 400; a light shielding layer 310, where the light shielding layer 310 is disposed on a partial surface of the substrate 100, an orthographic projection of the light shielding layer 310 on the substrate 100 covers an orthographic projection of the active layer 600 of the third thin film transistor on the substrate 100, and the light shielding layer 310 is connected to the source 800 of the third thin film transistor in the display backplane through a third via 541 in the active layer 600 (it should be noted that fig. 5 and 6 only show a case where the source 800 of the third thin film transistor is connected to the light shielding layer 310, and those skilled in the art can understand that the drain of the third thin film transistor may also be connected to the light shielding layer, which is not described herein again. Therefore, as can be understood by those skilled in the art, the light shielding layer can better protect the channel region of the third thin film transistor in the display backplane, and further achieve a normal display effect.
According to an embodiment of the present invention, referring to fig. 1, 9 and 12, the display backplane includes a first thin film transistor T1, a second thin film transistor T2 and a third thin film transistor T3, a gate of the first thin film transistor T1 is connected to a first Scan line Scan1 of the display backplane, a source of the first thin film transistor T1 is connected to a data line DL of the display backplane, and a drain of the first thin film transistor T1 is connected to the first electrode and a gate of the third thin film transistor T3; the gate of the second thin film transistor T2 is connected to the second Scan line Scan2 of the display backplane, the source of the second thin film transistor T2 is connected to the second electrode, the drain of the third thin film transistor T3 and the anode of the pixel structure in the display backplane, and the drain of the second thin film transistor T2 is connected to the reference voltage signal line Vref of the display backplane; the source of the third thin film transistor T3 is connected to the power bus VDD of the display backplane. Thus, the pixel circuits in the display backplane constitute a 3T1C circuit, thereby realizing the normal display thereof.
In a specific embodiment of the present invention, referring to fig. 5, 6, 9, 11 and 12, the display back plate includes: a base substrate 100; a light-shielding layer provided on a part of a surface of the base substrate (not shown in the figure); the active layer 600 is arranged on a part of the surface of the substrate 100, the orthographic projection of the light shielding layer 310 on the substrate 100 covers the orthographic projection of the active layer 600 of the third thin film transistor on the substrate 100, and the light shielding layer 310 is connected with the source electrode 800 of the third thin film transistor in the display backplane through a third via 541 in the active layer; an interlayer insulating layer 510, the interlayer insulating layer 510 being disposed on a portion of a surface of the active layer 600 away from the base substrate 100, the interlayer insulating layer having a first hole 511; a storage capacitor Cst including a first electrode 210 and a second electrode 220 that are oppositely disposed and transparent, the first electrode 210 being disposed on a portion of the surface of the substrate 100 and in the first hole 511, the storage capacitor Cst being disposed between the buffer layer 300 of the display backplane and the anode 400 of the pixel structure; a planarization layer 520, wherein the planarization layer 520 is disposed on the surface of the first electrode 210 away from the substrate 100, and the planarization layer 510 has a first via hole thereon, through which the second electrode 220 is connected to the drain of the third thin film transistor T3 in the display backplane; a pixel structure including an anode 400, the pixel structure being disposed on a side of the planarization layer 520 away from the substrate 100, the anode 400 being connected to the second electrode 220; a first thin film transistor T1, a gate of the first thin film transistor T1 being connected to the first Scan line Scan1 of the display backplane, a source of the first thin film transistor T1 being connected to the data line DL of the display backplane, a drain of the first thin film transistor T1 being connected to the first electrode 210 and a gate of the third thin film transistor T3; a second thin film transistor T2, a gate of the second thin film transistor T2 being connected to a second Scan line Scan2 of the display backplane, a source of the second thin film transistor T2 being connected to the second electrode 220, a drain of the third thin film transistor T3 and the anode 400, a drain of the second thin film transistor T2 being connected to a reference voltage signal line Vref of the display backplane 10; a third thin film transistor T3, a source of the third thin film transistor T3 being connected to the power supply bus VDD of the display backplane 10, wherein the second electrode 220 is disposed on a surface of the planarization layer 520 away from the substrate 100, and an orthographic projection of the storage capacitor Cst on the substrate 100 overlaps an orthographic projection of an opening area in the display backplane 10 on the substrate 100.
In another aspect of the present invention, a method of making the display backplane described above is provided. According to an embodiment of the present invention, the display backplane has a plurality of open areas for emitting light, the method comprising: providing a substrate base plate; forming an active layer on a portion of a surface of the base substrate; forming a first electrode on a part of the surface of the substrate base plate; forming an interlayer insulating layer on the active layer and a part of the surface of the first electrode away from the substrate base plate; forming a first hole on the interlayer insulating layer and exposing the first electrode; and forming a second electrode opposite to the first electrode on the side of the first electrode far away from the substrate, wherein the first electrode and the second electrode form a storage capacitor, and an orthographic projection of the storage capacitor on the substrate at least partially overlaps with an orthographic projection of the opening region on the substrate (the structural schematic diagram refers to fig. 2, 5 and 6). The method is simple and convenient to operate, easy to realize and easy for industrial production, and in the manufactured display back plate, the orthographic projection of the storage capacitor on the substrate base plate is at least partially overlapped with the orthographic projection of the opening area in the display back plate on the substrate base plate of the display back plate, so that the storage capacitor which should occupy the non-opening area is arranged in the opening area, the area of the non-opening area in the display back plate is obviously reduced, the opening rate of the display back plate is obviously increased, the service life of the display back plate is further prolonged, and the reliability is good.
According to an embodiment of the present invention, referring to fig. 7 and fig. 8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h, 8i, specifically, taking the structure of the display backplane 10 shown in fig. 5 as an example, the method may include the following steps:
s000: a light-shielding layer (not shown) is formed on a part of the surface of the base substrate.
According to the embodiment of the present invention, the process of forming the light shielding layer on the partial surface of the substrate base plate may include vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing, and the like. The process parameters of vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like are the process parameters of conventional vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like, and are not described in detail herein. Therefore, the light shielding layer can better protect a channel region of the third thin film transistor in the display back plate, and further normal display effect is achieved; meanwhile, the preparation process is simple and convenient, easy to realize and easy for industrial production.
S100: a buffer layer 300 of the display backplane is formed on the surface of the base substrate 100 and the light-shielding layer (see fig. 8a for a schematic cross-sectional structure).
According to the embodiment of the present invention, the process of forming the buffer layer 300 of the display backplane on the surface of the substrate base plate 100 may include vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing, and the like. The process parameters of vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like are the process parameters of conventional vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
S200: an active layer 600 of the display backplane is formed on a portion of the surface of the buffer layer 300 away from the substrate 100 (the cross-sectional structure is schematically shown in fig. 8 b).
According to the embodiment of the present invention, the buffer layer 300 is far away from the substrate base plate 100 is formed on the partial surface of the active layer 600 of the display backplane specifically can be formed by a composition process, the composition process can include steps of forming a semiconductor layer, coating photoresist on the partial surface of the substrate base plate 100, covering a mask on the surface of the semiconductor layer, exposing, developing, etching, stripping the photoresist, and the like, so as to form the active layer 600. The specific process parameters and the like of each step in the composition process are process parameters of a conventional composition process, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
S300: the first electrode 210 is formed on a portion of the surface of the buffer layer 300 away from the substrate 100 (the cross-sectional structure is schematically shown in fig. 8 c; the plan structure is schematically shown in fig. 9).
According to the embodiment of the present invention, the process of forming the first electrode 210 may be a magnetron sputtering technique, or may be vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing, or the like. The process parameters of the magnetron sputtering technology, the vacuum evaporation, the chemical vapor deposition, the spin coating, the inkjet printing and the like are the process parameters of the conventional magnetron sputtering technology, the vacuum evaporation, the chemical vapor deposition, the spin coating, the inkjet printing and the like, and redundant description is not repeated herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
S400: a gate insulating layer 710 and a gate electrode 700 are formed on a portion of the surface of the active layer 600 away from the buffer layer 300 (the cross-sectional structure is schematically shown in fig. 8 d).
According to the embodiment of the present invention, the gate insulating layer 710 and the gate electrode 700 may be formed through a patterning process, which may be to form a pre-formed insulating layer on the surface of the active layer 600 away from the substrate 100; then forming a prefabricated gate layer on the surface of the prefabricated insulating layer far away from the substrate 100; finally, the prefabricated insulating layer and the prefabricated gate layer are etched through a one-time composition process, the prefabricated insulating layer after the etching process forms the gate insulating layer 710 in the display back plate, the prefabricated gate layer after the etching process forms the gate 700 in the display back plate, and specific process parameters and the like of each step in the composition process are process parameters of a conventional composition process, and are not described in detail herein. Therefore, compared with the manufacturing method in the related technology, the method reduces one-time composition process, so the operation is simple, convenient and easy to realize, and the industrial production is easy to realize.
S500: an interlayer insulating layer 510 of a display backplane is formed on the active layer 600 and the surfaces of the buffer layer 300 and the gate electrode 700 away from the substrate 100 (the cross-sectional structure is schematically shown in fig. 8 e).
According to an embodiment of the present invention, the process of forming the interlayer insulating layer 510 of the display backplane on the surface of the substrate 100 away from the active layer 600 and the buffer layer 300 and the gate 700 may include forming the insulating layer by vacuum evaporation, chemical vapor deposition, spin coating, and inkjet printing, and then forming a first hole, a second hole, and a third hole (not shown in the figure) penetrating through the insulating layer in the insulating layer by using a mask respectively, thereby forming the first hole and the interlayer insulating layer 510, the second hole being used for connecting the source electrode of the third thin film transistor in the display backplane to the active layer, and the third hole being used for connecting the drain electrode of the third thin film transistor to the active layer (not shown in the figure). In other embodiments of the present invention, a halftone mask may also be used to form a first hole, a second hole and a third hole (not shown in the figure), wherein the second hole and the third hole are through holes (the halftone mask includes a body 2 and a hollow portion 3, and the schematic plane structure thereof refers to fig. 10, wherein the body 2 is used to cover the aforementioned portion that does not need to be etched in the insulating layer, and the hollow portion 3 is the portion that needs to be etched, so that only the portion exposed in the hollow portion 3 can be etched when etching). The process parameters of vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like are the process parameters of conventional vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
S600: and forming a source 800 and a drain 900 of a third thin film transistor in the display backplane (the cross-sectional structure is schematically shown in fig. 8 f).
According to the utility model discloses an embodiment, form show that the specific technology of the source electrode 800 and the drain electrode 900 of backplate is the same with the specific technology of the source electrode and the drain electrode of conventional formation display backplate, no longer has too much repeated description here.
S700: a planarization layer 520 of the display backplane is formed, and a first via 521 is formed on the planarization layer 520 (the cross-sectional structure is schematically shown in fig. 8 g).
According to the embodiment of the present invention, the process of forming the planarization layer 520 of the display back plate may include forming an insulating layer through processes such as vacuum evaporation, chemical vapor deposition, spin coating, and inkjet printing, and then forming via holes in the insulating layer, thereby forming the planarization layer 520 of the display back plate. The process parameters of vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like are the process parameters of conventional vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
According to the embodiment of the present invention, the specific process for forming the first via 521 is not particularly limited, for example, the planarization layer 520 may be directly perforated after being formed, or other conventional processes for forming a via in the art may also be used, and will not be described herein again.
S800: the second electrode 220 is formed, and the second electrode 220 is connected to the drain electrode 900 through the first via 521 (the cross-sectional structure is schematically shown in fig. 8 h; the plan structure is schematically shown in fig. 11).
According to the embodiment of the present invention, the process of forming the second electrode 220 may be a magnetron sputtering technique, or may be vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing, or the like. The process parameters of the magnetron sputtering technology, the vacuum evaporation, the chemical vapor deposition, the spin coating, the inkjet printing and the like are the process parameters of the conventional magnetron sputtering technology, the vacuum evaporation, the chemical vapor deposition, the spin coating, the inkjet printing and the like, and redundant description is not repeated herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
S900: forming a resin layer 530 of the display backplane, forming a second via 531 on the resin layer 530, and connecting an anode of a pixel structure in the display backplane and the second electrode 220 through the second via 531 (refer to fig. 8i, 5 and 6 for schematic cross-sectional structure).
According to an embodiment of the present invention, the process of forming the resin layer 530 may include vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing, and the like. The process parameters of vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like are the process parameters of conventional vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
According to the embodiment of the present invention, a specific process for forming the second via 531 is not particularly limited, for example, a hole may be directly formed in the planarization layer 531 after the resin layer 530 is formed, or other conventional processes for forming a via hole in the art may be used, and are not described herein in too much detail.
According to the embodiment of the present invention, it can be understood by those skilled in the art that after the resin layer 530 and the second via hole 531 are formed, a step of forming a color film and a pixel structure on the surface of the substrate 100 away from the resin layer 530 may be further included, wherein specific processes, conditions and parameters for forming the color film and the pixel structure are the same as those for forming the color film (not shown in the figure) and the pixel structure conventionally, and are not repeated herein, and the pixel structure may specifically include the anode 400, the cathode 420, the light emitting layer 430 and the pixel defining layer 410. Therefore, the display back plate (the cross-sectional schematic view is shown in fig. 5, and the plane structure schematic view of a single sub-pixel is shown in fig. 12) can be obtained well, is simple and convenient, and is easy for industrial production.
In yet another aspect of the present invention, the present invention provides a display device. According to the utility model discloses an embodiment, this display device includes preceding demonstration backplate. The display device has long service life and good reliability, and has all the characteristics and advantages of the display back plate, which are not described in detail herein.
According to the utility model discloses an embodiment, this display device still includes other necessary structures and constitutions except the preceding demonstration backplate, and the technical personnel in the field can supplement and design according to display device's specific kind and operation requirement, no longer has too much repeated description here.
According to the embodiment of the present invention, the specific type of the display device is not particularly limited, for example, including but not limited to a display panel, a mobile phone, a tablet computer, a wearable device, a game machine, and the like.
In the description of the present invention, it is to be understood that the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present application, unless expressly stated or limited otherwise, the first feature may be directly on or directly under the second feature or indirectly via intermediate members. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art without departing from the scope of the present invention.
Claims (11)
1. A display backplane having a plurality of open areas for emitting light, comprising:
a substrate base plate;
an active layer disposed on a portion of a surface of the base substrate;
an interlayer insulating layer disposed on a portion of a surface of the active layer away from the base substrate;
a storage capacitor including a first electrode and a second electrode that are arranged oppositely, the first electrode being arranged on a part of a surface of the base substrate, the second electrode being arranged on a side of the first electrode away from the base substrate,
wherein an orthographic projection of the storage capacitor on a substrate of the display backplane at least partially overlaps an orthographic projection of an open area in the display backplane on the substrate, the interlayer insulating layer having a first hole in which the first electrode is disposed.
2. The display backplane of claim 1, wherein the first hole is a through hole.
3. The display backplane of claim 1, wherein the first hole is a blind hole.
4. The display backplane of claim 1, wherein an orthographic projection of the storage capacitor on the substrate base overlaps an orthographic projection of the open area on the substrate base.
5. The display backplane of claim 1, wherein the display backplane is a bottom emitting display backplane, the first electrode and the second electrode are transparent electrodes, and a material forming at least one of the first electrode and the second electrode is indium tin oxide.
6. A display backplane according to claim 1, wherein the storage capacitor is arranged between the buffer layer of the display backplane and the anode of the pixel structure, and wherein at least one insulating layer is arranged between the first electrode and the second electrode.
7. The display backplane of claim 6, further comprising:
a planarization layer disposed on a surface of the first electrode remote from the substrate base plate;
a pixel structure including an anode, the pixel structure disposed on a side of the planarization layer away from the substrate base,
wherein the second electrode is arranged on the surface of the planarization layer far away from the substrate base plate, and the second electrode is connected with the anode.
8. The display backplane of claim 7, further comprising:
a source electrode of the third thin film transistor is connected with a power bus of the display back plate, and a drain electrode of the third thin film transistor is connected with the second electrode and the anode;
the light shielding layer is arranged on part of the surface of the substrate, the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the active layer of the third thin film transistor on the substrate, and the light shielding layer is connected with the source electrode or the drain electrode of the third thin film transistor in the display back plate through a third through hole in the active layer.
9. A display backplane according to claim 7, comprising a first thin film transistor, a second thin film transistor and a third thin film transistor,
the grid electrode of the first thin film transistor is connected with a first scanning line of the display back plate, the source electrode of the first thin film transistor is connected with a data line of the display back plate, and the drain electrode of the first thin film transistor is connected with the first electrode and the grid electrode of the third thin film transistor;
the grid electrode of the second thin film transistor is connected with a second scanning line of the display back plate, the source electrode of the second thin film transistor is connected with the second electrode, the drain electrode of the third thin film transistor and the anode of the pixel structure in the display back plate, and the drain electrode of the second thin film transistor is connected with a reference voltage signal line of the display back plate;
and the source electrode of the third thin film transistor is connected with a power bus of the display backboard.
10. The display backplane of claim 9, wherein the planarization layer has a first via through which the second electrode is connected to a drain of a third thin film transistor in the display backplane.
11. A display device comprising the display back sheet according to any one of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921941293.8U CN210429813U (en) | 2019-11-11 | 2019-11-11 | Display back plate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921941293.8U CN210429813U (en) | 2019-11-11 | 2019-11-11 | Display back plate and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210429813U true CN210429813U (en) | 2020-04-28 |
Family
ID=70369516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921941293.8U Active CN210429813U (en) | 2019-11-11 | 2019-11-11 | Display back plate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210429813U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021093681A1 (en) * | 2019-11-11 | 2021-05-20 | 京东方科技集团股份有限公司 | Display backplane, manufacturing method therefor, and display device |
-
2019
- 2019-11-11 CN CN201921941293.8U patent/CN210429813U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021093681A1 (en) * | 2019-11-11 | 2021-05-20 | 京东方科技集团股份有限公司 | Display backplane, manufacturing method therefor, and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109103231B (en) | Display substrate, manufacturing method thereof and display device | |
| EP3792976B1 (en) | Display substrate and manufacturing method therefor, and display device | |
| CN110610980B (en) | Display substrate, preparation method thereof and display device | |
| WO2021093681A1 (en) | Display backplane, manufacturing method therefor, and display device | |
| US20210141304A1 (en) | Mask strips, array substrates and display screens | |
| US10923543B1 (en) | Display panel and method of forming the same, display device | |
| US20210305336A1 (en) | Display panel | |
| US10504981B2 (en) | Array substrate with touch electrode lead arranged at top position, OLED display panel, methods of manufacturing the same, and display device | |
| CN109786434B (en) | Array substrate, preparation method thereof, display panel, device and pixel driving circuit | |
| EP4053904B1 (en) | Display substrate and manufacturing method therefor, and display device | |
| US20220376007A1 (en) | Display substrate, method for forming the same and display device | |
| CN108364993B (en) | Display panel manufacturing method, display panel and display device | |
| JP2021502579A (en) | Display panel and its manufacturing method, and display module | |
| CN109037285B (en) | Display panel and manufacturing method thereof, display device and mask assembly | |
| CN111816686B (en) | Display substrate, manufacturing method thereof and display panel | |
| JP2022539621A (en) | Display panel, manufacturing method thereof, and display device | |
| US20220293692A1 (en) | Array substrate, method for manufacturing the same, display panel and display device | |
| WO2021083226A1 (en) | Display substrate and manufacturing method therefor, and display device | |
| CN113196494B (en) | Display substrate, preparation method thereof and display device | |
| CN110416274B (en) | Substrate, preparation method thereof and OLED display panel | |
| US20220102472A1 (en) | Display panel and method for manufacturing same, and display apparatus | |
| US11494019B2 (en) | Touch display device, touch display panel and manufacturing method thereof | |
| CN210429813U (en) | Display back plate and display device | |
| CN111584586B (en) | Back film, display substrate and display device | |
| EP4131378A1 (en) | Display substrate and manufacturing method therefor, and display apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |