CN210429794U - Semiconductor module and packaging structure - Google Patents
Semiconductor module and packaging structure Download PDFInfo
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- CN210429794U CN210429794U CN201921540453.8U CN201921540453U CN210429794U CN 210429794 U CN210429794 U CN 210429794U CN 201921540453 U CN201921540453 U CN 201921540453U CN 210429794 U CN210429794 U CN 210429794U
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- semiconductor module
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- conductive sheet
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004806 packaging method and process Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims description 35
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 239000000919 ceramic Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 8
- 239000011888 foil Substances 0.000 claims description 5
- 238000000465 moulding Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000003466 welding Methods 0.000 description 21
- 238000005476 soldering Methods 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48455—Details of wedge bonds
- H01L2224/48456—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model relates to the field of semiconductor technology, concretely relates to semiconductor module and packaging structure, include: chip and base plate, the chip set up in on the base plate, just the chip pass through conductive thin slice with pin electric connection on the base plate, the utility model discloses a conductive thin slice compares in prior art single wire, has increased area of contact to strengthened the circulation ability of electric current, effectively strengthened the heat dissipation, improved current efficiency, reduce power loss, improve the reliability, produced great parasitic coefficient when also avoiding using many wires, simultaneously, need not at chip surface routing, reduces the damage to the chip, thereby simplifies the process steps, finally improves production efficiency.
Description
Technical Field
The utility model relates to the field of semiconductor technology, concretely relates to semiconductor module and packaging structure.
Background
The power devices in the power supply products generally have few electrical pins, but need to pass large current. Most of the existing electrical connection methods in power chip packaging adopt a lead bonding mode to connect metal wires such as aluminum wires, copper wires or gold wires and the like to a metallization layer on the surface of a chip and substrate pins so as to realize electrical interconnection between the metallization layer and the substrate pins.
However, wire bonding processes are limited by the process capabilities themselves, such as: the diameter of the gold wire and the copper wire is only 50um at most, the through-current capacity of a single gold wire is limited, and the gold wire and the copper wire can be blown by overlarge current, so that the power device needs to use a plurality of gold wires or copper wires for interconnection to realize the high-current passing capacity, and the plurality of gold wires or copper wires can generate larger parasitic parameters, thereby reducing the power efficiency and increasing the power loss.
SUMMERY OF THE UTILITY MODEL
In order to overcome the defects of the prior art, the utility model provides a semiconductor module and packaging structure can increase area of contact, and the circulation ability of reinforcing electric current improves current efficiency, lowers the power loss.
Technical scheme (I)
In order to realize the technical problem, the utility model provides a semiconductor module and packaging structure, include: the chip is arranged on the substrate and is electrically connected with the pins on the substrate through the conductive sheets.
Optionally, two ends of the conductive sheet are provided with two welding terminals, and at least one through hole is formed in each welding terminal.
Optionally, one end of the conductive sheet is soldered to the metallization layer on the chip surface through one of the solder terminals, and the other end of the conductive sheet is soldered to the pin of the substrate through the other solder terminal.
Optionally, the number of the chips is at least two, and the at least two chips are electrically connected through the conductive sheet.
Optionally, the substrate includes: the heat sink comprises a lead frame, a ceramic substrate and a heat sink, wherein the ceramic substrate is arranged between the lead frame and the heat sink.
Optionally, the chip is electrically connected to the lead of the lead frame through a conductive sheet.
Optionally, the pin includes: the chip comprises a grid pin and an emitter pin, wherein the emitter of the chip is electrically connected with the emitter pin through a conductive sheet, and the grid of the chip is electrically connected with the grid pin through the conductive sheet.
Optionally, the lead frame is connected to the pins by a conductive sheet.
Optionally, the conductive sheet, the lead frame and the heat sink are all made of copper materials.
Optionally, the semiconductor module and the plastic package layer are encapsulated outside the semiconductor module.
(II) advantageous effects
Compared with the prior art, the utility model, following beneficial effect has:
the utility model provides a semiconductor module and packaging structure, include: chip and base plate, the chip set up in on the base plate, just the chip pass through conductive thin slice with pin electric connection on the base plate, the utility model discloses a conductive thin slice compares in prior art single wire, has increased area of contact to strengthened the circulation ability of electric current, effectively strengthened the heat dissipation, improved current efficiency, reduce power loss, improve the reliability, produced great parasitic coefficient when also avoiding using many wires, simultaneously, need not at chip surface routing, reduces the damage to the chip, thereby simplifies the process steps, finally improves production efficiency.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained without inventive exercise, wherein:
fig. 1 is a schematic structural diagram of an embodiment of a semiconductor module according to the present invention;
fig. 2 is a schematic structural diagram of another embodiment of a semiconductor module according to the present invention;
FIG. 3 is an enlarged view of a portion of FIG. 1 at position A;
FIG. 4 is a schematic view of a solder terminal;
fig. 5 is a flowchart of an embodiment of a method for soldering a semiconductor module according to the present invention;
fig. 6 is a flowchart illustrating another embodiment of a method for soldering a semiconductor module according to the present invention.
In the figure: 1. a chip; 2. a substrate; 3. a pin; 4. welding a terminal; 5. a lead frame; 6. a ceramic substrate; 7. a heat sink; 8. a through hole; 9. a thin sheet welding layer; 10. a chip solder layer; 11. a conductive sheet.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The invention will be described in further detail with reference to the following drawings and embodiments:
fig. 1 is a schematic structural diagram of an embodiment of the present invention;
FIG. 3 is an enlarged view of a portion of FIG. 1 at position A;
fig. 4 is a schematic structural view of the solder terminal 4;
as shown in fig. 1, 3 and 4, an embodiment of the first aspect of the present application provides a semiconductor module, including: the chip comprises a chip 1 and a substrate 2, wherein the chip 1 is arranged on the substrate 2, preferably, the chip 1 is welded through a chip welding layer 10, the chip welding layer 10 can adopt tin paste or silver paste and the like, similar welding materials can be adopted, and in the application, the substrate 2 preferably selects a ceramic-based substrate 2(DBC substrate 2); the chip 1 is electrically connected to the pins 3 on the substrate 2 through the conductive sheet 11, preferably, the sheet solder layer 9 is used for welding, wherein the conductive sheet 11 is preferably a conductive copper sheet, and certainly, a conductive aluminum sheet may also be used, as long as the material applicable to the present application is within the protection scope of the present application.
The utility model discloses a conducting sheet 11 has increased area of contact compared in single wire among the prior art to strengthened the circulation ability of electric current, effectively strengthened the heat dissipation, improved current efficiency, reduce power loss, improve the reliability, produced great parasitic coefficient when also avoiding using many wires, simultaneously, need not at 1 surperficial routing of chip, reduce the damage to chip 1, thereby simplify the process steps, finally improve production efficiency.
According to the utility model discloses an embodiment, the both ends of conductive sheet 11 set up to two welding terminal 4, have all seted up at least one through-hole 8 on two welding terminal 4, and the effect of setting up through-hole 8 is that can flow to the opposite side via through-hole 8 in order to guarantee the solder, realizes the welding, and the quantity of through-hole 8 can be adjusted according to production needs, and in this scheme, through-hole 8 sets up to 9, becomes the matrix arrangement on every welding terminal 4.
According to the utility model discloses an embodiment, the one end of conductive sheet 11 is welded on the metallization layer on chip 1 surface through one of them welding terminal 4, and the other end passes through another welding terminal 4, welds on pin 3 of base plate 2 to the realization replaces the wire among the prior art with conductive sheet 11 and carries out electric connection, and in this embodiment, in prior art, uses the wire to realize electric connection's place, and conductive sheet 11 that all can adopt this scheme replaces.
According to the utility model discloses a further embodiment, as shown in fig. 2, chip 1 sets up to at least two, among the prior art, carry out electric connection through the wire between at least two chips 1, nevertheless realize electric connection through conductive sheet 11 in this embodiment, area of contact has been increased, thereby the circulation ability of electric current has been strengthened, effectively strengthen the heat dissipation, improve current efficiency, reduce power loss, improve the reliability, produced great parasitic coefficient when also avoiding using many wires, and simultaneously, need not at 1 surperficial routing of chip, reduce the damage to chip 1, thereby simplify the process steps, finally, the production efficiency is improved.
According to an embodiment of the present invention, the substrate 2 includes: the lead frame comprises a lead frame 5, a ceramic substrate 6 and a heat sink 7, wherein the ceramic substrate 6 is arranged between the lead frame 5 and the heat sink 7, the lead frame 5 is used for bearing the chip 1, and the heat sink 7 is used for balancing stress borne by the ceramic substrate 6 and heat dissipation.
According to an embodiment of the present invention, the chip 1 is electrically connected to the pins 3 of the lead frame 5 through the conductive sheet 11.
Specifically, pin 3 includes: grid pin and emitter pin, the emitter of chip 1 passes through conductive sheet 11 and emitter pin electric connection, and the grid of chip 1 passes through conductive sheet 11 and grid pin electric connection, and wherein, pin 3 still includes: and the collector pin is used for being electrically connected with an external power supply when in work.
According to an embodiment of the invention, the lead frame 5 is connected with the pins 3 by means of conductive foils 11.
Preferably, the conductive sheet 11, the lead frame 5 and the heat sink 7 are made of copper.
An embodiment of a second aspect of the present application provides a package structure, including: as mentioned above, the semiconductor module and the molding compound encapsulated outside the semiconductor module are preferably provided as epoxy resin, and the molding compound is used to protect the semiconductor module.
Fig. 5 is a flowchart of a method for soldering a semiconductor module according to the present invention.
As shown in fig. 5, an embodiment of the third aspect of the present application provides a method for soldering a semiconductor module, including:
s101: preparing a conductive sheet 11, a chip 1 and a substrate 2;
s102: welding the chip 1 on the substrate 2;
s103: one end of the conductive sheet 11 is soldered to the metallization layer on the surface of the chip 1, and the other end is soldered to the lead 3 of the substrate 2.
The utility model discloses a conducting sheet 11 has increased area of contact compared in single wire among the prior art to strengthened the circulation ability of electric current, effectively strengthened the heat dissipation, improved current efficiency, reduce power loss, improve the reliability, produced great parasitic coefficient when also avoiding using many wires, simultaneously, need not at 1 surperficial routing of chip, reduce the damage to chip 1, thereby simplify the process steps, finally improve production efficiency.
According to an embodiment of the present invention, a conductive sheet 11 is prepared, including:
at least one through hole 8 is formed in each of the welding terminals 4 arranged at the two ends of the conductive sheet 11;
solder is applied to both the solder terminals 4.
The through holes 8 are arranged to ensure that solder can flow to the other side through the through holes 8 to realize welding, the number of the through holes 8 can be adjusted according to production requirements, and in the scheme, the number of the through holes 8 is 9, and the through holes are arranged on each welding terminal 4 in a matrix.
According to another embodiment of the present invention, as shown in fig. 6, S201: if the number of the chips 1 is at least two, the at least two chips 1 are electrically connected through the conductive sheet 11.
According to an embodiment of the present invention, a substrate 2 is prepared, including:
the lead frame 5 and the heat sink 7 are provided at both ends of the ceramic substrate 6.
The lead frame 5 and the heat sink 7 are preferably made of copper, the lead frame 5 is used for bearing the chip 1, and the heat sink 7 is used for balancing stress borne by the ceramic substrate 6 and heat dissipation;
the number of the lead frames 5 corresponds to the number of the chips 1 one by one, that is, as long as how many chips 1 need to be mounted, that is, as many lead frames 5 are arranged, and the distance between two adjacent lead frames 5 is preset according to the production requirement.
According to the utility model discloses an embodiment, weld chip 1 on base plate 2, include:
the chip 1 is soldered to the lead frame 5.
According to the utility model discloses an embodiment, the one end of conductive thin slice 11 welds on the metallization layer on chip 1 surface, and the other end welds on pin 3 of base plate 2, include:
one end of the conductive sheet 11 is soldered to the metallization layer on the surface of the chip 1 via one of the solder terminals 4, and the other end is soldered to the lead 3 of the lead frame 5 via the other solder terminal 4.
When there are two chips 1 to be assembled, the process is as follows:
firstly, two lead frames 5 and a heat sink 7 are arranged at two ends of a ceramic substrate 6 to complete the assembly of the substrate 2;
the arrangement positions and the distances of the two lead frames 5 can be preset according to production requirements;
welding two chips 1 on a lead frame 5 through chip welding layers 10 respectively;
the corresponding chip 1 and the corresponding pin 3 are welded together through the corresponding conductive sheet 11, and the specific welding process is as follows:
placing the soldering terminal 4 on the conductive sheet 11 at a position where soldering is desired, and then applying solder on the soldering terminal 4, the solder flowing down via the through-hole 8, thereby effecting soldering;
finally, the two chips 1 to be connected are electrically connected by the conductive sheet 11.
The embodiments in the present description are all described in a progressive manner, and some of the embodiments are mainly described as different from other embodiments, and the same and similar parts among the embodiments can be referred to each other.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying importance; the words "bottom" and "top", "inner" and "outer" refer to directions toward and away from, respectively, a particular component geometry.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the communication may be direct, indirect via an intermediate medium, or internal to both elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The above description is only for the preferred embodiment of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (10)
1. A semiconductor module, comprising: the chip comprises a chip (1) and a substrate (2), wherein the chip (1) is arranged on the substrate (2), and the chip (1) is electrically connected with pins (3) on the substrate (2) through conductive sheets (11).
2. A semiconductor module according to claim 1, wherein two ends of the conductive sheet (11) are provided as two bonding terminals (4), and at least one through hole (8) is formed in each of the two bonding terminals (4).
3. A semiconductor module according to claim 2, characterized in that one end of the conductive sheet (11) is soldered to the metallization layer on the surface of the chip (1) via one of the solder terminals (4), and the other end is soldered to the lead (3) of the substrate (2) via the other solder terminal (4).
4. A semiconductor module according to claim 1, characterized in that said chips (1) are arranged in at least two, at least two of said chips (1) being electrically connected to each other by said conductive foil (11).
5. A semiconductor module according to claim 1, characterized in that the substrate (2) comprises: lead frame (5), ceramic substrate (6) and fin (7), ceramic substrate (6) set up lead frame (5) with fin (7) between.
6. A semiconductor module as claimed in claim 5, characterized in that the chip (1) is electrically connected to the leads (3) of the lead frame (5) by means of electrically conductive foils (11).
7. A semiconductor module according to claim 6, characterized in that the pin (3) comprises: the chip comprises a grid pin and an emitter pin, wherein the emitter of the chip (1) is electrically connected with the emitter pin through a conductive sheet (11), and the grid of the chip (1) is electrically connected with the grid pin through the conductive sheet (11).
8. A semiconductor module as claimed in claim 5, characterized in that the lead frame (5) is connected to the leads (3) by means of a conductive foil (11).
9. A semiconductor module as claimed in claim 5, characterized in that the electrically conductive foil (11), the lead frame (5) and the heat sink (7) are made of copper.
10. A package structure, comprising: a semiconductor module as claimed in any one of claims 1 to 9 and a molding layer encapsulated outside the semiconductor module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921540453.8U CN210429794U (en) | 2019-09-16 | 2019-09-16 | Semiconductor module and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921540453.8U CN210429794U (en) | 2019-09-16 | 2019-09-16 | Semiconductor module and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210429794U true CN210429794U (en) | 2020-04-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921540453.8U Active CN210429794U (en) | 2019-09-16 | 2019-09-16 | Semiconductor module and packaging structure |
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| Country | Link |
|---|---|
| CN (1) | CN210429794U (en) |
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2019
- 2019-09-16 CN CN201921540453.8U patent/CN210429794U/en active Active
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