CN210403725U

CN210403725U - Light emitting diode packaging assembly

Info

Publication number: CN210403725U
Application number: CN201921553485.1U
Authority: CN
Inventors: 廖燕秋; 时军朋; 辛舒宁; 林振端; 余长治; 徐宸科; 廖启维; 吴政; 李佳恩
Original assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Current assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2020-04-24
Anticipated expiration: 2029-09-18

Abstract

The utility model provides a light emitting diode encapsulation subassembly, in some embodiments, this LED encapsulation subassembly contains: with N_X×N_YN light emitting cells arranged in a matrix, wherein N_X，N_YIs an integer and N_X≥N_YN is more than or equal to 3, each light-emitting unit comprises a LED chips, and each LED chip comprises a first electrode positioned on the same sideAnd a second electrode; the packaging layer is used for filling gaps among the LED chips and covering the side walls of the LED chips; the wiring layer is formed on the second surfaces of the LED chips and electrically connects the light-emitting units to form an N-in-one light-emitting module; and pads formed on the wiring layer, wherein the number of pads P = Nx + Ny × a.

Description

Light emitting diode packaging assembly

Technical Field

The present invention relates to a package assembly, and more particularly to a light emitting diode package assembly.

Background

Light Emitting Diodes (LEDs) are one of the hottest light source technologies today, and are used as light sources for illumination apparatuses, but also for various electronic products, such as widely used as light sources for various display devices, such as TVs, cellular phones, PCs, notebook PCs, Personal Digital Assistants (PDAs), and the like. The display resolution can be improved by reducing the size of the LED device, so that the application field of an LED display screen is expanded, such as a mobile phone, a vehicle-mounted panel, a television, a computer, a video conference and the like. The mainstream display screen at present adopts package sizes 2121 and 1010, and with the development of technology, 0808 or smaller package sizes appear on the market.

SUMMERY OF THE UTILITY MODEL

The utility model provides a Light Emitting Diode (LED) encapsulation subassembly of super small interval, this LED encapsulation subassembly contain a plurality of pixel area PX with Nx Ny matrix arrangement. Each pixel area PX may be referred to as a pixel.

In some embodiments, the LED package assembly comprises: the LED light source comprises N light-emitting units arranged in an Nx Ny matrix, wherein Nx and Ny are integers, Nx is larger than or equal to Ny, N is larger than or equal to 3, each light-emitting unit comprises a LED chips, and each LED chip comprises a first electrode and a second electrode which are positioned on the same side; the packaging layer is used for filling gaps among the LED chips and covering the side walls of the LED chips; the wiring layer is formed on the second surfaces of the LED chips and electrically connects the light-emitting units to form an N-in-one light-emitting module; and pads formed on the wiring layer, wherein the number of pads P = Nx + Ny × a. Through such design, can reduce the pad quantity of encapsulation subassembly as far as, conveniently lay wire on the one hand, on the other hand does benefit to the paster of application end, reduces the risk of short circuit.

Preferably, the N light emitting cells are arranged in Nx rows and Ny columns, and the number P of pads is guaranteed to be the minimum.

In some embodiments, the a LED chips of the respective light emitting units are arranged in a row in a first direction Nx, and the first and second electrodes of each LED chip are arranged side by side in a second direction Ny.

In some embodiments, N is 2^2×kAt this time, Nx: ny = 4: 1, wherein k is a natural number.

In some embodiments, said N is 3^2×k+1Then Nx: ny = 3: 1, wherein k is an integer greater than or equal to zero.

Preferably, the distance D1 between adjacent light emitting units is preferably 0.8mm or less, where N may be an integer of 4 or more, such as 4, 6, 8, 9, 16, 32, or 64, and the larger the value of N, the smaller the value of D1, such as when N is 4 to 9, D1 may be 0.4 to 0.8, and when N is 8 or more, D may be 0.1 to 0.4.

In some embodiments, the first wiring layer electrically connects the first electrodes of the same type of LED chips located in the same row from the first direction, and electrically connects the second electrodes of the LED chips located in the same column from the second direction Ny.

In some embodiments, the wiring layers include a first wiring layer formed on the second surfaces of the LED chips to connect the first and second electrodes of the LED chips, a via layer formed on the first wiring layer to be electrically connected to the first wiring layer, and a second wiring layer formed on the via layer to be electrically connected to the via layer. Preferably, the thickness of the through hole layer is 20-80 μm.

Preferably, the total thickness of the packaging assembly is 100-500 mu m. In some embodiments, the total thickness of the package assembly is between 120-200 μm. In some embodiments, the total thickness of the package assembly is between 320 and 500 μm.

Preferably, the wiring layer includes a plurality of conductive traces electrically isolated from each other, and the number of the conductive traces is four or less. In some embodiments, at least one layer of the plurality of conductive traces has a thickness of 50 μm or less. In some embodiments, at least one layer of the plurality of conductive traces has a thickness of 60 μm or more.

The utility model has the advantages that: the utility model discloses a packaging form of no base plate, by the fixed LED chip of a plurality of luminescence units of packaging layer, and form the LED chip of this a plurality of luminescence units of multilayer wiring layer series-parallel connection at the back of this multilayer luminescence unit, wherein first wiring layer carries out the LED chip of a plurality of pixel regions in series, parallelly connected, and see through pore layer and second wiring layer, rewire, form the slim booth apart from emitting diode encapsulation subassembly of integrated form, secondly through reasonable wiring layer design, can reduce the quantity of the external pad of encapsulation subassembly on the one hand, thereby the paster degree of difficulty of application end has been reduced, the reliability of product has been improved simultaneously; and moreover, the number of layers of the wiring layers is not more than four, so that the light and thin thickness of the product can be ensured, and the light and thin terminal product is facilitated.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which:

fig. 1 is a perspective view illustrating the structure of a Light Emitting Diode (LED) package assembly of the present invention;

fig. 2 is a schematic top view illustrating the arrangement of the LED chips of the LED package assembly according to an embodiment of the present invention;

fig. 3 is a schematic side cross-sectional view illustrating that the LED chip of the LED package assembly of the embodiment is a conventional LED chip;

fig. 4 is a schematic side cross-sectional view illustrating the structure of a LED package assembly according to an embodiment of the present invention;

fig. 5 is a schematic top view illustrating the first wiring layer of the LED package assembly of the embodiment;

fig. 6 is a schematic top view illustrating the via layer of the led package assembly of the present invention;

fig. 7 is a schematic top view illustrating a second wiring layer of the LED package assembly of the embodiment;

fig. 8 is a circuit connection diagram illustrating circuit connections of the LED package assembly of the embodiment;

fig. 9 is a schematic top view illustrating the arrangement of the LED chips of the LED package assembly according to an embodiment of the present invention;

fig. 10 is a circuit connection diagram illustrating circuit connections of the LED package assembly of the embodiment.

Detailed Description

Before the present invention is described in detail, it should be noted that in the following description, similar components are denoted by the same reference numerals.

The following embodiments disclose an N-up LED package assembly, comprising: n light-emitting units are arranged in an Nx Ny matrix, wherein N is larger than or equal to 3, Nx, Ny are integers, Nx is larger than or equal to Ny, a packaging layer fills gaps among the light-emitting units, and a wiring layer is located below the packaging layer and connected with the light-emitting units, so that LED chips in a multi-point pixel area PX are connected in series and in parallel to form an N-in-one pixel area. For example, in an RGB display, each of the light emitting units may include 3 LED chips 100, each of which typically includes a first electrode and a second electrode on the same side, such as a horizontal type LED chip or a flip type LED chip, as shown in fig. 3. The number of horizontal pixel points is Nx, and the number of vertical pixel points is Ny, that is, Ny rows and Ny columns are arranged. Preferably, N is an integral multiple of a natural number below 5, Nx is greater than or equal to 3, and 1 is greater than or equal to Nx/Ny is less than or equal to 5, the ratio of Nx to Ny is maintained in the range, the packaging assembly with the minimum number of pads is easy to realize through the wiring layer design, a better length-width ratio is kept, and the subsequent application end can conveniently carry out the chip mounting.

In one embodiment, N =2^2×kFor example, 4-in-one, 16-in-one or 64-in-one may be used, and the ratio of Nx to Ny is preferably 4: 1 arranging the LED chips in this way, in conjunction with the wiring layer, a minimum number of pads can be implemented. Fig. 1-2 disclose a four-in-one LED package assembly, which includes 4 light emitting units arranged in a 4 × 1 matrix, each light emitting unit includes a plurality of LED chips with different wavelengths, preferably, at least three LED chips respectively emit red light (R), green light (G), and blue light (B), and may further include an LED chip (including a wavelength conversion layer) emitting white light, that is, an RGBW combination is formed, so that the brightness of a display screen can be improved, which is very beneficial for outdoor display.

Each light emitting unit corresponds to one pixel area PX and may also be referred to as a pixel. Referring to fig. 4, which is a cross-sectional view taken along line a-a of fig. 2, each pixel area PX has a plurality of LED chips 100 spaced apart from each other and having a light emitting surface S21, the package assembly further includes a package layer 200 fixed to and filling gaps between the plurality of LED chips, and a plurality of wiring layers 310 to 330 covering the package layer 200. The multi-layer wiring layer includes a first wiring layer 310, a via layer 320, and a second wiring layer 330, each of which is electrically isolated from the other by an insulating layer 500. Wherein a first wiring layer 310 is formed on the lower surfaces of the plurality of LED chips to connect the plurality of LED chips in parallel and/or in series, and the via layer 320 is formed on the first wiring layer to be electrically connected to the first wiring layer 310; a second wiring layer 330 is formed over the via layer and is electrically connected to the via layer 320.

Referring to fig. 3, in order to illustrate one of the LED chips 100L 1-100L 3, each of the LED chips 100L 1-100L 3 has a pair of LED chips located at the same sideThe electrode 110 has a first surface S21, a second surface S22 and a side surface S24 connected between the first surface S21 and the second surface S22. The first surface S21 is a light emitting surface S21, and the pair of electrodes 110 is disposed on the second surface S22. Further, the LED chip includes a substrate 101, a first type semiconductor layer 121, a light emitting layer 122, and a second type semiconductor layer 123. The first type semiconductor layer 121 and the second type semiconductor layer 123 may be a p-type semiconductor layer and an n-type semiconductor layer, respectively. The electrode group 110 of the LED chip includes a first electrode 111 electrically connected to the first type semiconductor layer 121, and a second electrode 112 electrically connected to the second type semiconductor layer 123. In other embodiments, the electrode assembly 110 of each LED chip further includes two thickened layers of conductive material. The thickening layers are respectively disposed between the first electrode 111 and the first wiring layer and between the second electrode 112 and the first wiring layer 310, and can be formed by electroplating, chemical plating or printing, and the material can be Cu, Cu_xW or other conductive metallic material. By increasing the thickness of the electrode, the area of the side S24 of the LED chip in contact with the encapsulation layer 200 can be increased, thereby increasing the adhesion between the LED chip and the encapsulation layer 200. Preferably, the thickness of the electrode set of each LED chip is 5 to 500 μm, such as 30 μm to 100 μm, 30 μm to 50 μm, or 80 μm to 120 μm, which is selected according to specific requirements. The LED chip 1100 may be an LED chip with a conventional size (generally, the single-side size of the chip exceeds 200 μm), or a Mini LED chip (generally, the chip size is between 100 μm and 200 μm), or a Micro LED chip (generally, the chip size does not exceed 100 μm), and a Mini LED chip or a Micro LED chip is preferred in this embodiment.

Referring to fig. 4, the first packaging layer 200 is filled around the first, second and third LED chips 100L 1-L3, and preferably, the light transmittance of the packaging layer 200 is less than 30%; more preferably, the light transmittance of the encapsulation layer 200 is 5% to 20%; optionally, the encapsulation layer 200 is opaque and opaque, and specifically includes a light absorbing component (not shown) disposed at least around a sidewall of the LED chip or between adjacent LED chips, or further at least around the LED semiconductor light emitting stack or around adjacent semiconductor light emitting stacks. The light absorbing component may be light absorbing particles dispersed in epoxy resin or silicone used for the encapsulation layer, such as black particles and carbon powder, or the light absorbing component may be black resin. The light absorption components of the packaging layer 200 are arranged at least around the side wall of the LED to prevent the side surface of the LED chip from emitting light, so that the light emitted from the LED chip is mainly concentrated on the light emitting surface or is completely concentrated on the light emitting surface, and the phenomenon of light crosstalk or light mixing of light among different LED chips in the side surface direction is reduced. In one embodiment, the package layer 200 may be epoxy resin or silicone rubber with a black colorant added thereto, so that the light emitting surface S21 of the LED chip 100 is black in the remaining area of the whole LED package assembly, which is helpful for improving the contrast of the display panel, and the LED chips 100 are isolated from each other by the black package material, which can reduce the optical interference between the LED chips. In some embodiments, the hardness of the encapsulation layer 200 is preferably above D60, and more preferably above D85.

Further, a transparent or translucent material layer is formed on the packaging layer 200 as another packaging layer 400, covering the first surfaces S21 of the first, second and third LED chips, so as to avoid the LED chips from being exposed. The package layer 400 can be used as a light scattering lens to generate a light scattering effect, so that the vertigo feeling can be effectively reduced when the LED package assembly is applied to a display panel, and further the package layer 40 can include a light scattering material, such as scattering g particles. The thickness of the packaging layer 400 is preferably 5-20 μm, for example 10 μm, so that on one hand, the light-emitting surface of the LED chip can be protected, and on the other hand, optical interference between the LED chips can be reduced by using the packaging layer 200 made of a light-absorbing material. The light transmittance is preferably 40% or more. In some embodiments, the LED package assembly is applied to an indoor display, and the package layer 400 is preferably a translucent layer, and has a light transmittance of preferably 40% to 80%, and more preferably 70% to 80%, so as to reduce the brightness of the LED chip, thereby reducing the glare effect of light. In some embodiments, the encapsulation is applied to the extrapupillary display, in which case the encapsulation layer 400 is preferably a transparent layer with a light transmittance of preferably more than 80%, more preferably 80%.

In this embodiment, the first, second and third LED chips 100L 1-L3 may be temporarily adhered to a support such as an adhesive tape with the light emitting surface S21 of the LED chip 100 as a crystal fixing surface, with the electrode surface S24 facing upward, and then the package layer 200 is formed by filling a fluid insulating material between the chips and curing the fluid insulating material. In this embodiment, the thickness of the adhesive material of the adhesive tape is preferably controlled to be 5 to 20 μm, so that on one hand, the LED chips are ensured not to be displaced when the encapsulation layer is filled, and on the other hand, the first surfaces S21 of the first, second, and third LED chips 100L1 to L3 are ensured to be substantially located on the same horizontal plane, and the height difference is substantially kept below 10 μm, so that the encapsulation assembly is beneficial to unifying the light emitting surfaces and reducing the influence of optical crosstalk between the side walls when the pixel area is greatly increased.

Referring to fig. 2, the first, second and third chips LED-100L 1-100-L3 of PX in each pixel region of the package assembly are arranged in a line, specifically, the LED chips of each light emitting unit are arranged in a row according to a first direction Y, and the first and second electrodes of each LED chip are arranged in parallel according to a second direction X, wherein the first and second directions are substantially perpendicular to each other, which facilitates the wiring at the application end, thereby reducing the pitch between the chips. If each pixel region is regarded as a pixel, the dot pitch D1 of each pixel is preferably 1mm, more preferably less than 0.8mm, and may be, for example, 0.3 to 0.5, or 0.5 to 0.8. The distance D2 between the chips in the same pixel region PX is preferably less than 100 μm, such as 50-100 μm, or less than 50 μm, and in some display panel applications, the distance between the LED chips in the same pixel region is preferably less than 50 μm, such as 40-50 μm, or 30-40 μm, or 20-30 μm, or 10-20 μm. The smaller the spacing is, the more beneficial the size of the LED packaging assembly is to be reduced, thereby improving the resolution of the display panel. In other embodiments, N may be 16, 64, or other, and the distance D1 between the pixels may be less than 0.3mm, for example, 0.2mm, or 0.1 mm.

Referring to fig. 4, a plurality of wiring layers are formed on the second surfaces of the LED chips, and specifically include a first wiring layer 310, a via layer 320 and a second wiring layer 330, wherein the first wiring layer 310 is connected to the electrodes 110 of the LED chips, the via layer 320 is formed on the first wiring layer 310, and the second wiring layer 330 is formed on the via layer 320 and is electrically connected to the first wiring layer 310 through the via layer 320. The multilayer wiring layer is preferably made of a metal material with a melting point higher than 400 ℃, such as Ag, Cu, Ni, Al and the like, and the materials of the layers can be the same or different and can be formed by electroplating, chemical plating, printing or other processes. The thickness of each layer is preferably 100 μm or less. Specifically, the first wiring layer 310 is formed on the surface of the encapsulation layer 200 and electrically connected to the electrodes 110 of the LED chips. The insulating layer 510 is filled in the gap between the wires of the first wiring layer 310, and the surface of the first wiring layer 310 away from the LED chip is exposed. The material of the insulating layer 510 may be the same as or different from that of the encapsulation layer 200. When the same material is used, the insulating layer 510 and the package layer 200 are combined into a layer, which is difficult to distinguish. For example, in one embodiment, the LED package assembly is applied to a display device, and the insulating layer 510 and the package layer 200 are both epoxy resin or silicone gel with a colorant added. Specifically, the insulating layer 510 and the encapsulation layer 200 are both epoxy resin or silicone gel with a colorant added. In some embodiments, the hardness of the insulating layer 510 is not lower than the hardness of the first wiring layer 310, for example, D60 or more, preferably D85 or more, so as to facilitate the polishing process to expose the surface S310 of the first wiring layer 310.

Referring to fig. 5 to 7, there are shown patterns of a first wiring layer, a via layer and a second wiring layer in an embodiment, in which the first wiring layer 310 includes common lines 314a to d respectively connecting second electrodes of first, second and third LED chips located in the same column in parallel, and further includes first lines 311a to 313a, in which 311a is connected to a first electrode of the first LED chip 100-L1, 312a is connected to a first electrode of the second LED chip 100-L2, and 313a is connected to a first electrode of the third LED chip 100-L3. The via layer 320 is located on the surface S310 of the first wiring layer 310, and a series of vias 321a to 323a, 324a to 324d are formed in an insulating layer 520, where the number and positions of the vias correspond to the respective wirings of the first wiring layer, and the solid-oblique line filling pattern in fig. 6 is a via. Wherein the material of the insulating layer 520 may be referenced to the insulating layer 510. The thickness of the via layer is usually less than 100 μm, and in some embodiments, the package assembly is a thin structure, and the via layer is preferably 20 to 50 μm, for example, 25 to 30 μm, so that excessive stress and thermal resistance of the via layer can be avoided, and the total thickness of the package structure is reduced while the strength of the package structure is ensured, and finally, the application product is thinner. In other embodiments, the via layer has a thickness of 50-80 μm, such as 60 μm, to increase the thickness of the package assembly appropriately to facilitate pickup from the sidewalls of the device. The second wiring layer 330 is located on the via layer 320 and electrically connected to the first wiring layer 310 through each via of the via layer 320, and includes a connection line 331-333 and connection portions 331 a-333 a, 334 a-334 d, wherein the connection line 331 connects the first electrodes of the first LED chips located in the same row, the connection line 332 connects the first electrodes of the second LED chips located in the same row, the connection line 333 connects the first electrodes of the third LED chips located in the same row, and the series of connection portions can be used as electrode pads of a package assembly for connecting a power supply. In a preferred embodiment, a pad may be formed in a region corresponding to the connection portion, and an area outside the pad may be covered with ink, epoxy resin, or other insulating material to protect the lines of the second wiring layer. The gaps between the lines of the third wiring layer 330 are filled with an insulating layer 530, and the surface of the second wiring layer 330 away from the LED chip is exposed, and the material of the insulating layer 530 can be designed with reference to the insulating layer 510. In one embodiment, the connection portion of the second wiring layer 330 completely covers each via of the via layer 320, so that the contact area between the second wiring layer and the via is increased, and meanwhile, in the process flow, the via layer and the second wiring layer can form a conductive material in the same process, so that a process of forming the conductive material and grinding is omitted, the cost can be effectively saved, and the product stability is improved.

The insulating layers 510-530 can be made of the same material or different materials, and the specific material can be epoxy resin, silica gel, polyimide, benzocyclobutene or PBO. When the insulating

layers

510 and 530 are made of the same material, they are combined into a layer 500, which is difficult to distinguish. In some embodiments, the insulating layers 510-530 are made of opaque or low-transmittance materials, such as epoxy or silicone doped with black colorant, to prevent or reduce light emitted from the LED chips from escaping from the redistribution layer and causing crosstalk. When a light-tight or low-light-transmission material is used as the insulating layer, a metal line pattern in the wiring layer can be formed first, then the insulating layer is refilled, and finally the surface of the metal line in the wiring layer is exposed in a grinding mode. In other embodiments, when the encapsulation layer 200 is made of a material with low light transmittance or without light transmittance, the insulating layers 510 to 530 may be partially or entirely made of a light-transmissive material, so that the light transmittance is higher than that of the encapsulation layer 200. The light-transmitting layer can be formed without adding coloring agent or light-absorbing material, such as carbon powder or dye, preferably a silica gel or epoxy resin material layer, and does not contain micron-sized particles (generally, particles with a diameter of more than 1 micron, such as C powder particles), so that the reliability of the insulating layer for covering the wiring layer can be ensured. In other embodiments, the light-sensitive material is cured to form the insulating layer, which simplifies the process, and the light-absorbing material is covered around the chip and the non-metal portion of the electrode surface as the packaging layer 200 to prevent the crosstalk of the light from the chip side.

Fig. 8 illustrates the circuit connection of the four-in-one light emitting unit. In this embodiment, first, on the LED chip arrangement, the LED chips in each PX are arranged in a "one" shape, specifically, the LED chips of each light emitting unit are arranged in a row according to a first direction Y, the first and second electrodes of each LED chip are arranged in parallel according to a second direction, wherein the first and second directions are substantially perpendicular, the wiring layer is connected in parallel to the first electrodes of the first, second and third LED chips in the same row from the first direction Y, and connected in parallel to the second electrodes of the first, second and third LED chips of two or more light emitting units in the same row from the second direction X, so as to electrically connect the plurality of light emitting units to form an all-in-one light emitting module. Unlike the package assembly in a 2 × 2 matrix arrangement, in the present embodiment, Nx/Ny is 4: 1, have preferred length, width ratio, make things convenient for the application end to carry out the paster to connect in parallel the first electrode of the LED chip of the same type from horizontal (X axle direction), can furthest reduce the quantity of external pad.

In other embodiments, N may be 16 or 64, etc., and when N is 16, Nx takes a value of 8, Ny is preferably 2, and the chip arrangement inside each light emitting unit may be as shown in fig. 2.

Referring again to fig. 4, the package assembly according to the above exemplary embodiment does not have a package substrate or a support for carrying the LED chip, the light emitting cells arranged in the Nx × Xy matrix are mainly fixed and supported by the insulating material layer (including 200, 400, and 500) and the wiring layer, and the thickness T of the package assembly is mainly determined by the thickness T of the LED chip_AAnd thickness T of wiring layer_C. In some embodiments, a mini-type LED chip is used, the chip thickness TA is between 40 and 150 μm, the thickness TC of the multi-layer wiring layer is between 20 and 200 μm, more preferably the thickness TC of the wiring layer is between 50 and 150 μm, and the T, TA satisfies the relation: T/TA is more than or equal to 1.4 and less than or equal to 10, so that overlarge stress and overlarge thermal resistance of the circuit layer can be avoided, and the total thickness of the packaging assembly is reduced while the strength of the packaging structure body is ensured. For example, in one embodiment, the thickness TA of the LED chip is about 80 μm, the package thickness can be 120 μm to 500 μm, such as 120 to 200 μm, and the sub-layer of each wiring layer can have a thickness of 20 to 50 μm, for example, 30 μm. For example, in another embodiment, when the package assembly has a small size (e.g., 0.4mm × 0.4mm or smaller), it is inconvenient to grab the package assembly from the upper surface of the package assembly, and the thickness T of the package assembly can be increased appropriately, so that the sidewall of the package assembly has a larger area for the grabbing device to contact and grab, and preferably, the thickness of the package assembly can be 320-500 μm, e.g., 340-360 μm, and the thickness of the package assembly can be increased by increasing the thickness of the LED chip and/or the thickness of the wiring layer, e.g., the thickness of the electrode of the LED chip can be increased, and the thickness of each wiring layer can be increased appropriately, and the thickness of the via is preferably 30-80 μm, and the thicknessThe thickness of (A) is preferably 50 to 100 μm. In some embodiments, a micro-type LED chip is adopted, the thickness TA of the chip is 5-10 μm, the thickness TC of the multilayer wiring layer is 20-200 μm, more preferably the thickness TC of the wiring layer is 50-150 μm, and the T, TA satisfies the relation: T/TA is more than or equal to 10 and less than or equal to 60, for example, the thickness of the package assembly can be 50-100 μm, or 100-200 μm.

Fig. 9-10 illustrate another embodiment of the LED package assembly of the present invention. Referring to FIGS. 9 and 10, the package assembly includes 8 pixel regions arranged in a 4 × 2 matrix, i.e., four columns Nx 1-Nx 4, N_Y1~N_Y2Two rows of light emitting units, routes 314 a-314 d of the wiring layer are connected with the second electrodes of all the LED chips in the same column from the first direction, for example, 314a is connected with the second electrodes of all the LED chips in Nx1 column, routes 331 a-333 a, 331 b-333 b of the wiring layer are connected with the first electrodes of the same type of LED chips in the same row, for example 331 is connected with the first electrodes of the same type of LED chips in Nth column_Y1The first LED chip of (1). In the present embodiment, by designing in this way, the number of pads P = Nx + Ny × 3, i.e., 10, of the package assembly, the minimum number of pads can be reached.

The utility model discloses LED encapsulation subassembly utilizes this packaging layer fixed and encapsulation to be the pixel of matrix arrangement to design multilayer wiring layer and establish ties the LED chip of each pixel. Therefore, the utility model discloses do not need the circuit board of bonding wire and accurate wiring, promoted reliability and contrast. In addition, the electrode group of the LED chip does not need to be soldered on the circuit board by solder paste, thereby avoiding the problem of poor soldering of the chip, improving the integration of the LED and the electronic component and really achieving the purpose of the utility model.

However, the above description is only an example of the present invention, and the scope of the present invention should not be limited thereby, and all the simple equivalent changes and modifications made according to the claims and the contents of the patent specification are still included in the scope of the present invention.

Claims

1. A light emitting diode package assembly, comprising:

the LED light source comprises N light-emitting units arranged in an Nx Ny matrix, wherein Nx and Ny are integers, Nx is larger than or equal to Ny, N is larger than or equal to 3, each light-emitting unit comprises a LED chips, and each LED chip comprises a first electrode and a second electrode which are positioned on the same side;

the packaging layer is used for filling gaps among the LED chips and covering the side walls of the LED chips;

the wiring layer is formed on the second surfaces of the LED chips and electrically connects the light-emitting units to form an N-in-one light-emitting module;

and pads formed on the wiring layer, wherein the number of pads P = Nx + Ny × a.

2. The light emitting diode package assembly of claim 1, wherein: the N light emitting cells are arranged in Nx rows and Ny columns such that the number P of pads is minimized.

3. The light emitting diode package assembly of claim 1, wherein: nx > Ny.

4. The light emitting diode package assembly of claim 1, wherein: the a LED chips of each light emitting unit are arranged in a row in a first direction Nx, and the first and second electrodes of each LED chip are arranged side by side in a second direction Ny.

5. The light emitting diode package assembly of claim 1, wherein: wherein 1 is less than or equal to N_x/N_y≤5。

6. The light emitting diode package assembly of claim 1, wherein: when the N is 2^2×kThen Nx: ny = 4: 1, wherein k is a natural number.

7. The light emitting diode package assembly of claim 1, wherein: when the N is 3^2×k+1Then Nx: ny = 3: 1, wherein k is an integer greater than or equal to zero.

8. The light emitting diode package assembly of claim 1, wherein: the pitch between adjacent light emitting cells is 0.8mm or less.

9. The light emitting diode package assembly of claim 1, wherein: the first wiring layer electrically connects the first electrodes of the same type of LED chips located in the same row from the first direction, and electrically connects the second electrodes of the LED chips located in the same column from the second direction Ny.

10. The light emitting diode package assembly of claim 1, wherein: the wiring layer comprises a first wiring layer, a through hole layer and a second wiring layer, wherein the first wiring layer is formed on the second surfaces of the LED chips and is connected with the first electrodes and the second electrodes of the LED chips, the through hole layer is formed on the first wiring layer and is electrically connected with the first wiring layer, and the second wiring layer is formed on the through hole layer and is electrically connected with the through hole layer.

11. The light emitting diode package assembly of claim 10, wherein: the thickness of the through hole layer is 20-80 mu m.

12. The light emitting diode package assembly of claim 1, wherein: the total thickness of the packaging assembly is 100-500 mu m.

13. The light emitting diode package assembly of claim 1, wherein: the total thickness of the packaging assembly is between 120 and 200 mu m or between 320 and 500 mu m.

14. The light emitting diode package assembly of claim 1, wherein: the wiring layer comprises a plurality of layers of conductive circuits which are electrically isolated from each other, and the number of the conductive circuits is less than four.

15. The light emitting diode package assembly of claim 14, wherein: at least one layer of the multilayer conductive circuit has a thickness of 50 μm or less.

16. The light emitting diode package assembly of claim 14, wherein: at least one layer of the multilayer conductive circuit has a thickness of 60 μm or more.