CN210403768U

CN210403768U - Light emitting diode packaging assembly

Info

Publication number: CN210403768U
Application number: CN201921554474.5U
Authority: CN
Inventors: 林振端; 廖燕秋; 时军朋; 辛舒宁; 余长治; 吴政; 徐宸科; 李佳恩; 廖启维; 曹爱华
Original assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Current assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2020-04-24
Anticipated expiration: 2029-09-18

Abstract

The utility model provides a light emitting diode encapsulation subassembly, in some embodiments, this LED encapsulation subassembly contains: the LED display device comprises a plurality of light-emitting units arranged in an m x n matrix, wherein m and n are integers, m x n is more than or equal to 4, and each light-emitting unit comprises a first LED chip, a second LED chip and a third LED chip; each LED chip comprises a first surface, a second surface, a side surface and an electrode group, wherein the first surface, the second surface, the side surface and the electrode group are opposite, the side surface is connected between the first surface and the second surface, the electrode group is formed on the second surface, the electrode group comprises a first electrode and a second electrode, and the first surface is a light-emitting surface; the packaging layer is used for filling gaps among the LED chips and covering the side walls of the LED chips; and the wiring layer is formed on the second surfaces of the LED chips.

Description

Light emitting diode packaging assembly

Technical Field

The present invention relates to a package assembly, and more particularly to a light emitting diode package assembly and a light emitting device including the same.

Background

Light Emitting Diodes (LEDs) are one of the hottest light source technologies today, and are used as light sources for illumination apparatuses, but also for various electronic products, such as widely used as light sources for various display devices, such as TVs, cellular phones, PCs, notebook PCs, Personal Digital Assistants (PDAs), and the like. The display resolution can be improved by reducing the size of the LED device, so that the application field of an LED display screen is expanded, such as a mobile phone, a vehicle-mounted panel, a television, a computer, a video conference and the like. The mainstream display screen at present adopts package sizes 2121 and 1010, and with the development of technology, 0808 or smaller package sizes appear on the market.

SUMMERY OF THE UTILITY MODEL

The utility model provides a Light Emitting Diode (LED) packaging subassembly of super small interval, this LED packaging subassembly contain a plurality of pixel region PXs with mxn matrix arrangement, wherein m and n are the integer that is greater than 1. Each pixel area PX may be referred to as a pixel.

In some embodiments, the LED package assembly comprises: the LED display device comprises a plurality of light-emitting units arranged in an m x n matrix, wherein m and n are integers, m x n is more than or equal to 4, and each light-emitting unit comprises a first LED chip, a second LED chip and a third LED chip; each LED chip comprises a first surface, a second surface, a side surface and an electrode group, wherein the first surface, the second surface, the side surface and the electrode group are opposite, the side surface is connected between the first surface and the second surface, the electrode group is formed on the second surface, the electrode group comprises a first electrode and a second electrode, and the first surface is a light-emitting surface; the packaging layer is used for filling gaps among the LED chips and covering the side walls of the LED chips; and the wiring layer is formed on the second surfaces of the LED chips.

In some embodiments, the LED chips of each light emitting unit are aligned in a first direction, and the first and second electrodes of each LED chip are juxtaposed in a second direction.

In some embodiments, the wiring layer connects the first electrodes of the first, second and third LED chips of two or more adjacent light emitting units in parallel from a third direction, which is the same as the first direction and the fourth direction, which is the same as the second direction, or the third direction, which is the same as the second direction, and the second electrodes of the first, second and third LED chips of two or more adjacent light emitting units in parallel from a fourth direction, which is the same as the first direction, to electrically connect the plurality of light emitting units to form an all-in-one light emitting module.

In some embodiments, the package assembly does not have a package substrate for carrying the LED chip, which is held in place by the package layer.

Further, the package assembly having the N-in-one light emitting module, wherein N = m × N, and a distance D1 between adjacent light emitting units is preferably 0.8mm or less, where N may be an integer of 4 or more, such as 4, 6, 8, 9, 16, 32, or 64, and the larger the value of N, the smaller the value of D1, such as 4 to 9, D1 may be 0.4 to 0.8, and when N is 8 or more, D may be 0.1 to 0.4.

In some embodiments, the package assembly further comprises pads for external connection, the number P of the pads is n + m × a, wherein a is the number of the LED chips of each light-emitting unit, and n is larger than or equal to m. Through such design, can reduce the pad quantity of encapsulation subassembly as far as, conveniently lay wire on the one hand, on the other hand does benefit to the paster of application end, reduces the risk of short circuit.

The utility model has the advantages that: the utility model discloses a packaging form of no base plate, by the fixed LED chip of a plurality of luminescence units of packaging layer, and form the LED chip of this a plurality of luminescence units of multilayer wiring layer series-parallel connection at the back of this multilayer luminescence unit, wherein first wiring layer carries out the LED chip of a plurality of pixel regions in series, parallelly connected, and see through pore layer and second wiring layer, rewire, form the slim booth apart from emitting diode encapsulation subassembly of integrated form, secondly through reasonable wiring layer design, can reduce the quantity of the external pad of encapsulation subassembly on the one hand, thereby the paster degree of difficulty of application end has been reduced, the reliability of product has been improved simultaneously; and moreover, the number of layers of the wiring layers is not more than four, so that the light and thin thickness of the product can be ensured, and the light and thin terminal product is facilitated.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which:

fig. 1 is a perspective view illustrating the structure of a Light Emitting Diode (LED) package assembly according to an embodiment of the present invention;

fig. 2 is a schematic side cross-sectional view illustrating the structure of an LED package assembly according to an embodiment of the present invention;

fig. 3 is a schematic top view illustrating the arrangement of the LED chips of the LED package assembly according to an embodiment of the present invention;

fig. 4 is a schematic side cross-sectional view illustrating that the LED chip of the LED package assembly of the embodiment is a conventional LED chip;

fig. 5 is a schematic side sectional view illustrating a die bonding manner of the LED chip of the LED package assembly according to the embodiment;

fig. 6 is a schematic side cross-sectional view illustrating the first wiring layer of the LED package assembly of the embodiment;

fig. 7 is a schematic top view illustrating the first wiring layer of the LED package assembly of the embodiment;

fig. 8 is a schematic side cross-sectional view illustrating a via layer of the LED package assembly of the embodiment;

fig. 9 is a schematic top view illustrating the via layer of the led package assembly of the present invention;

fig. 10 is a schematic side sectional view illustrating a second wiring layer of the LED package assembly of the embodiment;

fig. 11 is a schematic top view illustrating a second wiring layer of the LED package assembly of the embodiment;

fig. 12 is a schematic top view illustrating the first wiring layer, the via layer and the second wiring layer of the LED package assembly of the embodiment;

fig. 13 is a circuit diagram illustrating circuit connections of the LED package assembly of the embodiment;

fig. 14 is a schematic top view illustrating the LED chip arrangement and the first wiring layer of an LED package assembly according to an embodiment of the present invention;

fig. 15 is a schematic top view illustrating a second wiring layer of the LED package assembly of the embodiment of the present invention;

fig. 16 is a schematic top view illustrating the first wiring layer, via layer and second wiring layer of the LED package assembly of this embodiment of the invention;

fig. 17 is a circuit diagram illustrating circuit connections of the LED package assembly of the embodiment;

fig. 18 is a schematic circuit connection diagram illustrating the wiring connections of a LED package assembly in accordance with yet another embodiment of the present invention;

fig. 19 is a schematic circuit connection diagram illustrating the wiring connections of a LED package assembly in accordance with yet another embodiment of the present invention;

fig. 20 is a schematic top view illustrating a first wiring layer of a LED package assembly in accordance with yet another embodiment of the present invention;

fig. 21 is a schematic top view illustrating a second wiring layer of the LED package assembly of this embodiment of the invention;

fig. 22 is a schematic top view illustrating a third wiring layer of the LED package assembly of this embodiment of the present invention;

fig. 23 is a schematic side sectional view illustrating the structure of an LED package assembly according to an embodiment of the present invention.

Detailed Description

Before the present invention is described in detail, it should be noted that in the following description, similar components are denoted by the same reference numerals.

Referring to fig. 1 and 2, an embodiment of a Light Emitting Diode (LED) package assembly according to the present invention is a substrate-less LED package assembly that may include a plurality of light emitting units arranged in an m × n matrix, where m and n are integers greater than 1. Each light emitting unit includes a plurality of LED chips with different wavelengths, preferably, at least three LED chips respectively emit red light (R), green light (G), and blue light (B), and may further include an LED chip (including a wavelength conversion layer) emitting white light, that is, an RGBW combination is formed, so that the brightness of the display screen can be improved, which is very beneficial for outdoor display. Each light emitting unit corresponds to one pixel area PX and may also be referred to as a pixel. In one embodiment, the LED package assembly includes 2 × 2 pixel areas. Each pixel area PX has a plurality of LED chips 100 spaced apart from each other and having a light emitting surface S21, the package assembly further includes a package layer 200 fixing and filling gaps between the plurality of LED chips 100, and a plurality of wiring layers on the package layer. The multi-layer wiring layer includes a first wiring layer 310, a via layer 320, and a second wiring layer 330, each electrically isolated from the other by an insulating layer 500. Wherein a first wiring layer 310 is formed on the lower surfaces of the plurality of LED chips to connect the plurality of LED chips in parallel and/or in series, and the via layer 320 is formed on the first wiring layer 310 to be electrically connected to the first wiring layer 310; a second wiring layer 330 is formed over the via layer 320 in electrical connection with the via layer 320.

Fig. 3 is a simplified schematic diagram of the LED chip arrangement of the package assembly. Referring to fig. 3, the package assembly has four pixel regions PX 1-PX 4, each pixel region PX includes a plurality of LED chips 100, such as a first LED chip 100L1, a second LED chip 100L2, and a third LED chip 100L 3. In other embodiments, each pixel region may also include only two LED chips or more than three LED chips, for example four LED chips. The three LED chips 100L1, 100L2, and 100L3 may emit light of different wavelengths, for example, red light, green light, and blue light, respectively.

Referring to fig. 4, each of the LED chips 100L 1-100L 3 includes a pair of electrodes 110 located on the same side, and each of the LED chips 100L 1-100L 3 includes a first surface S21 and a second surface S22 opposite to each other, and a side surface S24 and an electrode surface S23 connected between the first surface S21 and the second surface S22. The first surface S21 is a light emitting surface S21, and the pair of electrodes 110 is disposed on the second surface S22. Further, the LED chip includes a substrate 101, a first type semiconductor layer 121, a light emitting layer 122, and a second type semiconductor layer 123. The first type semiconductor layer 121 and the second type semiconductor layer 123 may be a p-type semiconductor layer and an n-type semiconductor layer, respectively. The LED chip further includes a transparent substrate 101 disposed on the first type semiconductor layer 121. The electrode group 110 of the LED chip includes a first electrode 111 electrically connected to the first type semiconductor layer 121, and a second electrode 112 electrically connected to the second type semiconductor layer 123. In other embodiments, the electrode set 110 of each LED chip may further include a thickened layer of conductive material. The thickening layers are respectively disposed between the first electrode 111 and the first wiring layer and between the second electrode 112 and the first wiring layer 310, and can be formed by electroplating, chemical plating or printing, and the material can be Cu, Cu_xW or other conductive metallic material. By increasing the thickness of the electrode, the thickness of the electrode can be increasedThe area of the side S24 of the LED chip in contact with the encapsulation layer 200 is increased, thereby increasing the adhesion between the LED chip and the encapsulation layer 200. Preferably, the thickness of the electrode set of each LED chip is 5 to 200 μm, such as 5 to 30 μm, 30 to 50 μm, or 80 to 120 μm, which is selected according to specific requirements. The LED chip 100 may be an LED chip with a conventional size (generally, the single-side size of the chip exceeds 200 μm), or a Mini LED chip (generally, the chip size is 100 to 200 μm), or a Micro LED chip (generally, the chip size does not exceed 100 μm), and the Mini LED chip or the Micro LED chip is preferred in this embodiment.

Referring to fig. 3, the first, second and third LED chips 100L 1-100-L3 in each pixel region PX in the package assembly are arranged in a line, specifically, the LED chips of each light emitting unit are arranged in a line according to a first direction, and the first and second electrodes of each LED chip are arranged in parallel according to a second direction, wherein the first and second directions are substantially perpendicular. In this embodiment, the first electrode 111 and the second electrode 112 are arranged left and right, and the polarities of the electrodes of the two adjacent columns of LED chips are opposite, that is, the chip electrodes of the adjacent columns are symmetrical, so that the arrangement of wiring can be facilitated, and the distance between the chips can be reduced. For example, in the package assembly shown in fig. 3, the polarities of the electrodes of the three LED chips 100L1 to 100L3 in the first pixel area PX1 are opposite to the polarities of the electrodes of the three LED chips 100L1 to L3 in the second pixel area PX 2. When each pixel region is regarded as one pixel, the dot pitch D1 of each pixel is preferably 1mm, more preferably less than 0.8mm, and may be, for example, 0.1 to 0.3mm, 0.3 to 0.5mm, or 0.5 to 0.8 mm. The distance D2 between the chips in the same pixel region PX is preferably less than 100 μm, such as 50-100 μm, or less than 50 μm, and in some display panel applications, the distance between the LED chips in the same pixel region is preferably less than 50 μm, such as 40-50 μm, or 30-40 μm, or 20-30 μm, or 10-20 μm. The smaller the spacing is, the more beneficial the size of the LED packaging assembly is to be reduced, thereby improving the resolution of the display panel.

Referring to fig. 2, the first packaging layer 200 is filled around the first, second and third LED chips 100L 1-L3, and preferably, the light transmittance of the packaging layer 200 is less than 30%; more preferably, the light transmittance of the encapsulation layer 200 is 5% to 20%; optionally, the encapsulation layer 200 is opaque and opaque, and specifically includes a light absorbing component (not shown) disposed at least around a sidewall of the LED chip or between adjacent LED chips, or further at least around the LED semiconductor light emitting stack or around adjacent semiconductor light emitting stacks. The light absorbing component may be light absorbing particles dispersed in epoxy resin or silicone used for the encapsulation layer, such as black particles and carbon powder, or the light absorbing component may be black resin. The light absorption components of the packaging layer 200 are arranged at least around the side wall of the LED to prevent the side surface of the LED chip from emitting light, so that the light emitted from the LED chip is mainly concentrated on the light emitting surface of the LED chip or is completely concentrated on the light emitting surface of the LED chip, and the phenomenon of light crosstalk or light mixing of light between different LED chips in the side surface direction is reduced. In one embodiment, the package layer 200 may be epoxy resin or silicone rubber with a black colorant added thereto, so that the light emitting surface S21 of the LED chip 100 is black in the remaining area of the whole LED package assembly, which is helpful for improving the contrast of the display panel, and the LED chips 100 are isolated from each other by the black package material, which can reduce the optical interference between the LED chips. In some embodiments, the hardness of the encapsulation layer 200 is preferably above D60, and more preferably above D85.

Further, a transparent or translucent material layer is formed on the packaging layer 200 as another packaging layer 400, covering the first surfaces S21 of the first, second and third LED chips, so as to avoid the LED chips from being exposed. The package layer 400 can be used as a light scattering lens to generate a light scattering effect, and when the final LED package assembly is applied to a display panel, the vertigo feeling can be effectively reduced, and further, the package layer 400 can include light scattering materials, such as scattering particles. The thickness of the packaging layer 400 is preferably 5-20 μm, for example 10 μm, so that on one hand, the light-emitting surface of the LED chip can be protected, and on the other hand, optical interference between the LED chips can be reduced by using the packaging layer 200 made of a light-absorbing material. The light transmittance is preferably 40% or more. In some embodiments, the LED package assembly is applied to an indoor display, and the package layer 400 is preferably a translucent layer, and has a light transmittance of preferably 40% to 80%, and more preferably 70% to 80%, which can reduce the brightness of the LED chip, thereby reducing the glare effect of light. In some embodiments, the package assembly is applied to outdoor display, and the package layer 400 is preferably a transparent layer having a light transmittance of preferably 80% or more, more preferably 80%.

In this embodiment, the first, second and third LED chips 100L 1-L3 may be temporarily adhered to a support 600 such as an adhesive tape with the light emitting surface S21 of the LED chip 100 as a crystal fixing surface, and then the electrode surface S24 faces upward, and then the package layer 200 is formed by filling a fluid insulating material between the chips and curing, so as to expose the electrode surface S23 of the LED chip, as shown in fig. 5. In this embodiment, the thickness of the adhesive material 610 of the tape 600 is preferably controlled to be 5 to 20 μm, so as to ensure that the LED chips are not displaced when the package layer is filled, and to ensure that the first surfaces S21 of the first, second, and third LED chips 100L1 to L3 are substantially located on the same horizontal plane, and the height difference is substantially kept below 10 μm, so that the package assembly is beneficial to unifying the light emitting surfaces and reducing the influence of optical crosstalk between the sidewalls when the pixel area is greatly increased.

The multi-layer wiring layer is formed on the second surfaces of the plurality of LED chips, and specifically includes a first wiring layer 310, a via layer 320 and a second wiring layer 330, wherein the first wiring layer 310 is connected to the electrodes 110 of the LED chips, the via layer 320 is formed on the first wiring layer 310, and the second wiring layer 330 is formed on the via layer 320 and is electrically connected to the first wiring layer 310 through the via layer 320. The multilayer wiring layer is preferably made of a metal material with a melting point higher than 400 ℃, such as Ag, Cu, Ni, Al and the like, and the materials of the layers can be the same or different and can be formed by electroplating, chemical plating, printing or other processes. The thickness of each layer is preferably 100 μm or less.

Referring to fig. 6, a first wiring layer 310 is formed on the surface of the package layer 200 and electrically connected to the electrodes 110 of the LED chips. The gaps between the wires of the first wiring layer 310 are filled with an insulating layer 510, exposing the surface S310 of the first wiring layer 310 away from the LED chip. The material of the insulating layer 510 may be the same as or different from that of the encapsulation layer 200. When the same material is used, the insulating layer 510 and the packaging layer 200 are combined into a layer, which is difficult to distinguish, for example, in an embodiment, the LED package assembly is applied to a display device, and the insulating layer 510 and the packaging layer 200 are both epoxy resin or silica gel with a colorant added. In some embodiments, the hardness of the insulating layer 510 is not lower than the hardness of the first wiring layer 310, for example, D60 or more, preferably D85 or more, so as to facilitate the polishing process to expose the surface S310 of the first wiring layer 310.

The first wiring layer 310 includes a plurality of first wirings and at least two common wirings, thereby electrically connecting the LED chips in the multi-dot pixel region PX to constitute an n-up pixel region. Referring to fig. 7, an example of a four-in-one package assembly is shown, in which LED chips of four pixel regions are connected in series and parallel. In other embodiments, the structure is not limited to a four-in-one structure, and may be a nine-in-one structure, a sixteen-in-one structure, or the like. In the package assembly shown in fig. 7, the first wiring layer 310 includes two

common wirings

314a, 314d and ten first wirings, wherein the first wirings 311a to 311d are respectively connected to the first electrodes 111 of the first chips 100-L1 of the respective pixel regions PX, the wirings 313a to 313d are respectively connected to the first electrodes 111 of the third chips 100-L3 of the respective PX, the wiring 312a is connected to the first electrodes of the second LED chips 100-L2 of the PX1 and PX4, the wiring 312b is connected to the first electrodes of the second LED chips 100-L2 of the PX2 and PX3, the common wiring 314a is connected to the second electrodes 112 of the first, second and third LED chips of the PX1 and PX2, and the common wiring 314d is connected to the second electrodes 112 of the first, second and third LED chips of the PX3 and PX 4.

Referring to fig. 8 and 9, the via layer 320 is located on the surface S310 of the first wiring layer 310, in order to form a series of vias 320 on an insulating layer 520, the number and positions of the vias correspond to the respective wirings of the first wiring layer, wherein the solid-oblique line filling pattern of fig. 9 is a via, which is as far away from the respective LED chips as possible. Wherein the material of the insulating layer 520 may be referenced to the insulating layer 510. The thickness of the via layer is usually less than 100 μm, and in some embodiments, the package assembly is a thin structure, and the via layer is preferably 20 to 50 μm, for example, 25 to 30 μm, so that excessive stress and thermal resistance of the via layer can be avoided, and the total thickness of the package structure is reduced while the strength of the package structure is ensured, and finally, the application product is thinner. In other embodiments, the via layer has a thickness of 50-80 μm, such as 60 μm, to increase the thickness of the package assembly appropriately to facilitate pickup from the sidewalls of the device.

Referring to fig. 10, the second wiring layer 330 is disposed on the via layer 320 and electrically connected to the first wiring layer 310 through each via of the via layer 320, and an insulating layer 530 is filled in a gap between each line of the third wiring layer 330 and exposes a surface S330 of the second wiring layer 330 away from the LED chip. The material of the insulating layer 530 may be designed with reference to the insulating layer 510.

Referring to fig. 11, the circuit of the third wiring layer 330 includes a plurality of wires 331ac, 331bd, 333ac, 333bd for connecting the same polarity electrodes of the same type of LED chips, and a plurality of

connectors

331a, 331b, 332a, 332b, 333c, 333d, 334a, and 334d, for example, the wire 331ac connects the first electrodes 111 of the first LED chips 100-L1 of PX1 and PX3, the wire 333ac connects the first electrodes 111 of the third LED chips 100-L3 of PX1 and PX3, and the connectors can be external electrode pads for connecting power. In a preferred embodiment, a pad may be formed in the area corresponding to the connection portion, and an area outside the pad may be covered with ink, epoxy resin, or other insulating material to protect the wires of the second wiring layer 330. In a preferred embodiment, the connection portion of the second wiring layer 330 completely covers each via of the via layer, so as to increase the contact area between the second wiring layer and the via, and meanwhile, in the process flow, the via layer and the second wiring layer can simultaneously form conductive materials in the same process, thereby saving a process of forming conductive materials and grinding, effectively saving cost, and improving product stability.

The insulating layers 510-530 can be made of the same material or different materials, and the specific material can be epoxy resin, silica gel, polyimide, benzocyclobutene or PBO. When the insulating

layers

510 and 530 are made of the same material, they are combined into a layer 500, which is difficult to distinguish. In some embodiments, the insulating layers 510-530 are made of opaque or low-transmittance materials, such as epoxy or silicone doped with black colorant, to prevent or reduce light emitted from the LED chips from escaping from the redistribution layer and causing crosstalk. When a light-tight or low-light-transmission material is used as the insulating layer, a metal line pattern in the wiring layer can be formed first, then the insulating layer is refilled, and finally the surface of the metal line in the wiring layer is exposed in a grinding mode. In other embodiments, when the encapsulation layer 200 is made of a material with low light transmittance or without light transmittance, the insulating layers 510 to 530 may be partially or entirely made of a light-transmissive material, so that the light transmittance is higher than that of the encapsulation layer 200. The light-transmitting layer does not need to add coloring agent or light-absorbing material, such as carbon powder or dye, preferably a silica gel or epoxy resin material layer, and does not contain micron-sized particles (generally, particles with a diameter of more than 1 micron, such as C powder particles), so that the reliability reduction (such as insulation performance reduction) caused by possible non-uniformity, interface and other defects caused by adding the coloring agent is avoided, and the reliability of the insulating layer for coating the wiring layer can be ensured. In other embodiments, the insulating layer is formed by curing the photosensitive material, so that the process can be simplified, and the light-absorbing material is covered around the chip and on the non-metal part of the electrode surface to serve as the packaging layer 200, thereby preventing the crosstalk of the light at the side of the chip.

Referring to fig. 12 and 13, fig. 12 shows a connection relationship of three wiring layers, and fig. 13 is an equivalent circuit diagram of the four-in-one light emitting unit. The four-in-one light emitting unit is output by eight connecting

parts

331a, 331b, 332a, 332b, 333c, 333d, 334a and 334d, wherein the first electrode of the first LED chip 100-L1 is output by the connecting

parts

331a and 331b, the first electrode of the second LED chip 100-L2 is output by the connecting

parts

332a and 332b, the first electrode of the third LED chip 100-L3 is output by the connecting

parts

333c and 333d, the connecting

parts

334a and 334d are used as common electrodes, and the second electrodes 112 of all the LED chips PX 1-PX 4 are respectively connected.

In this embodiment, first, in the arrangement of the LED chips, the LED chips in each PX are arranged in a line, specifically, the LED chips of each light emitting unit are arranged in a row in a first direction, the first and second electrodes of each LED chip are arranged in parallel in a second direction, wherein the first direction and the second direction are basically vertical, the polarities of the electrodes of the LED chips in two adjacent columns are opposite, in the first wiring layer 310, the common poles of the two adjacent LED chips PX at the left and right are connected to form a common pole, the second LED chips 100-L2 of the two adjacent PX at the upper and lower sides (located in the middle of the three chips) are connected in parallel (i.e. the first electrodes of the second LED chips PX1 and PX3 are connected in parallel, and the first electrodes of the second LED chips PX1 and PX4 are connected in parallel), the first LED chips 100-L1 and the third LED chips 100-L3 of PX1 to PX4 are respectively and independently wired, so that the number of electrode terminals of the four-in-one light-emitting unit is reduced to 10; in the second wiring layer, the first and second LED chips of two adjacent upper and lower PX chips are connected in parallel by connecting lines (i.e. the first electrodes of the first LED chips PX1 and PX3 are connected in parallel to form one electrode terminal 331a, the first electrodes of the first LED chips PX2 and PX4 are connected in parallel to form one electrode terminal 331b, the first electrodes of the third LED chips PX1 and PX3 are connected in parallel to form one electrode terminal 334c, and the first electrodes of the third LED chips PX2 and PX4 are connected in parallel to form one electrode terminal 334 d), so that 8 electrode terminals (i.e. 8 connecting parts) are output in total, thereby effectively reducing the number of electrode pads of the package assembly and facilitating the mounting of the package assembly.

The package assembly according to the above exemplary embodiments does not have a package substrate or a support for carrying the LED chip, the light emitting cells arranged in the m × n matrix are mainly fixed and supported by the insulating material layer (including 200, 400, and 500) and the wiring layer, and the thickness T of the package assembly is mainly determined by the thickness T of the LED chip_AAnd thickness T of wiring layer_C. In some embodiments, a mini-type LED chip is used, the chip thickness TA is between 40 and 150 μm, the thickness TC of the multi-layer wiring layer is between 20 and 200 μm, more preferably the thickness TC of the wiring layer is between 50 and 150 μm, and the T, TA satisfies the relation: T/TA is more than or equal to 1.4 and less than or equal to 10, so that overlarge stress and overlarge thermal resistance of the circuit layer can be avoided, and the packaging assembly can be ensured to have strength whileThe total thickness is reduced. For example, in one embodiment, the thickness TA of the LED chip is about 80 μm, the package thickness can be 120 μm to 500 μm, such as 120 to 200 μm, and the sub-layer of each wiring layer can have a thickness of 20 to 50 μm, for example, 30 μm. For example, in another embodiment, when the package assembly has a small size (e.g., 0.4mm × 0.4mm or smaller), it is inconvenient to grab the package assembly from the upper surface of the package assembly, and at this time, the thickness T of the package assembly may be appropriately increased, so that the sidewall of the package assembly has a larger area for the grabbing device to contact and grab, and at this time, preferably, the thickness of the package assembly may be 320 to 500 μm, e.g., 340 to 360 μm, and the thickness of the package assembly may be increased by increasing the thickness of the LED chip and/or the thickness of the wiring layer, e.g., the thickness of the electrode of the LED chip may be increased, and the thickness of each wiring layer may be appropriately increased, at this time, the thickness of the through hole is preferably 30 to 80 μm. In some embodiments, a micro-type LED chip is adopted, the thickness TA of the chip is 5-10 μm, the thickness TC of the multilayer wiring layer is 20-200 μm, more preferably the thickness TC of the wiring layer is 50-150 μm, and the T, TA satisfies the relation: T/TA is more than or equal to 10 and less than or equal to 60, for example, the thickness of the package assembly can be 50-100 μm, or 100-200 μm.

Fig. 14-17 illustrate another embodiment of the LED package assembly of the present invention. Referring to fig. 14, the package assembly also includes a plurality of pixel regions PX 1-PX 4 arranged in an mxn matrix, and unlike the package assembly shown in fig. 3, the direction of the LED chip electrodes in each pixel region is the same, which is beneficial to improving the efficiency and accuracy of chip arrangement. In this embodiment, the first wiring layer includes

first wirings

311a, 313c and common wirings 314a, 314d, in which 311a connects the first LED chips 100-L1 of the laterally adjacent two pixel regions PX1 and PX2, 313c connects the third LED chips 100-L3 of the laterally adjacent two pixel regions PX3 and PX4, 314a is commonly connected to all the LED chips of the longitudinally adjacent pixel regions PX1 and PX4, and 314d is commonly connected to all the LED chips of the longitudinally adjacent pixel regions PX2 and PX 3. Referring to fig. 15 and 16, the second wiring layer includes

connection portions

331a, 331c, 332b, 332c, 333b, 333c, 334a, 334d and connection lines 331cd, 332ab, 332cd, 333ab, wherein 331cd connects the first LED chips 100-L1 of the laterally adjacent pixel regions PX3 and PX4, 332ab connects the second LED chips 100-L2 of the laterally adjacent pixel regions PX1 and PX2, 332ab connects the second LED chips 100-L2 of the laterally adjacent pixel regions PX1 and PX2, 333cd connects the third LED chips 100-L3 of the laterally adjacent pixel regions PX3 and PX4, fig. 17 shows an equivalent circuit diagram of the four-in-one package assembly, wherein 334a and 334d are respectively connected to all the LED chips of the light emitting units located at the same column in the longitudinal direction, and 331a, 331c, 332b, 332c, 333b, 333c are respectively connected to the same type of LED chips of the light emitting units located at the same row in the lateral direction.

Fig. 18 is yet another embodiment of the present invention LED package assembly. The LED device also includes four pixel regions PX 1-PX 4 arranged in a 2X 2 matrix, each pixel region corresponding to a light emitting unit, and the LED chips of each pixel region arranged in the same electrode direction. Unlike the LED package assemblies shown in fig. 14-17, the first wiring layer 330 includes

conductive traces

314a and 314b respectively connecting the second electrodes 112 of all the LED chips in the same column, the second wiring layer includes conductive traces 331 a-333 a, 331 b-333 b respectively connecting the first electrodes 111 of the LED chips of the same type in the same row, for example, the trace 331a connects the first electrodes 111-L1 of the first LED chip of the first row, the trace 332a connects the first electrodes 111-L2 of the second LED chip of the first row, and the trace 331b connects the first electrodes 111-L1 of the first LED chip of the second row. The first wiring layer is isolated from the second wiring layer by an insulating layer and electrically connected through the via layer. The routing connection mode of the first wiring layer and the second wiring layer can be reversed.

Fig. 19 is yet another embodiment of the present invention LED package assembly. The LED device also includes four pixel regions PX 1-PX 4 arranged in a 4 x1 matrix. The LED packaging assembly is rectangular or approximately rectangular, is convenient to assemble when applied to a display device, and can realize the minimum number of external bonding pads through wiring design. Specifically, the first wiring layer includes lines 314a to 314d respectively connecting the second electrodes of the light emitting cells of the pixel regions PX1 to PX4 in parallel in the longitudinal direction, and forming four external electrode terminals; the second wiring layer includes 331a to 333a connecting the first, second and third LED chips having the same pixel regions PX1 to PX4, respectively, and forming three external electrode terminals, so that the pixel regions PX1 to PX4 can form a four-in-one light emitting module.

In this embodiment, the four-in-one LED package assembly changes the arrangement of the light emitting units, and adopts a 4 × 1 manner, and the number of external bonding pads P =4+ a, where a is the number of chips in a single light emitting unit, and in a specific embodiment, each light emitting unit has three chips, namely, the red LED chip 100-L1, the green LED chip 100-L2, and the blue LED chip 100-L3, and only 7 bonding pads are needed, so that the minimum number of bonding pads can be achieved, the size of the package assembly can be reduced, the wiring is facilitated, the application-side mounting is facilitated, and the risk of short circuit is reduced.

Fig. 20-22 illustrate yet another embodiment of the present invention LED package assembly. FIG. 20 shows an arrangement of LED chips and a first wiring layer of the LED package assembly, wherein the LED device also includes 16 pixel regions PX 1-PX 4 arranged in a 4 × 4 matrix. In the 16-in-one LED package assembly, the distance D1 between the light emitting units is preferably 0.1-0.5 mm, for example, 0.2-0.5 mm. The LED chip structure comprises LED chips, a first electrode and a second electrode, wherein the LED chips of each light-emitting unit are arranged in a row according to a first direction, the first electrode and the second electrode of each LED chip are arranged in parallel according to a second direction, the first direction and the second direction are basically vertical, the second electrodes of all the LED chips in the same row are connected in parallel in the first direction, the first electrodes of the same type of LED chips in the same row are connected in parallel in the second direction, and the first electrodes and the second electrodes of the LED chips in adjacent rows are opposite in position, so that the first electrodes of the same type of LED chips in the same row are conveniently connected in parallel, and the circuit of a wiring layer is simplified. Specifically, the first wiring layer includes common wirings 314a to 314d commonly connected to second electrodes of the LED chips of the light emitting cells of Nx1 to Nx4 columns, respectively, and the first wiring includes 311 to 313, wherein 311 is connected to the first electrodes of the first LED chips L1 of Nx2 and Nx3 columns in the same row, and 312 is connected to Nx2 and Nx3 columns in the same rowThe first electrodes of the second LED chips L2 in the same row are 313 connected to the first electrodes of the Nx2 th and Nx3 th columns of the third LED chips L3 in the same row. The first line further includes lines 311a to 313a connected to first electrodes of the first, second and third LED chips of Nx1 and Nx4 rows, respectively. FIG. 21 shows a via level pattern having a series of vias, wherein via 324 is connected to common lines 314 a-d of a first wiring level and vias 321-323 are connected to first lines of the first wiring level, respectively. FIG. 22 shows a second wiring layer pattern including connection lines 331 to 333 and connection portions 331a to 333, 334, where the connection line 331 is connected in parallel to the first electrodes of the first LED chips in the same row, and the connection line 332 is connected in parallel to the same row (e.g., N is N)_Y1~ N_Y4Row), a connecting line 333 connected in parallel with the first electrodes of the third LED chips in the same row, and a connecting portion serving as an external connecting terminal, wherein 331a to 333a are respectively connected to the connecting lines 331 to 333, and 334 is connected to 324. In a preferred embodiment, a pad may be formed in a region corresponding to the connection portion, and an area outside the pad may be covered with ink, epoxy resin, or other insulating material to protect the lines of the second wiring layer.

In the embodiment, through reasonable arrangement of the LED chips and design of the wiring layers, on one hand, the circuit connection of the wiring layers can be simplified, and meanwhile, the reliability of the product is improved; moreover, the number of layers of the wiring layer is not more than four (including the external bonding pad layer), so that the light and thin thickness of the product can be ensured, and the light and thin terminal product is facilitated.

Fig. 23 is a substrate-less LED package assembly. Unlike the package assembly shown in fig. 2, the package layer 200 covers both the sidewall of the LED chip and the sidewall S311 of the first wiring layer 310. The encapsulation layer 200 is preferably opaque or low-transparent, for example, the light transmittance is lower than 30%, for example, 5 to 20%, and more preferably, the encapsulation layer is made of a black material, for example, epoxy resin or silica gel of a black colorant. The insulating

layers

520 and 530 may be made of a material that is transparent or opaque to light.

On the contrary, the utility model discloses LED encapsulation subassembly utilizes this packaging layer fixed and encapsulation to be the pixel of matrix arrangement to design multilayer wiring layer and carry out the LED chip of each pixel of establishing ties. Therefore, the utility model discloses do not need the circuit board of bonding wire and accurate wiring, promoted reliability and contrast. In addition, the electrode group of the LED chip does not need to be soldered on the circuit board by solder paste, thereby avoiding the problem of poor soldering of the chip, improving the integration of the LED and the electronic component and really achieving the purpose of the utility model.

However, the above description is only an example of the present invention, and the scope of the present invention should not be limited thereby, and all the simple equivalent changes and modifications made according to the claims and the contents of the patent specification are still included in the scope of the present invention.

Claims

1. A light emitting diode package assembly, comprising:

the LED display device comprises a plurality of light-emitting units arranged in an m x n matrix, wherein m and n are integers, m x n is more than or equal to 4, and each light-emitting unit comprises a first LED chip, a second LED chip and a third LED chip; each LED chip comprises a first surface, a second surface, a side surface and an electrode group, wherein the first surface, the second surface, the side surface and the electrode group are opposite to each other, the side surface is connected between the first surface and the second surface, the electrode group is formed on the second surface and comprises a first electrode and a second electrode, the first surface is a light-emitting surface, the LED chips of each light-emitting unit are arranged in a row according to a first direction, and the first electrode and the second electrode of each LED chip are arranged in parallel according to a second direction;

the packaging layer is used for filling gaps among the LED chips and covering the side walls of the LED chips;

and the wiring layer is formed on the second surfaces of the LED chips, and is used for connecting the first electrodes of the first, second and third LED chips of two or more adjacent light-emitting units in parallel from a third direction and connecting the second electrodes of the first, second and third LED chips of two or more adjacent light-emitting units in parallel from a fourth direction so as to electrically connect the light-emitting units to form the all-in-one light-emitting module, wherein the third direction is the same as the first direction, the fourth direction is the same as the second direction, or the third direction is the same as the second direction, and the fourth direction is the same as the first direction.

2. The light emitting diode package assembly of claim 1, wherein: the pitch between adjacent light emitting cells is 0.8mm or less.

3. The light emitting diode package assembly of claim 1, wherein: the total thickness of the packaging assembly is 100-500 mu m.

4. The light emitting diode package assembly of claim 1, wherein: the total thickness of the packaging assembly is between 120 and 200 mu m or between 320 and 500 mu m.

5. The light emitting diode package assembly of claim 1, wherein: defining the thickness of the LED chip as T_AThe thickness of the packaging layer is T_BTotal thickness of the package assembly is T, T, T_A、T_BSatisfy the relation: t is_B/T_A≥1，10≥T/T_A≥1.4，120μm≥T_A≥50μm。

6. The light emitting diode package assembly of claim 1, wherein: defining the thickness of the LED chip as T_AThe thickness of the packaging layer is T_BTotal thickness of the package assembly is T, T, T_A、T_BSatisfy the relation: t is_B/T_A≥1，60≥T/T_A≥10，10μm≥T_A≥5μm。

7. The light emitting diode package assembly of claim 1, wherein: the height difference of the first surfaces of the plurality of LED chips of the plurality of light emitting units is 10 [ mu ] m or less.

8. The light emitting diode package assembly of claim 1, wherein: the packaging layer is a colored layer, a light-transmitting layer covers the first surface of the light-emitting unit, and the transmissivity of the light-transmitting layer is greater than that of the packaging layer.

9. The light emitting diode package assembly of claim 8, wherein: the thickness of the light-transmitting layer is 20 [ mu ] m or less.

10. The light emitting diode package assembly of claim 8, wherein: the light transmittance of the light-transmitting layer is 40-80%.

11. The light emitting diode package assembly of claim 8, wherein: the light-transmitting layer has a light transmittance of 70 or more.

12. The light emitting diode package assembly of claim 1, wherein: the light transmittance of the packaging layer is 0-30%.

13. The light emitting diode package assembly of claim 1, wherein: the light emitting units are adjacently arranged side by side, wherein the first electrodes of the plurality of LED chips of a first light emitting unit are adjacent to the first electrodes of the plurality of LED chips of a second light emitting unit.

14. The light emitting diode package assembly of claim 1, wherein: the wiring layer comprises a first wiring layer, a through hole layer and a second wiring layer, wherein the first wiring layer is formed on the second surfaces of the LED chips and is connected with the first electrodes and the second electrodes of the LED chips, the through hole layer is formed on the first wiring layer and is electrically connected with the first wiring layer, and the second wiring layer is formed on the through hole layer and is electrically connected with the through hole layer.

15. The light emitting diode package assembly of claim 14, wherein: the first wiring layer is connected to first electrodes of two or more LED chips positioned in the same row and emitting the same type of light, and the second wiring layer is connected to second electrodes of first, second and third LED chips of two or more light emitting units positioned in the same column.

16. The light emitting diode package assembly of claim 14, wherein: the first wiring layer includes a common wiring commonly connected to the plurality of LED chips of two groups of light emitting cells adjacent in the second direction, and a first wiring; the first wiring layer connects the first LED chips of two groups of light-emitting units adjacent to each other in the first direction in parallel, and the second wiring layer connects the second LED chips and the third LED chips of two groups of light-emitting units adjacent to each other in the second direction in parallel.

17. The light emitting diode package assembly of claim 14, wherein: the first wiring layer includes a common wiring commonly connected to the plurality of LED chips of two groups of light emitting cells adjacent in the second direction, and a first wiring; the light-emitting units are divided into two parts, first wiring is respectively connected with a first LED chip of the light-emitting unit of the first part in parallel and a third LED chip of the light-emitting unit of the second part in parallel, the first LED chips of two groups of light-emitting units adjacent in the first direction are respectively connected with the second wiring layer in parallel, and the second wiring layer is respectively connected with LED chips of the same type of the light-emitting units adjacent in the second direction in parallel, so that the LED chips of the same type of the light-emitting units adjacent in the first direction are respectively connected in parallel.

18. The light emitting diode package assembly of claim 14, wherein: the second wiring layer includes a wiring connecting the same type of LED chips of different light emitting units in parallel and a connection portion serving as an external connection input electrode.

19. The light emitting diode package assembly of claim 18, wherein: the number of the connecting parts is n + mxa, wherein a is the number of the LED chips of each light-emitting unit, and n is larger than or equal to m.

20. The light emitting diode package assembly of claim 14, wherein: the thickness of the through hole layer is 20-80 mu m.

21. The light emitting diode package assembly of claim 1, wherein: the wiring layer comprises a plurality of layers of conductive circuits which are electrically isolated from each other, and the number of the conductive circuits is less than four.

22. The light emitting diode package assembly of claim 21, wherein: at least one layer of the multilayer conductive circuit has a thickness of 50 μm or less.

23. The light emitting diode package assembly of claim 21, wherein: at least one layer of the multilayer conductive circuit has a thickness of 60 μm or more.

24. The light emitting diode package assembly of claim 1, wherein: the packaging structure further comprises an insulating layer formed on the surface of the packaging layer, and the insulating layer covers the wiring layer.

25. The light emitting diode package assembly of claim 24, wherein: the insulating layer includes one or more layers, wherein at least one layer has a hardness greater than that of the wiring layer.

26. The light emitting diode package assembly of claim 24, wherein: the insulating layer includes one or more layers, at least one of which has a hardness of D60 or more.

27. The light emitting diode package assembly of claim 24, wherein: the insulating layer comprises one or more layers, wherein at least one layer is made of the same material as the packaging layer.

28. The light emitting diode package assembly of claim 24, wherein: the insulating layer is of one-layer or multi-layer structure, wherein at least one layer is formed by curing photosensitive materials.

29. The light emitting diode package assembly of claim 24, wherein: the insulating layer comprises one or more layers, at least one of which is a transparent layer.

30. The light emitting diode package assembly of claim 1, wherein: the LED packaging structure further comprises bonding pads, wherein the number P of the bonding pads is n + m multiplied by a, a is the number of the LED chips of each light-emitting unit, and n is larger than or equal to m.