CN210351116U - Time delay control circuit - Google Patents
Time delay control circuit Download PDFInfo
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- CN210351116U CN210351116U CN201921343339.6U CN201921343339U CN210351116U CN 210351116 U CN210351116 U CN 210351116U CN 201921343339 U CN201921343339 U CN 201921343339U CN 210351116 U CN210351116 U CN 210351116U
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Abstract
The utility model relates to a time delay control circuit, which comprises a timing circuit, a release circuit and a control circuit; compared with the prior art, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the second voltage stabilizing diode D2 are added in the timing circuit, so that the base current of the first triode Q1 is slowed down, and the intrinsic safety requirement of the industrial and mining industry is met; a third resistor R3, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third capacitor C3, a third voltage stabilizing diode D3, a fourth diode D4 and a second triode Q2 are added in the control circuit, so that the time delay function can be stably realized when the input voltage signal Vin is frequently switched on and off, the return difference of the corresponding input voltage signal Vin in the starting and the closing of the time delay control circuit can be set, and the working stability of the circuit is improved.
Description
Technical Field
The utility model relates to an electronic circuit technical field, in particular to compromise delay control circuit who starts time delay and turn-off hold time.
Background
In a delay control circuit requiring high precision and long time, digital logic control circuit schemes taking a microprocessor as a core are widely applied in the market at present, and the circuit schemes are not suitable for circuits requiring short delay time due to high component cost and complex structure. Especially for the circuits with higher volume and cost requirements and lower delay time, the use of such circuit solution will result in unnecessary space and cost waste.
In recent years, with the rapid development of the internet of things, the internet of things technology has been applied to various industries including the coal mine industry. Environmental information such as temperature and humidity in a mine can be collected through the sensor, and a power supply of the sensor is connected with an intrinsically safe power supply output end in a mine substation through a lead with a safety distance of thousands of meters. In the coal mine environment with a large amount of flammable and combustible mixtures, the electrical equipment has intrinsic safety requirements, and even the instrument equipment is required to pass relevant authentication of intrinsic safety and explosion prevention. Because the input end passes through a long power supply wire, the power supply of the sensor cannot have current spikes when being started according to the requirement of intrinsic safety in a mine, and a long time delay starting function is needed. When the front end of the sensor is suddenly powered off, a certain time is required to process the current data, so that the sensor power supply is required to have the corresponding required turn-off maintenance performance.
After the input voltage signal is turned off, a circuit with a certain requirement on the output turn-off maintaining time must have larger energy storage devices, such as a large capacitor or a large inductor, and the energy storage devices release the stored electric energy after the power-off so that the circuit continues to work to achieve the required turn-off maintaining time. If the circuit needs the starting delay function and the turn-off maintaining function at the same time, the starting delay energy supply can be designed by combining the energy storage devices which must be used, and the benefits of reducing the cost and the volume can be achieved by multiplexing the components.
For example, when the electric energy stored in the large capacitor is used as the main power source after the input is turned off, it is considered that the RC charging/discharging circuit is also used as a part of the start-up delay circuit. However, considering that the charging time of the RC charging circuit varies greatly in different input voltages and operating temperature ranges, it needs to be optimized.
Fig. 1 is a schematic block diagram of a delay control circuit, which includes a timing circuit, a bleeding circuit and a control circuit; the timing circuit is used for setting start delay time and turn-off maintaining time, the input end of the timing circuit is connected with an input voltage signal Vin, the control output end of the timing circuit is connected with the control end of the control circuit, and the discharge output end of the timing circuit is connected with the input end of the discharge circuit; the bleeder circuit is used for providing a bleeder channel for the capacitor when the circuit is switched off and maintaining the power supply of the circuit, and the output end of the bleeder circuit is connected with an input voltage signal Vin; the control circuit is used for converting the output end of the delay control circuit from a suspension or high level state to a grounding state or from the grounding state to the suspension or high level state after the input voltage signal Vin is started and through set starting delay time, the input end of the control circuit is connected with the output end of the bleeder circuit and the input voltage signal Vin, and the output end of the control circuit is connected with the signal output end Vo to serve as the output end of the whole delay control circuit. The output end of the delay control circuit is particularly suitable for being connected with an enabling pin of a control chip, the connection mode of the delay control circuit, the main power circuit, the control chip and peripheral circuits thereof is shown in an application implementation principle block diagram of the delay control circuit shown in figure 2, after an input voltage signal Vin is started, the delay control circuit outputs an overturning signal to the enabling pin of the control chip after starting delay time, so that the control chip starts to work, and the main power circuit starts to work; after the input voltage signal Vin is turned off, the delay control circuit maintains the main power circuit, the control chip and the peripheral circuits thereof to work for a period of time.
Fig. 3 is a schematic diagram of a conventional delay control circuit, in which a first resistor R1 and a first capacitor C1 constitute a timing circuit, one end of the first resistor R1 is an input end of the timing circuit and is connected to an input voltage signal Vin, the other end of the first resistor R1 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, and a connection point of the first resistor R1 and the first capacitor C1 is a control output end and a bleed-off output end of the timing circuit at the same time; the first diode D1 forms a bleeder circuit, the anode of the first diode D1 is the input end of the bleeder circuit, and the cathode of the first diode D1 is the output end of the bleeder circuit and is connected with the input voltage signal Vin; the control circuit is composed of a second resistor R2 and a first triode Q1, one end of the second resistor R2 is an input end of the control circuit and is connected with an input voltage signal Vin, the other end of the second resistor R2 is connected with a collector of the first triode Q1, an emitter of the first triode Q1 is grounded, a base of the first triode Q1 is a control end of the control circuit, and a connection point of the second resistor R2 and the collector of the first triode Q1 is an output end of the control circuit.
The working principle of the circuit of fig. 3 is as follows:
1. before the input voltage signal Vin is powered on, the first triode Q1 is in an off state;
2. when the input voltage signal Vin is powered on, the input voltage signal Vin is connected to the signal output terminal Vo through the second resistor R2, the signal output terminal Vo outputs a high level, and meanwhile, the input voltage signal Vin charges the first capacitor C1 through the first resistor R1, and the charging time of the first capacitor C1 can be changed by selecting appropriate parameters of the first resistor R1. When the first capacitor C1 is charged for a period of time T1 until the emitter junction voltage Vbe1 of the first transistor Q1 reaches the turn-on voltage, the first transistor Q1 starts to be turned on and gradually enters a saturated conduction state, the output voltage signal Vo is also changed from a high level to a ground state, and the time T1 is the start delay time of the delay control circuit.
3. When the input voltage signal Vin is turned off, the capacitor C1 releases the stored electric energy to the input voltage signal Vin end through the first diode, so that the signal output end Vo still keeps a high level state, thereby achieving the function of turn-off maintaining.
This technique has the disadvantage that,
1. the circuit is simple in structure, and in a wide input voltage range or temperature range, the consistency of the starting delay time of the circuit is poor because the RC charge-discharge time can change along with the change of an input voltage signal Vin and the conduction voltage drop of the first triode Q1 is a negative temperature coefficient;
2. when the first triode Q1 is just conducted, the base current of the first triode Q1 is not subjected to current limiting protection, so that the circuit is not suitable for being directly used in intrinsically safe electrical equipment in mine special environments;
3. the output end of the circuit after delayed start is in a grounding state, and the circuit is not suitable for circuits requiring high-level work.
SUMMERY OF THE UTILITY MODEL
Therefore, the to-be-solved technical problem of the utility model is to provide a high time accuracy, compromise the time delay control circuit who starts time delay and turn-off and maintain, be applicable to the mine class special environment's essential safety electrical equipment in, satisfy the requirement of the present case explosion-proof standard, can be in the input voltage scope of broad and the temperature range of broad, better keep starting the uniformity of time delay.
In order to solve the above problem, the technical scheme of the utility model is as follows:
a time delay control circuit comprises a timing circuit, a bleeder circuit and a control circuit; the input end of the timing circuit is connected with the input voltage signal Vin, the control output end of the timing circuit is connected with the control end of the control circuit, and the discharge output end of the timing circuit is connected with the input end of the discharge circuit; the output end of the bleeder circuit is connected with an input voltage signal Vin; the input end of the control circuit is connected with an input voltage signal Vin, and the output end of the control circuit is connected with a signal output end Vo to be used as the output end of the whole delay control circuit; the timing circuit comprises a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is an input end of the timing circuit, the other end of the first resistor R1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, and a connection point of the first resistor R1 and the first capacitor C1 is a discharge output end of the timing circuit; the bleeder circuit comprises a first diode D1, wherein the anode of the first diode D1 is the input end of the bleeder circuit, and the cathode of the first diode D1 is the output end of the bleeder circuit; the control circuit comprises a second resistor R2 and a first triode Q1, one end of the second resistor R2 is an input end of the control circuit, the other end of the second resistor R2 is connected with a collector of the first triode Q1, an emitter of the first triode Q1 is grounded, and a connection point of the second resistor R2 and the collector of the first triode Q1 is an output end of the control circuit; the method is characterized in that:
the timing circuit further comprises a seventh resistor R7, one end of the seventh resistor R7 is connected to the other end of the first resistor R1, and the other end of the seventh resistor R7 is used as a control output end of the timing circuit.
The control circuit further comprises a third resistor R3 and a second triode Q2, one end of the third resistor R3 is connected with the input end of the control circuit, the other end of the third resistor R3 is connected with the base electrode of the first triode Q1 and the collector electrode of the second triode Q2, the base electrode of the second triode Q2 is the control end of the control circuit, and the emitter electrode of the second triode Q2 is grounded.
As a first modified embodiment of the control circuit, the control circuit is characterized in that: the control circuit comprises a second capacitor C2, a third voltage-stabilizing diode D3, a first triode Q1, a second resistor R2 and a seventh resistor R7, one end of the second resistor R2 is an input end of the control circuit, the other end of the second resistor R2 is connected with a collector of the first triode Q1 to be an output end of the control circuit, one end of a second capacitor C2, a cathode of the third voltage-stabilizing diode D3 and one end of the seventh resistor R7 are connected, a connection point of the second capacitor C53925 and the cathode of the third voltage-stabilizing diode D3 is a control end of the control circuit, the other end of the seventh resistor R7 and an anode of the third voltage-stabilizing diode D3 are connected with a base of the first triode Q1, and the other end of the second capacitor C2 and an emitter of the first.
The negative temperature characteristic of the PN junction conducting voltage can be compensated by utilizing the positive temperature characteristic of the voltage stabilizing value of the third voltage stabilizing diode D3, so that the starting delay time can keep better consistency in a wider temperature range; the second capacitor C2 serves as a bypass capacitor to prevent the cathode electrical signal of the third zener diode D3 from being triggered by mistake; by adjusting the resistance of the seventh resistor R7, the base current of the first transistor Q1 can be compensated.
As a second modified embodiment of the control circuit, the control circuit is characterized in that: the control circuit comprises a second resistor R2, a third resistor R3, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third voltage-stabilizing diode D3, a fourth diode D4, a first triode Q1 and a second triode Q2, one end of a second resistor R2 and one end of the third resistor R3 are connected with an input end of the control circuit, the cathode of the fourth diode D4, one end of the seventh resistor R7, the cathode of the third voltage-stabilizing diode D3 and one end of a second capacitor C2 are connected, the connection point is a control end of the control circuit, the other end of the seventh resistor R7 and the anode of the third voltage-stabilizing diode D3 are connected with the base of the second triode Q2, the anode of the fourth diode D4 is connected with one end of an eighth resistor R8, the other end of the third resistor R3 is connected with the collector of the second triode Q2 and the base of the first triode Q1, the other end of the first resistor Q1, the collector of the second resistor R8 and the other end of the eighth resistor R2 are connected with an output end of the control, the other end of the second capacitor C2, the emitter of the first transistor Q1, and the emitter of the second transistor Q2 are grounded.
A turn-off release channel of the signal output end Vo is introduced through the fourth diode D4 and the eighth resistor R8, so that the delay control circuit can still realize reliable start-up delay and turn-off maintenance when an input voltage signal is rapidly and frequently turned on and turned off; by designing the parameters of the fourth diode and the eighth resistor, the return difference of the input voltage signals corresponding to the starting and the turning-off of the delay control circuit can be set, and the working stability of the circuit is improved.
Preferably, the control circuit further comprises a third capacitor C3, the third capacitor C3 is connected in parallel between the collector and the emitter of the first transistor Q1, and the third capacitor C3 serves as a decoupling capacitor to prevent the signal at the signal output terminal Vo from being interfered.
The utility model also provides another delay control circuit with the same inventive concept, which comprises a timing circuit, a release circuit and a control circuit; the input end of the timing circuit is connected with the input voltage signal Vin, the control output end of the timing circuit is connected with the control end of the control circuit, and the discharge output end of the timing circuit is connected with the input end of the discharge circuit; the output end of the bleeder circuit is connected with an input voltage signal Vin; the input end of the control circuit is connected with an input voltage signal Vin, and the output end of the control circuit is connected with a signal output end Vo to be used as the output end of the whole delay control circuit; the timing circuit comprises a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is an input end of the timing circuit, the other end of the first resistor R1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, and a connection point of the first resistor R1 and the first capacitor C1 is a discharge output end of the timing circuit; the bleeder circuit comprises a first diode D1, wherein the anode of the first diode D1 is the input end of the bleeder circuit, and the cathode of the first diode D1 is the output end of the bleeder circuit; the control circuit comprises a second resistor R2 and a first triode Q1, one end of the second resistor R2 is an input end of the control circuit, the other end of the second resistor R2 is connected with a collector of the first triode Q1, an emitter of the first triode Q1 is grounded, and a connection point of the second resistor R2 and the collector of the first triode Q1 is an output end of the control circuit; the method is characterized in that:
the timing circuit further comprises a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second zener diode D2, one end of the sixth resistor R6 is connected to a connection point of the first resistor R1 and the first capacitor C1, the other end of the sixth resistor is connected to a cathode of the second zener diode D2 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected with one end of the fifth resistor R5 to serve as a control output end of the timing circuit, and an anode of the second zener diode D2 and the other end of the fifth resistor R5 are grounded.
By setting the voltage-stabilizing value of the second voltage-stabilizing diode D2 and the voltage-dividing proportion of the fourth resistor R4 and the fifth resistor R5 in the timing circuit, a high-precision starting voltage point and an under-voltage turn-off point are set, so that the starting delay time and the turn-off maintaining time have better consistency in a wider input voltage range.
As a first modified embodiment of the control circuit, the control circuit is characterized in that: the control circuit further comprises a third resistor R3 and a second triode Q2, one end of the third resistor R3 is connected with the input end of the control circuit, the other end of the third resistor R3 is connected with the base electrode of the first triode Q1 and the collector electrode of the second triode Q2, the base electrode of the second triode Q2 is the control end of the control circuit, and the emitter electrode of the third resistor R3 is grounded.
When the delay control circuit works normally, the signal output end Vo outputs a high level, and the delay control circuit is particularly suitable for being combined with a commonly used high level enabling control chip, the output end of the delay control circuit is connected with an enabling pin of the high level enabling control chip, and the control chip drives the main power circuit to work, so that starting delay and power failure delay can be realized.
As a second modified embodiment of the control circuit, the control circuit is characterized in that: the control circuit further comprises a second capacitor C2, a third voltage-stabilizing diode D3 and a seventh resistor R7, one end of the second capacitor C2, the cathode of the third voltage-stabilizing diode D3 and one end of the seventh resistor R7 are connected, the connection point of the second capacitor C2 and the cathode of the third voltage-stabilizing diode D3 is the control end of the control circuit, the other end of the seventh resistor R7 and the anode of the third voltage-stabilizing diode D3 are connected with the base electrode of the first triode Q1, and the other end of the second capacitor C2 is grounded.
The beneficial effects of the improved implementation are the same as those of the first improved implementation of the control circuit of the first delay control circuit, and are not described herein again.
As a third modified embodiment of the control circuit, the control circuit is characterized in that: the control circuit further comprises a third resistor R3, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third zener diode D3, a fourth diode D4 and a second triode Q2, one end of the third resistor R3 is connected with the input end of the control circuit, the cathode of the fourth diode D4, one end of the seventh resistor R7, the cathode of the third zener diode D3 and one end of the second capacitor C2 are connected, the connection point is the control end of the control circuit, the other end of the seventh resistor R7 and the anode of the third zener diode D3 are connected with the base of the second triode Q2, the anode of the fourth diode D4 is connected with one end of the eighth resistor R8, the other end of the third resistor R3 is connected with the collector of the second triode Q2 and the base of the first triode Q1, the other end of the eighth resistor R8 is connected with the output end of the control circuit, and the emitter of the second capacitor C2 and the emitter of the second triode Q2 are grounded.
The beneficial effects of the improved implementation are the same as those of the second improved implementation of the control circuit of the first delay control circuit, and are not described herein again.
Preferably, the control circuit further includes a third capacitor C3, and the third capacitor C3 is connected in parallel between the collector and the emitter of the first transistor Q1.
In addition to the above-mentioned beneficial effect that brings of improving the embodiment, the utility model discloses still have following beneficial effect and do:
(1) the charging and discharging speed of the first capacitor C1 is set by changing the parameters of the first resistor R1 and the first capacitor C1, so that the starting delay time and the turn-off maintaining time of the circuit can be freely set;
(2) a divider resistor is added at the control output end of the timing circuit to reduce the base current when the triode is conducted, so that the requirement of intrinsic safety is met.
Drawings
FIG. 1 is a functional block diagram of a delay control circuit;
FIG. 2 is a schematic block diagram of an application implementation of the delay control circuit;
FIG. 3 is a schematic diagram of a conventional delay control circuit;
fig. 4 is a schematic diagram of a delay control circuit according to a first embodiment of the present invention;
fig. 5 is a schematic diagram of a delay control circuit according to a second embodiment of the present invention;
fig. 6 is a schematic diagram of a delay control circuit according to a third embodiment of the present invention;
fig. 7 is a schematic diagram of a delay control circuit according to a fourth embodiment of the present invention.
Detailed Description
First embodiment
Fig. 4 is a schematic diagram of a delay control circuit according to a first embodiment of the present invention, where the difference between the present embodiment and the prior art shown in fig. 3 is: the timing circuit further comprises a seventh resistor R7, the control circuit further comprises a third resistor R3 and a second triode Q2, one end of the seventh resistor R7 is connected to the other end of the first resistor R1, the other end of the seventh resistor R7 is connected with the base of the second triode Q2, one end of the third resistor R3 is connected with the input end of the control circuit, the other end of the third resistor R3 is connected with the base of the first triode Q1 and the collector of the second triode Q2, and the emitter of the second triode Q2 is grounded.
The working principle of the device is different from that of the prior art shown in figure 3 in that:
when the input voltage signal Vin is powered on, the first triode Q1 is firstly turned on through the second resistor R2, the signal output terminal Vo is pulled to the ground, when the first capacitor C1 is charged for a period of time T1 until the second triode Q2 starts to be turned on and gradually enters a saturated conduction state, the base voltage of the first triode Q1 is pulled to the ground, the first triode Q1 is turned off, the signal output terminal Vo is also changed from the ground to a high level state, the time T1 is the start delay time of the delay control circuit, and if the R3 is removed, the signal output terminal Vo is changed from the ground to a floating state after the start delay time T1.
The seventh resistor R7 is connected in series between one end of the first capacitor C1 and the base of the second triode Q2 to reduce the base current of the second triode Q2 when the second triode Q2 is conducted, thereby meeting the requirement of intrinsic safety.
Second embodiment
Fig. 5 is a schematic diagram of a delay control circuit according to a second embodiment of the present invention, where the difference between the present embodiment and the prior art shown in fig. 3 is: the timing circuit further comprises a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second zener diode D2, one end of the sixth resistor R6 is connected to a connection point of the first resistor R1 and the first capacitor C1, the other end of the sixth resistor is connected to a cathode of the second zener diode D2 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected with one end of the fifth resistor R5 to serve as a control output end of the timing circuit, and an anode of the second zener diode D2 and the other end of the fifth resistor R5 are grounded; if R2 is removed, the signal output Vo will be grounded from floating after the activation delay time T1.
The working principle of this embodiment is basically the same as that of the prior art shown in fig. 3, and will not be described herein. One end of the first capacitor C1 is connected to the base of the first transistor Q1 through the sixth resistor R6 and the fourth resistor R4, and when the first transistor Q1 is turned on, the base current is slowed down to meet the requirement of intrinsic safety.
Third embodiment
Fig. 6 is a schematic diagram of a delay control circuit according to a third embodiment of the present invention, and as shown in the drawing, the present embodiment is different from the second embodiment in that: the control circuit further comprises a second capacitor C2, a third voltage-stabilizing diode D3 and a seventh resistor R7, one end of the second capacitor C2, the cathode of the third voltage-stabilizing diode D3 and one end of the seventh resistor R7 are connected, the connection point of the second capacitor C2 and the cathode of the third voltage-stabilizing diode D3 is the control end of the control circuit, the other end of the seventh resistor R7 and the anode of the third voltage-stabilizing diode D3 are connected with the base electrode of the first triode Q1, and the other end of the second capacitor C2 is grounded.
The second capacitor C2 is connected in parallel with the fifth resistor R5 as a bypass capacitor to prevent the cathode electrical signal of the third zener diode D3 from being triggered by mistake; the seventh resistor R7 is connected in parallel with the third zener diode D3, and the base current of the first transistor Q1 can be compensated by adjusting the resistance of the seventh resistor R7. In this embodiment, a second capacitor C2, a seventh resistor R7, and a third zener diode D3 are added on the basis of the second embodiment, and the start delay principle and the turn-off maintaining principle of this embodiment are the same as those of the second embodiment, and are not described herein again.
Fourth embodiment
Fig. 7 is a schematic diagram of a delay control circuit according to a fourth embodiment of the present invention, and as shown in the drawing, the present embodiment is different from the second embodiment in that: the control circuit also comprises a third resistor R3, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third capacitor C3, a third zener diode D3, a fourth diode D4 and a second triode Q2, wherein one end of the third resistor R3 is connected with the input end of the control circuit, the cathode of the fourth diode D4, one end of the seventh resistor R7, the cathode of the third zener diode D3 and one end of the second capacitor C2 are connected, the connection point of the three-phase current source is the control end of a control circuit, the other end of a seventh resistor R7 and the anode of a third voltage-stabilizing diode D3 are connected with the base electrode of a second triode Q2, the anode of a fourth diode D4 is connected with one end of an eighth resistor R8, the other end of a third resistor R3 is connected with the collector electrode of a second triode Q2 and the base electrode of a first triode Q1, the other end of the eighth resistor R8 is connected with the output end of the control circuit, the other end of a second capacitor C2 and the emitter electrode of the second triode Q2 are grounded, and a third capacitor C3 is connected between the collector electrode and the emitter electrode of the first triode Q1 in.
When the delay control circuit works stably, the signal output end Vo superposes a voltage on two ends of the second capacitor C2 through the eighth resistor R8 and the fourth diode D4, so that the voltage value V1 of the input voltage signal Vin for controlling the second triode Q2 to be turned from off to on when the delay control circuit is started is larger than the voltage value V2 of the input voltage signal Vin for controlling the second triode Q2 to be turned from on to off when the delay control circuit is turned off, therefore, the return difference of the corresponding input voltage signal Vin when the delay control circuit is started and turned off can be set, and the working stability of the circuit is improved; the third capacitor C3 acts as a decoupling capacitor to prevent the signal at the signal output Vo from being disturbed. The start delay principle and the turn-off maintaining principle of this embodiment are the same as those of the second embodiment, and the temperature drift compensation principle of the third zener diode D3 is the same as that of the third embodiment, which is not described herein again.
The above four embodiments are only preferred embodiments of the present invention, and it should be noted that the above preferred embodiments should not be considered as limitations of the present invention. It will be apparent to those skilled in the art that the above four embodiments of the timing circuit and control circuit switching combination can also achieve the object of the present invention, and that several modifications and improvements can be made without departing from the spirit and scope of the present invention, which are obvious from the prior art, and should be considered as the protection scope of the present invention, and no further description is needed.
Claims (9)
1. A time delay control circuit comprises a timing circuit, a bleeder circuit and a control circuit; the input end of the timing circuit is connected with the input voltage signal Vin, the control output end of the timing circuit is connected with the control end of the control circuit, and the discharge output end of the timing circuit is connected with the input end of the discharge circuit; the output end of the bleeder circuit is connected with an input voltage signal Vin; the input end of the control circuit is connected with an input voltage signal Vin, and the output end of the control circuit is connected with a signal output end Vo to be used as the output end of the whole delay control circuit; the timing circuit comprises a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is an input end of the timing circuit, the other end of the first resistor R1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, and a connection point of the first resistor R1 and the first capacitor C1 is a discharge output end of the timing circuit; the bleeder circuit comprises a first diode D1, wherein the anode of the first diode D1 is the input end of the bleeder circuit, and the cathode of the first diode D1 is the output end of the bleeder circuit; the control circuit comprises a second resistor R2 and a first triode Q1, one end of the second resistor R2 is an input end of the control circuit, the other end of the second resistor R2 is connected with a collector of the first triode Q1, an emitter of the first triode Q1 is grounded, and a connection point of the second resistor R2 and the collector of the first triode Q1 is an output end of the control circuit; the method is characterized in that:
the timing circuit further comprises a seventh resistor R7, one end of the seventh resistor R7 is connected to the other end of the first resistor R1, and the other end of the seventh resistor R7 is used as a control output end of the timing circuit;
the control circuit further comprises a third resistor R3 and a second triode Q2, one end of the third resistor R3 is connected with the input end of the control circuit, the other end of the third resistor R3 is connected with the base electrode of the first triode Q1 and the collector electrode of the second triode Q2, the base electrode of the second triode Q2 is the control end of the control circuit, and the emitter electrode of the second triode Q2 is grounded.
2. The delay control circuit of claim 1, wherein: the control circuit comprises a second capacitor C2, a third voltage-stabilizing diode D3, a first triode Q1, a second resistor R2 and a seventh resistor R7, one end of the second resistor R2 is an input end of the control circuit, the other end of the second resistor R2 is connected with a collector of the first triode Q1 to be an output end of the control circuit, one end of a second capacitor C2, a cathode of the third voltage-stabilizing diode D3 and one end of the seventh resistor R7 are connected, a connection point of the second capacitor C53925 and the cathode of the third voltage-stabilizing diode D3 is a control end of the control circuit, the other end of the seventh resistor R7 and an anode of the third voltage-stabilizing diode D3 are connected with a base of the first triode Q1, and the other end of the second capacitor C2 and an emitter of the first.
3. The delay control circuit of claim 1, wherein: the control circuit comprises a second resistor R2, a third resistor R3, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third voltage-stabilizing diode D3, a fourth diode D4, a first triode Q1 and a second triode Q2, one end of a second resistor R2 and one end of the third resistor R3 are connected with an input end of the control circuit, the cathode of the fourth diode D4, one end of the seventh resistor R7, the cathode of the third voltage-stabilizing diode D3 and one end of a second capacitor C2 are connected, the connection point is a control end of the control circuit, the other end of the seventh resistor R7 and the anode of the third voltage-stabilizing diode D3 are connected with the base of the second triode Q2, the anode of the fourth diode D4 is connected with one end of an eighth resistor R8, the other end of the third resistor R3 is connected with the collector of the second triode Q2 and the base of the first triode Q1, the other end of the first resistor Q1, the collector of the second resistor R8 and the other end of the eighth resistor R2 are connected with an output end of the control, the other end of the second capacitor C2, the emitter of the first transistor Q1, and the emitter of the second transistor Q2 are grounded.
4. The delay control circuit of any one of claims 1 to 3, wherein: the control circuit further includes a third capacitor C3, and the third capacitor C3 is connected in parallel between the collector and emitter of the first transistor Q1.
5. A time delay control circuit comprises a timing circuit, a bleeder circuit and a control circuit; the input end of the timing circuit is connected with the input voltage signal Vin, the control output end of the timing circuit is connected with the control end of the control circuit, and the discharge output end of the timing circuit is connected with the input end of the discharge circuit; the output end of the bleeder circuit is connected with an input voltage signal Vin; the input end of the control circuit is connected with an input voltage signal Vin, and the output end of the control circuit is connected with a signal output end Vo to be used as the output end of the whole delay control circuit; the timing circuit comprises a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is an input end of the timing circuit, the other end of the first resistor R1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, and a connection point of the first resistor R1 and the first capacitor C1 is a discharge output end of the timing circuit; the bleeder circuit comprises a first diode D1, wherein the anode of the first diode D1 is the input end of the bleeder circuit, and the cathode of the first diode D1 is the output end of the bleeder circuit; the control circuit comprises a second resistor R2 and a first triode Q1, one end of the second resistor R2 is an input end of the control circuit, the other end of the second resistor R2 is connected with a collector of the first triode Q1, an emitter of the first triode Q1 is grounded, and a connection point of the second resistor R2 and the collector of the first triode Q1 is an output end of the control circuit; the method is characterized in that:
the timing circuit further comprises a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second zener diode D2, one end of the sixth resistor R6 is connected to a connection point of the first resistor R1 and the first capacitor C1, the other end of the sixth resistor is connected to a cathode of the second zener diode D2 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected with one end of the fifth resistor R5 to serve as a control output end of the timing circuit, and an anode of the second zener diode D2 and the other end of the fifth resistor R5 are grounded.
6. The delay control circuit of claim 5, wherein: the control circuit further comprises a third resistor R3 and a second triode Q2, one end of the third resistor R3 is connected with the input end of the control circuit, the other end of the third resistor R3 is connected with the base electrode of the first triode Q1 and the collector electrode of the second triode Q2, the base electrode of the second triode Q2 is the control end of the control circuit, and the emitter electrode of the third resistor R3 is grounded.
7. The delay control circuit of claim 5, wherein: the control circuit further comprises a second capacitor C2, a third voltage-stabilizing diode D3 and a seventh resistor R7, one end of the second capacitor C2, the cathode of the third voltage-stabilizing diode D3 and one end of the seventh resistor R7 are connected, the connection point of the second capacitor C2 and the cathode of the third voltage-stabilizing diode D3 is the control end of the control circuit, the other end of the seventh resistor R7 and the anode of the third voltage-stabilizing diode D3 are connected with the base electrode of the first triode Q1, and the other end of the second capacitor C2 is grounded.
8. The delay control circuit of claim 5, wherein: the control circuit further comprises a third resistor R3, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, a third zener diode D3, a fourth diode D4 and a second triode Q2, one end of the third resistor R3 is connected with the input end of the control circuit, the cathode of the fourth diode D4, one end of the seventh resistor R7, the cathode of the third zener diode D3 and one end of the second capacitor C2 are connected, the connection point is the control end of the control circuit, the other end of the seventh resistor R7 and the anode of the third zener diode D3 are connected with the base of the second triode Q2, the anode of the fourth diode D4 is connected with one end of the eighth resistor R8, the other end of the third resistor R3 is connected with the collector of the second triode Q2 and the base of the first triode Q1, the other end of the eighth resistor R8 is connected with the output end of the control circuit, and the emitter of the second capacitor C2 and the emitter of the second triode Q2 are grounded.
9. The delay control circuit of any one of claims 5 to 8, wherein: the control circuit further includes a third capacitor C3, and the third capacitor C3 is connected in parallel between the collector and emitter of the first transistor Q1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921343339.6U CN210351116U (en) | 2019-08-19 | 2019-08-19 | Time delay control circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921343339.6U CN210351116U (en) | 2019-08-19 | 2019-08-19 | Time delay control circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510998A (en) * | 2020-11-26 | 2021-03-16 | 武汉美格科技股份有限公司 | Solar MPPT booster unit |
| CN112821344A (en) * | 2021-01-08 | 2021-05-18 | 韦静 | Time-delay suction release control circuit for medical equipment |
-
2019
- 2019-08-19 CN CN201921343339.6U patent/CN210351116U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510998A (en) * | 2020-11-26 | 2021-03-16 | 武汉美格科技股份有限公司 | Solar MPPT booster unit |
| CN112510998B (en) * | 2020-11-26 | 2022-03-11 | 武汉美格科技股份有限公司 | Solar MPPT booster unit |
| CN112821344A (en) * | 2021-01-08 | 2021-05-18 | 韦静 | Time-delay suction release control circuit for medical equipment |
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