CN210348517U

CN210348517U - Display substrate, display panel and display device

Info

Publication number: CN210348517U
Application number: CN201921973515.4U
Authority: CN
Inventors: 许晨
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2019-11-15
Filing date: 2019-11-15
Publication date: 2020-04-17
Anticipated expiration: 2029-11-15

Abstract

The utility model provides a display substrates, display panel and display device. The display substrate comprises an array layer and a light shielding layer, wherein the array layer is positioned on a substrate, the light shielding layer is positioned on one side, far away from the substrate, of the array layer, a plurality of imaging small holes are formed in the light shielding layer, and the first orthographic projection of the imaging small holes on the substrate is not overlapped with the second orthographic projection of active layer patterns of switching transistors in the array layer on the substrate; the switching transistor is a transistor connected to a gate of the driving transistor in the array layer. The utility model discloses can avoid showing the unsafe problem of gray scale.

Description

Display substrate, display panel and display device

Technical Field

The utility model relates to a show technical field, especially relate to a display substrates, display panel and display device.

Background

The prior art has proposed a scheme of integrating fingerprint identification inside a display panel, and the main principle is to use the self-luminous characteristic of an OLED (organic light emitting diode) as a light source for fingerprint identification, when light irradiates a finger, light reflected back by the finger is received by a fingerprint identification module after passing through imaging holes arranged in a back plate, and pattern information of the fingerprint can be obtained after synthetic analysis is performed on images formed by each imaging hole.

The mode of placing OLED display panel in fingerprint identification has improved the screen ratio, but integrated fingerprint identification's display panel shows the homogeneity and shows grey scale accuracy and reduce to some extent, and through analysis discovery, because formation of image aperture department has carried out the printing opacity design, consequently, the light through fingerprint reflection causes the influence to the circuit structure in the backplate especially TFT (thin film transistor) device structure, leads to the degradation of TFT device structure, and then causes and shows the homogeneity and grey scale accuracy reduction.

SUMMERY OF THE UTILITY MODEL

A primary object of the present invention is to provide a display substrate, a display panel and a display device, which are capable of displaying images with high accuracy, and the display substrate, the display panel and the display device are provided with a plurality of light sources, wherein the light sources are arranged in the light source, and the light sources are arranged in the light source.

In order to achieve the above object, the present invention provides a display substrate, including an array layer located on a substrate and a light shielding layer located on one side of the array layer away from the substrate, the light shielding layer being formed with a plurality of imaging apertures, a first orthographic projection of the imaging apertures on the substrate being not overlapped with a second orthographic projection of active layer patterns of switching transistors in the array layer on the substrate;

the switching transistor is a transistor connected to a gate of the driving transistor in the array layer.

In implementation, an orthographic projection of a channel region in an active layer pattern of a control transistor in the array layer on the substrate is a third orthographic projection, and an orthographic projection of a channel region in an active layer pattern of a drive transistor on the substrate is a fourth orthographic projection;

the orthographic projection of a channel region in the active layer pattern of the switching transistor on the substrate is a fifth orthographic projection;

the shortest distance between the edge of the first forward projection and the fifth forward projection is greater than the distance between the edge of the first forward projection and the third forward projection;

the shortest distance between the edge of the first forward projection and the fifth forward projection is greater than the distance between the edge of the first forward projection and the fourth forward projection;

the control transistor is a transistor other than the switching transistor and the driving transistor in the array layer.

In practice, the display substrate comprises a first pixel area provided with an imaging aperture and a second pixel area not provided with the imaging aperture;

the area of the first pixel region is larger than that of the second pixel region.

In practice, the width-to-length ratio of the switching transistor in the first pixel region is smaller than the width-to-length ratio of the switching transistor in the second pixel region.

In practice, the first orthographic projection does not overlap with the orthographic projection of the metal pattern included in the array layer on the substrate.

In practice, the diameter of the imaging aperture is greater than or equal to 2um and less than or equal to 20 um.

In practice, the diameter of the imaging aperture is greater than or equal to 4um and less than or equal to 7 um.

In implementation, the array layer comprises the active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source drain metal layer and a second insulating layer which are sequentially arranged between the substrate and the shading layer; the display substrate further comprises a flat layer and an anode layer which are sequentially arranged on one side, far away from the second insulating layer, of the shading layer;

the light shielding layer comprises a light shielding pattern and a connecting pattern; the shading pattern is provided with the imaging small holes; a light leakage gap is formed between the shading graph and the connecting graph;

the first source drain metal layer is electrically connected with the anode layer through a first through hole penetrating through the second insulating layer, the connecting pattern and a second through hole penetrating through the flat layer;

the orthographic projection of the light leakage gap on the substrate is covered by the orthographic projection of the metal electrode included in the array layer on the substrate.

The utility model also provides a display panel, including foretell display substrate.

The utility model also provides a display device, including foretell display panel.

Compared with the prior art, display substrate, display panel and display device through the formation of image aperture that will form on the light shield layer set up to the active layer figure that does not correspond to the switching transistor in the array layer to make the light that passes the formation of image aperture can not be right the active layer figure of switching transistor causes the influence, thereby can not cause this switching transistor to also have the light to produce the leakage current to exist under the off-state because shining of light, and then can not influence the electric potential of driving transistor's grid, avoid showing the unsafe problem of grey scale.

Drawings

FIG. 1 is a circuit diagram of one embodiment of a pixel drive circuit in a pixel;

FIG. 2 is a timing diagram of the operation of the embodiment of the pixel driving circuit shown in FIG. 1;

fig. 3 is a schematic diagram of an embodiment of a layout of transistors and storage capacitors in a display substrate according to an embodiment of the present invention;

FIG. 4 is a schematic view of the active layer of FIG. 3;

FIG. 5 is a schematic diagram of the first gate metal layer of FIG. 3;

FIG. 6 is a schematic diagram of the second gate metal layer of FIG. 3;

FIG. 7 is a schematic view of the first source drain metal layer of FIG. 3;

FIG. 8 is a schematic diagram of a layout embodiment in which a second source-drain metal layer is added on the basis of FIG. 3;

FIG. 9 is a schematic view of the second source drain metal layer of FIG. 8;

FIG. 10 is a schematic diagram of an embodiment of a layout for adding an anode layer to the layout of FIG. 8;

fig. 11 is a schematic diagram of a layout embodiment of adding a data line, a pixel region and an anode included in an anode layer on the basis of fig. 8.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The transistors adopted in all the embodiments of the utility model can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, to distinguish the two electrodes of the transistor except the control electrode, one of the two electrodes is referred to as a first electrode, and the other electrode is referred to as a second electrode.

In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

The embodiment of the utility model provides a display substrate, including the array layer that is located substrate base plate and be located the array layer keep away from the light shield layer of substrate base plate one side, be formed with a plurality of formation of image apertures on the light shield layer, the formation of image aperture first orthographic projection on substrate base plate and the second orthographic projection on substrate base plate of active layer figure of switch transistor in the array layer are not overlapped;

The embodiment of the utility model provides a display panel set up to the active layer figure that does not correspond to the switching transistor in the array layer through the formation of image aperture that will form on the light shield layer to it can not be right to make the light that passes the formation of image aperture the active layer figure of switching transistor causes the influence, thereby can not cause this switching transistor also to have the light to leak current to exist under the off-state because shining of light, and then can not influence the electric potential of driving transistor's grid, avoids showing the unsafe problem of grey scale.

In an embodiment of the present invention, the first orthographic projection and the second orthographic projection do not overlap and refer to: there is no overlapping portion between the first forward projection and the second forward projection, but not limited thereto.

According to a specific embodiment, the array layer may be a thin film transistor array layer, but is not limited thereto.

According to another specific embodiment, the thin film transistor array layer may include an array layer and a second source-drain metal layer, where the second source-drain metal layer is reused as the light shielding layer, but not limited thereto.

Specifically, an orthographic projection of a channel region in an active layer pattern of the control transistor in the array layer on the substrate is a third orthographic projection, and an orthographic projection of a channel region in an active layer pattern of the drive transistor on the substrate is a fourth orthographic projection;

In a specific implementation, a shortest distance between an edge of the first orthographic projection and the fifth orthographic projection is greater than a distance between the edge of the first orthographic projection and the third orthographic projection, a shortest distance between the edge of the first orthographic projection and the fifth orthographic projection is greater than a distance between the edge of the first orthographic projection and the fourth orthographic projection, and the imaging aperture is farther from a channel region of the active layer pattern of the switching transistor, so that the channel region of the active layer pattern of the switching transistor is prevented from being irradiated by light passing through the imaging aperture.

Specifically, the display substrate may include a first pixel region provided with an imaging aperture and a second pixel region not provided with an imaging aperture;

Preferably, the width-to-length ratio of the switching transistor in the first pixel region may be smaller than the width-to-length ratio of the switching transistor in the second pixel region, so as to reduce a current value of the photo-generated leakage current, and further improve the display gray scale accuracy, but not limited thereto.

In a specific implementation, the first orthographic projection does not overlap with an orthographic projection of a metal pattern included in the array layer on the substrate.

Furthermore, the imaging small hole needs not to be shielded by a metal pattern, so that the accuracy of the small hole imaging fingerprint identification is improved.

In the embodiment of the present invention, the diameter of the imaging aperture may be greater than or equal to 2um and less than or equal to 20um, but not limited thereto.

In a preferred case, the diameter of the imaging aperture may be greater than or equal to 4um and less than or equal to 7um, but not limited thereto.

When specifically implementing, in the display substrate in the utility model provides an in the density of formation of image aperture can be adjusted according to actual conditions is nimble, can set up an formation of image aperture in N pixel region, N is the positive integer.

In a preferred case, N may be greater than or equal to 3 and less than or equal to 10, but is not limited thereto.

Specifically, the array layer may include the active layer, the gate insulating layer, the first gate metal layer, the first insulating layer, the second gate metal layer, the interlayer dielectric layer, the first source drain metal layer, and the second insulating layer, which are sequentially disposed between the substrate and the light shielding layer; the display substrate further comprises a flat layer and an anode layer which are sequentially arranged on one side, far away from the second insulating layer, of the shading layer;

the light shielding layer comprises a light shielding pattern and a connecting pattern; the shading pattern is provided with the imaging small holes;

the first source drain metal layer is electrically connected with the anode layer through a first through hole penetrating through the second insulating layer, the connecting pattern and a second through hole penetrating through the flat layer; a light leakage gap is formed between the connecting pattern and the shading pattern;

the orthographic projection of the light leakage gap on the substrate is covered by the orthographic projection of the metal electrode included in the thin film transistor array layer on the substrate.

In specific implementation, the shading graph and the connecting graph are separated from each other, and the shading graph and the connecting graph are insulated from each other.

In specific implementation, the display substrate according to the embodiment of the present invention may include a substrate, an array layer, a light shielding layer, a planarization layer, and an anode layer, which are sequentially disposed from bottom to top;

the array layer can comprise an active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source drain metal layer and a second insulating layer which are arranged from bottom to top;

in actual operation, the anode layer needs to be electrically connected with the first source drain metal layer, so that the first source drain metal layer is electrically connected with the anode layer through a first through hole penetrating through the second insulating layer, the connecting pattern and a second through hole penetrating through the flat layer by arranging the connecting pattern which is separated from the shading pattern in the shading layer;

and because the shading graph and the connecting graph are insulated, a light leakage gap exists between the shading graph and the connecting graph, and the light leakage gap can leak light, so that the orthographic projection of the light leakage gap on the substrate is covered by the orthographic projection of the metal electrode included in the array layer on the substrate, and the influence of the light exposed through the light leakage gap on the pinhole imaging fingerprint identification is prevented.

The metal electrode may be, for example, an upper plate of a storage capacitor, but is not limited thereto.

Fig. 1 is a circuit diagram of an embodiment of a pixel driving circuit in a pixel.

As shown in fig. 1, an embodiment of the pixel driving circuit may include a driving transistor T1, a first switching transistor T3, a second switching transistor T6, a first control transistor T2, a second control transistor T4, a third control transistor T5, a fourth control transistor T7, and a storage capacitor Cst;

a source T3s of the first switching transistor T3 is electrically connected to a gate T1g of the driving transistor T1, and a drain T3d of the first switching transistor T3 is electrically connected to a drain T1d of the driving transistor T1;

the gate T3g of the first switching transistor T3 is electrically connected to the nth row gate line g (n);

a gate T6g of the second switching transistor T6 is electrically connected to an nth row reset line reset (n), a drain T6d of the second switching transistor T6 is electrically connected to a gate T1g of the driving transistor T1, and a source T6s of the second switching transistor T6 is electrically connected to an initial voltage line Vint;

the gate T2g of the first control transistor T2 is electrically connected to the nth row gate line g (n), the source T2s of the first control transistor T2 is electrically connected to the mth column data line d (m), and the drain T2d of the first control transistor T2 is electrically connected to the source T1s of the driving transistor T1;

the gate T4g of the second control transistor T4 is electrically connected to the nth row emission control line em (n), the source T4s of the second control transistor T4 is electrically connected to the power voltage line ELVDD, and the drain T4d of the second control transistor T4 is electrically connected to the source T1s of the driving transistor T1;

a gate T5g of the third control transistor T5 is electrically connected to an nth row emission control line em (n), a source T5s of the third control transistor T5 is electrically connected to a drain T1d of the driving transistor T1, and a drain T5s of the third control transistor T5 is electrically connected to an anode of the organic light emitting diode OLED; the cathode of the organic light emitting diode OLED is electrically connected with a low voltage line ELVSS;

a gate T7g of the fourth control transistor T7 is electrically connected to a Reset line Reset (n +1) of the (n +1) th row, a drain T7d of the fourth control transistor T7 is electrically connected to an anode of the organic light emitting diode OLED, and a source T7s of the fourth control transistor T7 is electrically connected to a primary voltage line Vint;

the first plate Csa of the storage capacitor Cst is electrically connected to the power voltage line ELVDD, and the gate electrode T1g of the driving transistor T1 may be multiplexed as the second plate Csb of the storage capacitor Cst.

Wherein n is a positive integer and m is a positive integer.

The embodiment of the pixel driving circuit shown in fig. 1 may be a pixel driving circuit in the pixel region of the nth row and the mth column, but is not limited thereto.

In the embodiment of the pixel driving circuit shown in fig. 1, all the transistors are p-type thin film transistors, but not limited thereto.

In fig. 1, the first node N1 is a node electrically connected to the gate of T1.

The pixel driving circuit shown in fig. 1 is only an example of a pixel driving circuit in a pixel, and the structure of the pixel driving circuit is not limited.

In the embodiment of the present invention, the T6 may be a dual gate transistor to reduce the leakage current thereof, and the potential of the gate of the T1 can be kept well, but not limited thereto.

Fig. 2 is an operation timing diagram of the pixel driving circuit shown in fig. 1, wherein t1 is a first phase, t2 is a second phase, and t3 is a third phase, and the data voltage labeled Vdata is provided to the data line d (n).

As shown in fig. 2, the embodiment of the pixel driving circuit shown in fig. 1 is in operation,

in the first stage T1 (i.e. reset stage), reset (n) inputs low level, g (n) inputs high level, em (n) inputs high level, T6 is turned on, and the potential of the gate of T1 is reset to the initial voltage;

in the second stage T2 (i.e. data writing and threshold voltage compensation stage), reset (N) inputs high level, g (N) inputs low level, data (m) inputs data voltage Vdata, em (N) inputs high level, T6 is turned off, T4 and T5 are turned off, T2, T3, T1 and T7 are turned on, Vdata charges Cst through T2, T1 and T3 to raise the potential of the gate of T1 until the potential of the gate of T1 becomes Vdata + Vth (Vth is the threshold voltage of T1), T3 is turned off, the potential of N1 is stored Cst, and T7 is turned on to reset the potential of the anode of the OLED to the initial voltage;

in the third stage T3 (i.e. the light emitting stage), reset (n) is inputted with high level, G (n) is inputted with high level, EM (n) is inputted with low level, T1, T2, T3, T6 and T7 are turned off, T4 and T5 are turned on, OLED emits light, the driving current I for driving OLED to emit light by T1 is equal to (1/2) K (Vdata-Vdd)²(ii) a Where K is the current coefficient and Vdd is the power supply value of the power supply voltage at the ELVDD input.

In the embodiment of the pixel driving circuit shown in fig. 1, the source T3s of T3 is electrically connected to the gate T1g of T1, and the drain T6d of T6 is electrically connected to the gate T1g of T1, if light irradiates on T3 and T6, there may be photo leakage current existing in the off state of T3 and T6, and the potential of the gate T1g of the driving transistor T1 is affected, so that the display gray scale is inaccurate. Based on this, the embodiment of the utility model provides a display substrates of integrated aperture formation of image function has optimized the position and the mode that set up of formation of image aperture, when guaranteeing aperture formation of image fingerprint identification's precision, has reduced the influence of formation of image aperture to showing quality and display accuracy.

In specific implementation, the display substrate may be provided with a specific fingerprint identification area alone, or may be all fingerprint identification areas in a full screen.

The embodiment of the utility model provides an in, display substrates can include from the lower supreme substrate base plate, buffer layer, array layer, the second source drain metal level that sets up, flat layer, anode layer, pixel define layer, luminescent layer and cathode layer. The array layer comprises an active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source drain metal layer and a second insulating layer which are sequentially arranged from bottom to top; wherein the content of the first and second substances,

the first grid metal layer is used for forming structures such as grid lines, light-emitting control lines, grids of transistors in the pixel driving circuit and the like;

the second gate metal layer is used for forming a plate of the storage capacitor and an initial voltage line;

the first source-drain metal layer is used for forming structures such as a data line, a power supply voltage line, a source electrode of each transistor in the pixel driving circuit, a drain electrode of each transistor in the pixel driving circuit and the like;

the second source drain metal layer is reused as a shading layer, and imaging small holes are formed in the shading layer.

In specific implementation, since the anode layer needs to be electrically connected to the first source-drain metal layer to complete the circuit structure, the second source-drain metal layer (i.e., the light shielding layer) needs to be further configured to include a connection pattern, and the first source-drain metal layer is electrically connected to the anode layer through a first via hole penetrating through the second insulating layer, the connection pattern, and a second via hole penetrating through the planarization layer.

In an embodiment of the present invention, the active layer pattern may include, for example, a channel region, a source region, and a drain region. The channel region may not be doped with impurities and thus has semiconductor characteristics. The source region is disposed on a first side of the channel region, and the drain region is disposed on a second side of the channel region, which are opposite sides, and are doped with impurities and thus have conductivity. The impurities may vary depending on whether the transistor is an n-type transistor or a p-type transistor.

The doped source region may correspond to a source electrode of the transistor, and the doped drain region may correspond to a drain electrode of the transistor.

Fig. 3 is a schematic diagram of an embodiment of a layout of a transistor and a storage capacitor in a display substrate according to an embodiment of the present invention, and fig. 3 is composed of an active layer, a first gate metal layer, a second gate metal layer, and a first source drain metal layer from bottom to top.

Fig. 4 is a schematic view of an active layer in fig. 3, fig. 5 is a schematic view of a first gate metal layer in fig. 3, fig. 6 is a schematic view of a second gate metal layer in fig. 3, and fig. 7 is a schematic view of a first source-drain metal layer in fig. 3.

In fig. 3 to 7, Data (m) is a Data line of the m-th column, Data (m +1) is a Data line of the m + 1-th column, ELVDD is a power supply voltage line, Vint is an initial voltage line, Reset (n) is a Reset line of the n-th row, Reset (n +1) is a Reset line of the n + 1-th row, EM (n) is a light-emitting control line of the n-th row, EM (n +1) is a light-emitting control line of the n + 1-th row, G (n) is a gate line of the n-th row, and G (n +1) is a gate line of the n-th row.

In fig. 3 to 7, a channel region of an active layer pattern of T6, which is denoted by reference numeral 16g, a source region of an active layer pattern of T6, which is denoted by reference numeral 16s, a drain region of an active layer pattern of T6, which is denoted by reference numeral 16d, a channel region of an active layer pattern of T3, which is denoted by reference numeral 13g, a channel region of an active layer pattern of T1, which is denoted by reference numeral 11g, a drain region of an active layer pattern of T1, which is denoted by reference numeral 11d, and a source region of an active layer pattern of T1, which is denoted by reference numeral 11 s; a channel region of the active layer pattern of T2, 12g, a source region of the active layer pattern of T2, 14g, T4, 14s, a channel region of the active layer pattern of T4, 15g, a channel region of the active layer pattern of T5, 15d, a drain region of the active layer pattern of T5, 17g, a channel region of the active layer pattern of T7, 17s, a source region of the active layer pattern of T7, Csa, a first plate of the storage capacitor Cst, 16g 'of the active layer pattern of the second switching transistor in the mth column pixel region of row n +1, and 16 d' of the active layer pattern of the second switching transistor in the mth column pixel region of row n + 1.

In fig. 3, reference numeral H0 denotes an imaging pinhole, an orthographic projection of H0 on the underlying substrate does not overlap with an orthographic projection of the active layer pattern of T3 on the underlying substrate, an orthographic projection of H0 on the underlying substrate does not overlap with an orthographic projection of the active layer pattern of T6 on the underlying substrate, and an orthographic projection of H0 on the underlying substrate does not overlap with the active layer pattern of the second switching transistor in the mth column pixel region in the n +1 th row, so that the active layer pattern of T3, the active layer pattern of T6, and the active layer pattern of the second switching transistor in the mth column pixel region in the n +1 th row are not irradiated by light passing through the imaging pinhole H0, thereby preventing photo-generated leakage current from existing in an off state of each switching transistor due to the irradiation of light, further not affecting the gate potential of T1, and avoiding the problem of inaccurate display gray scale.

In fig. 3, the distance d1 between the edge of the orthographic projection of H0 on the substrate base plate and 16 g' is greater than the distance d2 between the edge of the orthographic projection of H0 on the substrate base plate and 15 g.

In the embodiment shown in fig. 3, the shortest distance between the orthographic projection edge of H0 on the substrate base plate and the active layer of T3 is greater than the distance between the orthographic projection edge of H0 on the substrate base plate and the active layer of any transistor other than T3 and T6, and the shortest distance between the orthographic projection edge of H0 on the substrate base plate and the active layer of T6 is greater than the distance between the orthographic projection edge of H0 on the substrate base plate and the active layer of any transistor other than T3 and T6.

And in the layout implementation of the transistor and the storage capacitor in the display substrate according to the embodiment of the present invention shown in fig. 3, 11d is communicated with the source region in the active layer pattern of T5, 15d is communicated with the drain region in the active layer pattern of T7, 16d is communicated with the source region in the active layer pattern of T3, 11s is communicated with the drain region in the active layer pattern of T4, 11d is communicated with the drain region in the active layer pattern of T5, and 11s is communicated with the drain region in the active layer pattern of T2.

In fig. 5, reference numeral T6 g' is the gate of the second switching transistor in the pixel region of the mth column in the (n +1) th row.

In fig. 5, a gate denoted by T1 denoted by T1g, a gate denoted by T2 denoted by T2g, a gate denoted by T3 denoted by T3g, a gate denoted by T4 denoted by T4g, a gate denoted by T5 denoted by T5g, a gate denoted by T6 denoted by T6g, and a gate denoted by T7 denoted by T7 g.

In fig. 3 and 7, the cross-hatching of the boxes indicates vias.

In fig. 7, vertical lines in the longitudinal direction other than the data lines and the power supply voltage lines are connection lines.

The embodiment of the utility model provides a display substrate optimize formation of image aperture design position, when keeping aperture formation of image discernment precision, reduced aperture imaging system to showing the quality, especially show the influence of precision, promoted the demonstration quality.

As shown in fig. 8, a second source-drain metal layer is added to the schematic diagram of the layout embodiment shown in fig. 3; in fig. 8, a light leakage slit is denoted by F1, and a connection pattern included in the first source-drain metal layer is denoted by L1; fig. 9 shows the second source-drain metal layer in fig. 8, and in fig. 9, a connection pattern included in the second source-drain metal layer is denoted by reference numeral L0; a shading graph included by the second source drain metal layer is marked as SE, an imaging pinhole is marked as H0, and a light leakage gap is marked as F1;

the connection pattern L1 included by the first source-drain metal layer is used for electrically connecting the drain electrode of the T5 with the connection pattern L0 included by the second source-drain metal layer;

and the connection pattern L0 included by the second source-drain metal layer is used for electrically connecting the connection pattern L1 included by the second source-drain metal layer with the anode layer.

As shown in fig. 10, an anode layer is added to the schematic diagram of the layout embodiment shown in fig. 8; in fig. 10, reference numeral An1 is a first anode included in the anode layer, reference numeral An2 is a second anode included in the anode layer, reference numeral An3 is a third anode included in the anode layer, reference numeral An4 is a fourth anode included in the anode layer;

the first anode An1 included in the anode layer is electrically connected to the drain of the T5 through the connection pattern L0 included in the second source-drain metal layer and the connection pattern L1 included in the first source-drain metal layer.

In fig. 11, on the basis of the schematic diagram of the layout embodiment shown in fig. 10, the m +2 th column Data line Data (m +2), the m +3 th column Data line Data (m +3), and two column power voltage lines are added, and a fifth anode An5 included in the anode layer, a sixth anode An6 included in the anode layer, and a seventh anode An7 included in the anode layer are also added.

In fig. 11, An1 may be An anode of a blue organic light emitting diode, An5 may be An anode of a red organic light emitting diode, and An7 may be An anode of a green organic light emitting diode, but not limited thereto.

In fig. 11, the imaging aperture H0 is provided in the pixel region surrounded by Reset (n), Reset (n +1), D (m), and D (m +1), but not limited thereto.

As shown in fig. 8 and 9, a certain distance is required between the imaging aperture H0 and the connection pattern L0, and the orthographic projection of the light leakage aperture F1 between the connection pattern L0 and the light shielding pattern SE on the substrate needs to be covered by the orthographic projection of the metal electrode (for example, the plate of the storage capacitor) included in the array layer on the substrate, however, due to the limitation of the manufacturing accuracy, the width of the light leakage aperture F1 cannot be infinitely narrow, the radius of the imaging aperture H0, the size of the connection pattern L0, and the distance between the imaging aperture H0 and the connection pattern L0 are also limited by the manufacturing accuracy, and therefore, the area of each pattern of the pixel region provided with the imaging aperture can be appropriately enlarged compared with the area of each pattern of the pixel region not provided with the imaging aperture, so as to ensure that the orthographic projection of the light leakage aperture F1 between the connection pattern L0 and the light shielding pattern SE on the substrate needs to be covered by the metal electrode (for example, the metal electrode included in the array layer The plates of the storage capacitor) is overlaid on the substrate in an orthographic projection.

The embodiment of the utility model provides a display panel include foretell display substrate.

The embodiment of the utility model provides a display device include foretell display panel.

The embodiment of the utility model provides a display device can be any products or parts that have the display function such as cell-phone, panel computer, TV set, display, notebook computer, digital photo holder frame, navigator.

The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A display substrate is characterized by comprising an array layer and a light shielding layer, wherein the array layer is positioned on a substrate, the light shielding layer is positioned on one side, far away from the substrate, of the array layer, a plurality of imaging small holes are formed in the light shielding layer, and a first orthographic projection of the imaging small holes on the substrate is not overlapped with a second orthographic projection of an active layer pattern of a switching transistor in the array layer on the substrate;

2. The display substrate according to claim 1, wherein an orthographic projection of a channel region in the active layer pattern of the control transistor in the array layer on the substrate is a third orthographic projection, and an orthographic projection of a channel region in the active layer pattern of the drive transistor on the substrate is a fourth orthographic projection;

3. The display substrate of claim 1, wherein the display substrate comprises a first pixel region provided with an imaging aperture and a second pixel region not provided with an imaging aperture;

4. The display substrate according to claim 3, wherein a width-to-length ratio of the switching transistor in the first pixel region is smaller than a width-to-length ratio of the switching transistor in the second pixel region.

5. The display substrate of claim 1, wherein the first orthographic projection does not overlap with an orthographic projection of a metal pattern included in the array layer on the substrate base.

6. The display substrate of claim 1, wherein the imaging apertures have a diameter greater than or equal to 2um and less than or equal to 20 um.

7. The display substrate of claim 6, wherein the imaging apertures have a diameter greater than or equal to 4um and less than or equal to 7 um.

8. The display substrate of claim 1, wherein the array layer comprises the active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source drain metal layer and a second insulating layer sequentially arranged between the substrate and the light shielding layer; the display substrate further comprises a flat layer and an anode layer which are sequentially arranged on one side, far away from the second insulating layer, of the shading layer;

9. A display panel comprising the display substrate according to any one of claims 1 to 8.

10. A display device characterized by comprising the display panel according to claim 9.