CN210325758U - Integrated chip for mobile communication equipment - Google Patents

Integrated chip for mobile communication equipment Download PDF

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Publication number
CN210325758U
CN210325758U CN201921528316.2U CN201921528316U CN210325758U CN 210325758 U CN210325758 U CN 210325758U CN 201921528316 U CN201921528316 U CN 201921528316U CN 210325758 U CN210325758 U CN 210325758U
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integrated chip
pin
pins
mobile communication
wafer
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CN201921528316.2U
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Chinese (zh)
Inventor
谢思坦
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Shenzhen Aoli Electronic Co Ltd
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Shenzhen Aoli Electronic Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Semiconductor Integrated Circuits (AREA)

Abstract

The utility model discloses an integrated chip for mobile communication equipment, which is characterized in that the integrated chip comprises a main control unit and a storage unit which are arranged around the periphery of the main body of the integrated chip and are integrated and packaged in the central area inside the main body of the integrated chip, thereby reducing the number of electronic components of a main board, saving materials, reducing the occupied area of a PCB board, further reducing the production cost and saving the production process; and simultaneously, the main control unit has a plurality of pins, and its pin is connected to the pin that the integrated chip periphery corresponds with the arc height that is higher than substrate 200um ~ 300um through the copper line, memory cell has a plurality of pins, and its pin is connected to the pin that the integrated chip periphery corresponds with the arc height that is higher than substrate 100 ~ 200um through the copper line, the utility model discloses the high low arc of novelty use is managed and is controlled for there is crossed copper line 100um distance that staggers on the plan view, thereby has avoided the copper line to cross, has guaranteed the success rate of integrated package.

Description

Integrated chip for mobile communication equipment
Technical Field
The utility model belongs to the technical field of wireless communication, more specifically relates to an integrated chip for mobile communication equipment.
Background
The interphone is a two-way mobile communication tool, and has the characteristics of being capable of communicating without any network support and generating no telephone charge, so that the interphone is widely applied to relatively fixed and frequent communication occasions.
In order to realize the functions of a common interphone, a main board of the common interphone usually comprises a singlechip, an EEPROM and other functional chips with independent functions, but most of the functional chips in the prior art are independently designed and packaged; such independent packaging, on the one hand, is not conducive to the optimal design of the functional chip, for example, some unusual functions are removed according to actual needs and the chip is redesigned for the deleted functions to achieve the optimal design; on the other hand, each functional chip is independently packaged, so that the problems of limited working efficiency of the mainboard, high production cost and the like are caused.
With the increasing maturity of communication technology, how to realize that communication equipment has the characteristics of lightness, thinness, shortness, multiple functions, low power consumption and the like through the integration and integration of multiple functional chips is an important development trend.
Disclosure of Invention
To the above defect or the improvement demand of prior art, the utility model provides an integrated chip for mobile communication equipment, its aim at is through being in the same place EEPROM and singlechip integration, solves the electronic components that exists among the prior art from this and is in large quantity, PCB version occupation space is big, technical problem that manufacturing cost is high.
To achieve the above object, according to one aspect of the present invention, there is provided an ic chip for a mobile communication device, comprising a main control unit and a memory unit integrally packaged in a central region inside an ic chip body, surrounding a plurality of pins disposed at an outer periphery of the ic chip body; wherein:
the main control unit is provided with a plurality of pins, and the pins of the main control unit are connected to the pins corresponding to the periphery of the integrated chip through copper wires at the arc height which is 200 um-300 um higher than the substrate, so that the main control unit is electrically connected with the substrate circuit;
the memory cell has a plurality of pins, the pin of memory cell is connected to the corresponding pin of integrated chip peripherad through the copper line with the arc height that is higher than substrate 100 ~ 200um to make memory cell and base plate circuit electricity be connected.
Preferably, the memory unit of the integrated chip for mobile communication equipment is an EEPROM wafer.
Preferably, the integrated chip for the mobile communication device has an EEPROM wafer model P24C 02.
Preferably, the main control unit of the integrated chip for the mobile communication device is a single chip microcomputer wafer.
Preferably, the single chip microcomputer wafer of the integrated chip for the mobile communication device is an 8-bit single chip microcomputer wafer.
Preferably, the integrated chip for the mobile communication device has a single chip microcomputer with a wafer model number of HNST 1602.
Preferably, the main control unit and the memory unit of the integrated chip for mobile communication device are integrally packaged in the central area inside the main body of the integrated chip in a TSSOP manner.
Preferably, the integrated chip for the mobile communication device is provided with 20 pins around the outer periphery of the main body of the integrated chip.
Generally, through the utility model discloses above technical scheme who conceives compares with prior art, can gain following beneficial effect:
(1) the utility model discloses an integrate and encapsulate storage unit and main control unit in an integrated chip, use the chip after the integration in relevant field in order to realize same function to solved each function chip and divided into independent chip respectively among the prior art and lead to mainboard electronic components in large quantity, PCB version occupation space big, technical problem such as manufacturing cost height, the utility model discloses reduced mainboard electronic components quantity, practiced thrift the material, reduced PCB board area occupied, and then reduced manufacturing cost, practiced thrift production technology;
(2) the utility model provides an integrated chip for mobile communication equipment, which is characterized in that pins of a main control unit are connected to pins corresponding to the periphery of the integrated chip through copper wires with the arc height higher than 200 um-300 um of a substrate, so that the main control unit is electrically connected with a substrate circuit; pins of a storage unit of the chip are connected to pins corresponding to the outer periphery of the integrated chip through copper wires with arc heights higher than 100-200 um of a substrate, so that the storage unit is electrically connected with a substrate circuit, high-low arc control is innovatively used, and crossed copper wires are staggered by a distance of 100um on a top view on a chip thickness coordinate, so that copper wire crossing is avoided, the success rate of integrated packaging is guaranteed, the stability of communication is guaranteed, and interference caused by crossing is avoided;
(3) in the preferred scheme, the main control unit and the storage unit are integrally packaged in the central area inside the integrated chip main body in a TSSOP mode, so that the volume of the integrated chip is smaller, the occupied area of a PCB is further saved, and the production cost is further reduced.
Drawings
Fig. 1 is a schematic structural diagram of an integrated chip according to embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Furthermore, the technical features mentioned in the embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
With the increasing maturity of communication technology, how to realize lightness, thinness, shortness and smallness of mobile communication equipment is an important development trend; the main board of the two-way mobile communication equipment such as an interphone generally comprises a signal transmitting unit, a signal receiving unit and a singlechip so as to realize signal control and processing and provide a small-capacity storage function and the like; however, because the storage capacity of the single chip is limited, for the interphone with frequent calls, the storage capacity of the interphone cannot completely meet the storage requirement of the interphone, and because the EEPROM (electrically Erasable Programmable read only memory) has the characteristic of plug and play, the existing information can be erased and reprogrammed on a computer or special equipment; therefore, the single chip microcomputer is generally combined with the mobile communication field such as an interphone and the like to solve the problem that the communication is affected due to insufficient storage capacity of the single chip microcomputer.
In the present interphone mainboard, each functional module is respectively packaged into an independent chip, and the integration of the chips cannot be realized, so that the technical problems of large quantity of electronic components of the mainboard, large occupied space of a PCB (printed circuit board) version, high production cost and the like are caused.
In order to solve the above problems, the present invention provides an integrated chip for mobile communication device, as shown in fig. 1, including a plurality of pins surrounding the outer periphery of the integrated chip main body and a main control unit and a storage unit integrally packaged in the central region inside the integrated chip main body;
specifically, the integrated chip comprises a substrate and an integrated chip main body arranged on the substrate, wherein a plurality of pins are arranged on the periphery of the integrated chip main body in a surrounding mode, a main control unit and a storage unit are integrally packaged in the inner center area of the integrated chip main body, and the main control unit and the storage unit are both arranged on the substrate.
The utility model discloses an integrate and encapsulate storage unit and main control unit in an integrated chip, use the chip after the integration in relevant field in order to realize same function to solved each function chip and divided into independent chip respectively among the prior art and lead to mainboard electronic components in large quantity, PCB version occupation space big, technical problem such as manufacturing cost height, the utility model discloses reduced mainboard electronic components quantity, practiced thrift the material, reduced PCB board area occupied, and then reduced manufacturing cost, practiced thrift production technology; more specifically, the utility model provides an integrated chip for mobile communication equipment, can make PCB face area save 4mm 5mm at least;
the main control unit is preferably a singlechip wafer and comprises 18 pins, and the pins of the main control unit are connected to the pins corresponding to the periphery of the integrated chip through copper wires at the arc height higher than 200-300 um of the substrate so as to electrically connect the main control unit with the substrate circuit; the PCB circuit can be physically connected with the singlechip wafer through the pins corresponding to the periphery of the integrated chip, so that the singlechip wafer normally works; the single chip microcomputer wafer is electrically connected with a circuit of the PCB, so that when the integrated chip is powered on, the integrated chip can realize the functions of IO pin control, data reading and writing and the like;
further, the main control unit is preferably an 8-bit single chip microcomputer wafer, so as to reduce the cost while meeting the actual working requirement under the condition of the same IO number, and the model of the main control unit is preferably an 8-bit single chip microcomputer wafer HNST 1602.
The memory cell is preferably an EEPROM wafer, which comprises 8 pins, the pins of the memory cell are connected to the pins corresponding to the periphery of the integrated chip through copper wires with the arc height higher than the substrate by 100-200 um so as to electrically connect the memory cell with a substrate circuit, wherein the substrate circuit is a PCB circuit, and in an actual use environment, the PCB circuit can pass through the pins corresponding to the periphery of the integrated chip and the EEPROM wafer, so that the EEPROM wafer normally works and meets the mobile two-way communication memory requirements of interphones and the like; the EEPROM wafer is electrically connected with the PCB circuit, so that when the power is on, the integrated chip can erase and rewrite data, the memory is guaranteed to the maximum extent, and the practicability is improved;
further, the model of the storage unit is preferably P24C 02.
The utility model connects the pins of the main control unit to the corresponding pins at the periphery of the integrated chip by copper wires with the arc height higher than 200um to 300um of the substrate, so that the main control unit is electrically connected with the substrate circuit; pins of a storage unit of the chip are connected to pins corresponding to the outer periphery of the integrated chip through copper wires with arc heights higher than 100-200 um of a substrate, so that the storage unit is electrically connected with a substrate circuit, high-low arc control is innovatively used, and crossed copper wires are staggered by a distance of 100um on a top view on a chip thickness coordinate, so that copper wire crossing is avoided, the success rate of integrated packaging is guaranteed, the stability of communication is guaranteed, and interference caused by crossing is avoided;
in the prior art, common integrated packaging methods include SIP, DIP and SDIP; the SIP is a single-in-line package, pins are led out from one side surface of the package and are arranged into a straight line, the center distance of the pins is usually 2.54mm, the number of the pins is 2-23, and the SIP is mainly applied to customized products; DIP is a dual in-line package, the packaging mode is that pins are led out from two sides of the package, the pin center distance is 2.54mm, the pin number is from 6 to 64, the packaging width is usually 15.2mm, and the main application range comprises a standard logic IC, a memory LSI, a microcomputer circuit and the like; SDIP is a contracted type DIP, which has the same shape as DIP, but has a center-to-center pin pitch (1.778mm) smaller than DIP (2.54mm), and has a pin count of 14 to 90, and its main application is similar to DIP.
For the interphone mainboard, the area of the mainboard is smaller, so that the occupied PCB space after the chip is packaged is required to be smaller, and therefore, the size of the integrated chip can be reduced to a greater extent by selecting a TSSOP packaging mode (TSSOP is an abbreviation of Thin Small Outline Package);
specifically, the main control unit and the storage unit of the integrated chip for the mobile communication device are integrally packaged in the central area inside the main body of the integrated chip in a TSSOP mode, so that the volume of the integrated chip is smaller, the occupied area of a PCB is further saved, and the production cost is further reduced.
The periphery of the main body of the integrated chip is provided with 20 pins in a surrounding way, and the pins are connected to a main board circuit of the mobile communication equipment so as to realize multiple functions of data processing, data storage and the like;
particularly, because of its integration have singlechip wafer and EEPROM wafer, and singlechip wafer and EEPROM wafer equally divide and do not be connected to outside base plate circuit through the pin, consequently, it has singlechip and EEPROM wafer all independent functions separately, promptly, the utility model provides an integrated chip, its pin carry out the erasing of data and write again through the voltage that PCB board circuit provided, furthest has ensured the memory, has improved the practicality; meanwhile, the pins of the PCB realize the functions of IO pin control, data reading and writing and the like through a circuit of the PCB.
The following is further illustrated with reference to the examples:
as shown in fig. 1, the present invention provides an integrated chip for a mobile communication device, hereinafter designated TSSOP 20L; as shown in fig. 1, the integrated chip comprises a plurality of pins arranged around the outer periphery of the integrated chip body and a main control unit and a storage unit integrally packaged in the inner central area of the integrated chip body;
the main control unit is an 8-bit single chip microcomputer wafer HNST1602, which includes 18 pins, in this embodiment, the specific connection relationship between the pins of the single chip microcomputer wafer and the corresponding pins at the outer periphery of the integrated chip is as follows:
pin 19 of the HNST1602 wafer is connected to pin 17 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 18 of the HNST1602 wafer is connected to pin 16 of the TSSOP20L frame using copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 17 of the HNST1602 wafer is connected to pin 15 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 16 of the HNST1602 wafer is connected to pin 14 of the TSSOP20L frame using copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 15 of the HNST1602 wafer is connected to pin 13 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 14 of the HNST1602 wafer is connected to pin 12 of the TSSOP20L frame using copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 13 of the HNST1602 wafer is connected to pin 11 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 12 of the HNST1602 wafer is connected to pin 10 of the TSSOP20L frame using copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 11 of the HNST1602 wafer is connected to pin 9 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 10 of the HNST1602 wafer is connected to pin 8 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 9 of the HNST1602 wafer is connected to the metal frame (ground) of the TSSOP20L frame using copper wires; the arc height of the copper wire is 200um higher than that of the substrate;
pin 8 of the HNST1602 wafer is connected to pin 7 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 7 of the HNST1602 wafer is connected to pin 5 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 6 of the HNST1602 wafer is connected to pin 4 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 5 of the HNST1602 wafer is connected to pin 3 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 4 of the HNST1602 wafer is connected to pin 2 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 3 of the HNST1602 wafer is connected to pin 1 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
pin 2 of the HNST1602 wafer is connected to pin 20 of the TSSOP20L frame using copper wire; the arc height of the copper wire is 300um higher than that of the substrate;
pin 1 of the HNST1602 wafer is connected to pin 18 of the TSSOP20L frame using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
the memory cell is an EEPROM wafer, which is P24C02 type and includes 8 pins, and in this embodiment, the specific connection relationship between the EEPROM wafer pins and the pins corresponding to the outer periphery of the ic is as follows:
the VDD pin of the P24C02 wafer is connected with the pin 19 of the TSSOP20L frame by a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
the SCL pin of the P24C02 wafer is connected to pin 20 of the TSSOP20L frame using copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
the SDA pin of the P24C02 wafer is connected with pin 1 of the TSSOP20L frame by using a copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
the VSS pin of the P24C02 wafer is connected to the metal frame (ground) of the TSSOP20L frame using copper wire; the arc height of the copper wire is 200um higher than that of the substrate;
TSSOP20L frame pins 14 are connected to the metal frame (ground) of TSSOP 20L;
the copper wires connected with the SCL pin of the P24C02 wafer and the pin 20 of the TSSOP20L frame and the copper wires connected with the VDD pin of the P24C02 wafer and the pin 19 of the TSSOP20L frame are crossed in a top view, so that high-low arc control is adopted, namely two copper wires are staggered by a distance of 100um on a chip thickness coordinate;
when pin 2 of the HNST1602 wafer is connected with pin 20 of the TSSOP20L frame by using a copper wire and the arc height of the copper wire is higher than 200um of the substrate, the VDD pin of the P24C02 wafer is connected with pin 19 of the TSSOP20L frame by using a copper wire and the arc height of the copper wire is higher than 100um of the substrate; to form high-low arc control, namely two copper wires are staggered by a distance of 100um on a thickness coordinate of the chip;
the main control unit and the storage unit of the integrated chip are integrated and packaged in the central area in the main body of the integrated chip in a TSSOP mode, 20 pins are arranged around the outer periphery of the main body of the integrated chip, and the pins are connected to a main board circuit of the mobile communication equipment so as to realize multiple functions of data processing, data storage and the like;
specifically, the integrated chip is integrated with the singlechip wafer and the EEPROM wafer, and the singlechip wafer and the EEPROM wafer are respectively connected to the external substrate circuit through pins, so that the integrated chip has all independent functions of the singlechip and the EEPROM wafer;
when in work: the utility model provides an integrated chip, it is connected to intercom mainboard circuit through the pin of peripheral, and its inside singlechip wafer HNST1602 is connected to outside mainboard circuit and power-on work through its pin, begins to carry out the application that the user wrote and writes in it, and controls the IO pin of HNST 1602; meanwhile, reading and writing operations are performed on the P24C02 according to program requirements; because the memory of singlechip is limited, can't satisfy the frequent dialogue demand of intercom, consequently, the utility model provides an integrated chip, its inside EEPROM wafer P24C02 is through being connected to outside mainboard circuit through its pin and go up electric work, begins to carry out electrified erasing and programming repeatedly of data to satisfy the data storage demand.
It will be understood by those skilled in the art that the foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. An integrated chip for a mobile communication device, comprising a plurality of pins arranged around the outer periphery of an integrated chip body and a main control unit and a storage unit integrally packaged in the inner central area of the integrated chip body; wherein:
the main control unit is provided with a plurality of pins, and the pins of the main control unit are connected to the pins corresponding to the periphery of the integrated chip through copper wires at the arc height which is 200 um-300 um higher than the substrate, so that the main control unit is electrically connected with the substrate circuit;
the memory cell has a plurality of pins, the pin of memory cell is connected to the corresponding pin of integrated chip peripherad through the copper line with the arc height that is higher than substrate 100 ~ 200um to make memory cell and base plate circuit electricity be connected.
2. The integrated chip for a mobile communication device of claim 1, wherein said memory cells are EEPROM wafers.
3. The integrated chip for a mobile communication device of claim 2, wherein said EEPROM wafer model is P24C 02.
4. The integrated chip for a mobile communication device of claim 1, wherein the master control unit is a single chip microcomputer wafer.
5. The integrated chip for mobile communication device of claim 4, wherein said monolithic chip is an 8-bit monolithic chip wafer.
6. The integrated chip for mobile communication device of claim 4 or 5, wherein said single chip microcomputer wafer model is HNST 1602.
7. The integrated chip for mobile communication device according to claim 1, wherein the main control unit and the memory unit are integrally packaged in the central region inside the integrated chip body by TSSOP.
8. The integrated chip for a mobile communication device according to claim 1, wherein the integrated chip body outer periphery is circumferentially provided with 20 pins.
CN201921528316.2U 2019-09-16 2019-09-16 Integrated chip for mobile communication equipment Active CN210325758U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201921528316.2U CN210325758U (en) 2019-09-16 2019-09-16 Integrated chip for mobile communication equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201921528316.2U CN210325758U (en) 2019-09-16 2019-09-16 Integrated chip for mobile communication equipment

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CN210325758U true CN210325758U (en) 2020-04-14

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