CN204516361U

CN204516361U - Embedded storage chip, EMBEDDED AVIONICS

Info

Publication number: CN204516361U
Application number: CN201520031836.8U
Authority: CN
Inventors: 李志雄; 邓恩华
Original assignee: Shenzhen Netcom Electronics Co Ltd
Current assignee: Shenzhen Netcom Electronics Co Ltd
Priority date: 2015-01-16
Filing date: 2015-01-16
Publication date: 2015-07-29
Anticipated expiration: 2025-01-16

Abstract

The utility model relates to a kind of embedded storage chip, comprise body, be arranged on the first interface contact on body, be encapsulated in intrinsic control integration circuit die and Nand Flash storage integrated-circuit die, described Nand Flash stores integrated-circuit die and first interface contact is electrically connected with control integration circuit die respectively; Described control integration circuit die is provided with SPI interface, described body is also provided with SPI interface contact, described SPI interface contact is electrically connected with described SPI interface, at least comprises power lead, ground wire, DOL Data Output Line, Data In-Line, chip select line, clock line 6 contacts.Above-mentioned embedded storage chip, control integration circuit die is set up SPI interface, code data required when external electronic device can be started by SPI interface quick obtaining, thus make external electronic device no longer need to configure a SPI Nor Flash memory chip in addition, reduce the production cost of external electronic device.

Description

Embedded storage chip, EMBEDDED AVIONICS

Technical field

The utility model relates to memory device, particularly relates to a kind of embedded storage chip, EMBEDDED AVIONICS.

Background technology

Existing EMBEDDED AVIONICS is as intelligent watch, Intelligent bracelet etc., function gets more and more, but the space holding internal circuit truly has limit, and product is more and more towards lightening, the future development of miniaturization, therefore more and more higher to the integration level necessitates of embedded chip, and existing embedded storage chip in use, all need to configure a SPI Nor Flash memory chip more in addition to store some start-up code supervisors, like this, because embedded storage chip and SPI Nor Flash memory chip all need to occupy certain area on a printed circuit, therefore restriction is caused to the further miniaturization of electronic product.And need employing two kinds of storage chips due to EMBEDDED AVIONICS such as described intelligent watch, Intelligent bracelet, the inevitable cost that also can raise described EMBEDDED AVIONICS.

Utility model content

Based on this, be necessary the problem causing restriction for existing embedded storage chip structure to the further miniaturization of EMBEDDED AVIONICS, the embedded storage chip that is novel is provided.

In addition, there is a need to provide a kind of novel EMBEDDED AVIONICS.

A kind of embedded storage chip, comprise body, be encapsulated in intrinsic control integration circuit die and Nand Flash storage integrated-circuit die, and the first interface contact be arranged on body, described control integration circuit die is provided with first interface, described Nand Flash stores integrated-circuit die and is electrically connected with described control integration circuit die, described first interface contact is electrically connected with described first interface, described control integration circuit die is also provided with the second interface, described embedded storage chip also comprises the second interface contact be electrically connected with described second interface be arranged on body, described second interface is SPI interface, described second interface contact is SPI interface contact, described second interface contact at least comprises power lead, ground wire, DOL Data Output Line, Data In-Line, chip select line, clock line 6 contacts.

In a specific embodiment, described second interface contact also comprises state maintaining line contact and write-protect line contact.

In a specific embodiment, described first interface is SD interface, described first interface contact is SD interface contact, and described first interface contact at least comprises power lead, ground wire, data line 0, data line 1, data line 2, data line 3, clock line, order wire eight contacts.

In a specific embodiment, described first interface is USB interface, and described first interface contact is USB interface contact, and described first interface contact at least comprises power lead, ground wire, correction data line, negative data line four contacts.

In a specific embodiment, described first interface is eMMC interface, described first interface contact is eMMC interface contact, and described first interface contact at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.

In a specific embodiment, the body of described embedded storage chip is provided with 30 contacts, except first interface contact and the second interface contact, also comprise the power cord point of core power line contact and reservation, all the other contacts are the stick contact temporarily do not used.

In a specific embodiment, described embedded storage chip length is of a size of 8mm*8mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.

In a specific embodiment, described embedded storage chip length is of a size of 8mm*7.5mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.

In a specific embodiment, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described contact is circular pad contact or spherical contact or dome shaped contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.

A kind of EMBEDDED AVIONICS, comprises embedded storage chip described above.

Above-mentioned embedded storage chip, EMBEDDED AVIONICS, by arranging a SPI interface on control integration circuit die, the start-up code of external electronic device can be stored in Nand Flash stores in the storage space that provides of integrated-circuit die, code data required when external electronic device can be started by SPI interface quick obtaining, thus make external electronic device no longer need to configure a SPI Nor Flash memory chip in addition, reduce the production cost of external electronic device; Meanwhile, owing to decreasing the use of SPI Nor Flash memory chip, the area that external electronic device printed circuit board (PCB) takies can be reduced, be convenient to the Miniaturization Design of external electronic device; Further, because described embedded storage chip possesses first interface, therefore described external electronic device can copy ROMPaq the upgrading of to described embedded storage chip copy by first interface, relative to the mode that traditional SPI Nor Flash memory chip is upgraded by burning, greatly facilitate the use of domestic consumer.

Accompanying drawing explanation

Fig. 1 is the electrical block diagram of embedded storage chip in an embodiment;

Fig. 2 is the pad distribution schematic diagram of embedded storage chip in an embodiment;

Fig. 3 is the physical dimension schematic diagram of embedded storage chip in an embodiment.

Embodiment

In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.

Fig. 1 is the electrical block diagram of embedded storage chip in an embodiment; Fig. 2 is the pad distribution schematic diagram of embedded storage chip in an embodiment.As depicted in figs. 1 and 2, this embedded storage chip 10, comprise body 105, be encapsulated in the control integration circuit die 101 in body 105 and Nand Flash storage integrated-circuit die 102, and the first interface contact 103 be arranged on body, described control integration circuit die 101 is provided with first interface, described Nand Flash stores integrated-circuit die 102 and is electrically connected 101 with described control integration circuit die, described first interface contact 103 is electrically connected with described first interface, described control is formed circuit die 101 and is also provided with the second interface, described embedded storage chip 10 also comprises the second interface contact 104 be electrically connected with described second interface be arranged on described body 105, described second interface is SPI interface, described second interface contact 104 is SPI interface contact, described second interface contact 104 at least comprises power lead (SPI-VCC), ground wire (GND), DOL Data Output Line (SPI-DO), Data In-Line (SPI-DI), chip select line (SPI-CS), clock line (SPI-CLK) 6 contacts.

In a specific embodiment, as shown in Figure 2, described second interface contact 104 also comprises state maintaining line contact (SPI-HOLD) and write-protect line contact (SPI-WP).

In a specific embodiment, as shown in Figure 2, described first interface is SD interface, described first interface contact 103 is SD interface contact, and described first interface contact 103 at least comprises power lead (VCCSD), ground wire (GND), data line 0 (SDD0), data line 1 (SDD1), data line 2 (SDD2), data line 3 (SDD3), clock line (SDCLK), order wire (SDCMD) eight contacts.

In a specific embodiment, described first interface is USB interface, and described first interface contact 103 is USB interface contact, and described first interface contact 103 at least comprises power lead, ground wire, correction data line, negative data line four contacts.

In a specific embodiment, described first interface is eMMC interface, described first interface contact 103 is eMMC interface contact, and described first interface contact 103 at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.

In a specific embodiment, as shown in Figure 2, the body 105 of described embedded storage chip 10 is provided with 30 contacts, except first interface contact 103 and the second interface contact 104, the power cord point (VCCS) also comprising core power line contact (VDDK) and retain, all the other contacts are the stick contact (DNU) temporarily do not used.

In a specific embodiment, as shown in Figure 3, described embedded storage chip is of a size of 8mm*8mm*0.8mm (mm:millimeter millimeter), and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.Certain described embedded storage chip also can be other sizes, at this not in order to limit the utility model.

In a specific embodiment, as shown in Figure 3, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described contact is circular pad contact or spherical contact or dome shaped contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, and the 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.Certainly, described contact also can be other shapes, at this not in order to limit the utility model.

In another specific embodiment, the size of described embedded storage chip length can also be 8mm*7.5mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.

Above-mentioned embedded storage chip, by arranging a SPI interface on control integration circuit die, the start-up code of external electronic device can be stored in Nand Flash stores in the storage space that provides of integrated-circuit die, code data required when external electronic device can be started by SPI interface quick obtaining, thus make external electronic device no longer need to configure a SPI Nor Flash memory chip in addition, reduce the production cost of external electronic device; Meanwhile, owing to decreasing the use of SPI Nor Flash memory chip, the area that external electronic device printed circuit board (PCB) takies can be reduced, be convenient to the Miniaturization Design of external electronic device; Further, because described embedded storage chip possesses first interface, therefore described external electronic device can copy ROMPaq the upgrading of to described embedded storage chip copy by first interface, relative to the mode that traditional SPI Nor Flash memory chip is upgraded by burning, greatly facilitate the use of domestic consumer.

The utility model also provides a kind of EMBEDDED AVIONICS, and this EMBEDDED AVIONICS comprises embedded storage chip described above.

Described EMBEDDED AVIONICS is the equipment such as intelligent watch, Intelligent bracelet, panel computer.

The EMBEDDED AVIONICS that the utility model provides, owing to not needing to configure separately a SPI Nor Flash memory chip again, can not only greatly reduce its hardware cost, more can also be convenient to the Miniaturization Design of its structure.

The above embodiment only have expressed several embodiment of the present utility model, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the utility model the scope of the claims.It should be pointed out that for the person of ordinary skill of the art, without departing from the concept of the premise utility, can also make some distortion and improvement, these all belong to protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be as the criterion with claims.

Claims

1. an embedded storage chip, comprise body, be encapsulated in intrinsic control integration circuit die and Nand Flash storage integrated-circuit die, and the first interface contact be arranged on body, described control integration circuit die is provided with first interface, described Nand Flash stores integrated-circuit die and is electrically connected with described control integration circuit die, described first interface contact is electrically connected with described first interface, it is characterized in that, described control integration circuit die is also provided with the second interface, described embedded storage chip also comprises the second interface contact be electrically connected with described second interface be arranged on body, described second interface is SPI interface, described second interface contact is SPI interface contact, described second interface contact at least comprises power lead, ground wire, DOL Data Output Line, Data In-Line, chip select line, clock line 6 contacts.

2. embedded storage chip according to claim 1, is characterized in that, described second interface contact also comprises state maintaining line contact and write-protect line contact.

3. embedded storage chip according to claim 1, it is characterized in that, described first interface is SD interface, described first interface contact is SD interface contact, and described first interface contact at least comprises power lead, ground wire, data line 0, data line 1, data line 2, data line 3, clock line, order wire eight contacts.

4. embedded storage chip according to claim 1, it is characterized in that, described first interface is USB interface, and described first interface contact is USB interface contact, and described first interface contact at least comprises power lead, ground wire, correction data line, negative data line four contacts.

5. embedded storage chip according to claim 1, it is characterized in that, described first interface is eMMC interface, described first interface contact is eMMC interface contact, and described first interface contact at least comprises power lead 1, power lead 2, ground wire, clock line, order wire, reset line, 8 data lines, 14 contacts.

6. the embedded storage chip according to any one of claim 1-5, it is characterized in that, the body of described embedded storage chip is provided with 30 contacts, except first interface contact and the second interface contact, also comprise the power cord point of core power line contact and reservation, all the other contacts are the stick contact temporarily do not used.

7. embedded storage chip according to claim 6, is characterized in that, described embedded storage chip length is of a size of 8mm*8mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.

8. embedded storage chip according to claim 6, is characterized in that, described embedded storage chip length is of a size of 8mm*7.5mm*0.8mm, and the tolerance dimension of length and width is positive and negative 0.1mm, and high tolerance dimension is positive and negative 0.01mm.

9. the embedded storage chip according to claim 7 or 8, it is characterized in that, the mode that described 30 contacts arrange by 5 row 6 is uniformly distributed between two parties at described body surface, described interface contact is circular pad contact or spherical contact or dome shaped contact, radius is 0.6mm, wherein the 1st row contact is 6mm to the distance of the 6th row contact, and the 1st row contact is 4.8mm to the distance of the 5th row contact, and the distance of adjacent two contacts is 1.2mm.

10. an EMBEDDED AVIONICS, is characterized in that, described EMBEDDED AVIONICS comprises embedded storage chip as claimed in any one of claims 1-9 wherein.