CN210296361U - Semiconductor structure - Google Patents

Abstract

The utility model provides a semiconductor structure. The second contact pad is arranged on the side edge of the first contact pad of the interconnection structure, so that the first contact pad formed through graphical processing is not exposed in a larger space area in an isolated manner when the interconnection structure is prepared, and the problem that the first contact pad is over-analyzed is avoided under the protection of the second contact pad, thereby being beneficial to improving the graphic precision of the formed first contact pad and further being beneficial to ensuring the electrical transmission performance of the formed interconnection structure.

Description

Semiconductor structure

Technical Field

The utility model relates to the field of semiconductor technology, in particular to semiconductor structure.

Background

In a semiconductor structure, it is generally necessary to utilize an interconnect structure to realize electrical transmission of a semiconductor device, and thus the electrical transmission performance of the interconnect structure is very important. However, in the currently prepared interconnect structure, the pattern of the contact pad is often deformed, which further causes the problem of poor contact between the contact pad and other electrical transmission elements, thereby affecting the electrical transmission performance of the interconnect structure.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a semiconductor structure to solve among the current semiconductor structure its interconnect structure's the relatively poor problem of electrical property transmission performance.

In order to solve the above technical problem, the utility model provides a semiconductor structure, include:

the semiconductor device comprises a substrate, wherein at least one semiconductor device and an interlayer dielectric layer are formed on the substrate, and the interlayer dielectric layer covers the semiconductor device;

an interconnect structure including a contact plug extending through the interlevel dielectric layer and to the semiconductor device and a first contact pad covering a top portion of the contact plug and extending over a portion of a top surface of the interlevel dielectric layer; and the number of the first and second groups,

and the second contact pad is formed on the top surface of the interlayer dielectric layer and is positioned at the side of the first contact pad.

Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer; the contact plug is formed on the side edge of the gate conducting layer, and the first contact pad transversely extends from the side edge of the gate conducting layer to the shielding layer.

Optionally, the second contact pad is formed on the shielding layer and is spaced apart from the first contact pad.

Optionally, a width dimension of the first contact pad covering the shielding layer is smaller than a width dimension of the second contact pad.

Optionally, the interlayer dielectric layer further includes an isolation sidewall covering the sidewall of the gate conductive layer, the contact plug is formed on a side of the isolation sidewall far from the gate conductive layer, and the first contact pad extends transversely and covers the isolation sidewall adjacent to the contact plug.

Optionally, the interlayer dielectric layer further includes an isolation dielectric layer formed on the periphery of the gate conductive layer, and the contact plug penetrates through the isolation dielectric layer.

Optionally, the material of the first contact pad and the second contact pad is the same.

Optionally, the first contact pad and the second contact pad each include a first conductive layer and a second conductive layer formed on the first conductive layer, and the material of the first conductive layer in the first contact pad and the material of the first conductive layer in the second contact pad are the same, and the material of the second conductive layer in the first contact pad and the material of the second conductive layer in the second contact pad are the same.

The utility model also provides another kind of semiconductor structure, include:

the semiconductor device comprises a substrate, wherein at least one semiconductor device and an interlayer dielectric layer are formed on the substrate, and the interlayer dielectric layer covers the semiconductor device;

an interconnect structure including a contact plug extending through the interlevel dielectric layer and to the semiconductor device and a first contact pad covering a top portion of the contact plug and extending over a portion of a top surface of the interlevel dielectric layer; and the number of the first and second groups,

a second contact pad formed on a top surface of the interlayer dielectric layer and located at a periphery of the first contact pad; and the number of the first and second groups,

a recess between the first contact pad and the second contact pad, the recess further extending downward to stop in the interlevel dielectric layer.

Optionally, the semiconductor structure further includes:

and the insulating filling layer is filled in the groove and covers the side walls of the first contact pad and the second contact pad exposed to the groove.

Optionally, a gap is formed in the insulating filling layer.

Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer;

the contact plug is formed on the side of the gate conductive layer, the first contact pad extends from the side of the gate conductive layer to the shielding layer, the second contact pad is formed on the shielding layer and spaced from the first contact pad, and the groove extends downward between the first contact pad and the second contact pad and stops in the shielding layer.

The utility model provides an among the semiconductor structure, still be provided with the second contact pad at the side of interconnect structure's first contact pad to can avoid first contact pad to expose in a great spatial region. Therefore, when the interconnection structure is prepared, the problem that the first contact pad is over-analyzed can be prevented under the protection of the second contact pad, the pattern precision of the formed first contact pad is improved, and the electrical transmission performance of the formed interconnection structure is further favorably ensured.

Drawings

Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

fig. 2 is a schematic flow chart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 3a to 3f are schematic structural diagrams of a semiconductor structure forming method in the manufacturing process according to an embodiment of the present invention.

Wherein the reference numbers are as follows:

100-a substrate;

110 — a first source/drain region;

120-a second source/drain region;

200-a gate conductive layer;

210-a third conductive layer;

220-a fourth conductive layer;

230-a fifth conductive layer;

300-interlayer dielectric layer;

310-a shielding layer;

320-isolating side walls;

321-a first isolation layer;

322-a second barrier layer;

323-a third barrier layer;

330-isolation dielectric layer;

400-an interconnect structure;

410-contact plugs;

420-a first contact pad;

500-a second contact pad;

600-an insulating filling layer;

610-voids;

600 a-a groove;

700-a layer of conductive material;

700 a-contact hole;

710-a first conductive layer;

720-second conductive layer.

Detailed Description

As described in the background, problems of pattern distortion of contact pads in interconnect structures often occur in existing semiconductor structures.

In view of the above technical problem, the inventors of the present invention have found through research that the pattern of the contact pad is generally defined by the patterning process when the interconnect structure is prepared, however, the patterning precision is often affected by the density of the pattern in the specific patterning process. Specifically, when the pattern arrangement is too dense, the phenomenon that adjacent patterns are adhered to each other due to incomplete pattern resolution is likely to occur; when the pattern layout is too sparse, the formed pattern is over-resolved and is prone to have ripples or notches. For the interconnect structure, the contact pad is usually formed in an isolated manner in a larger spatial area, and therefore, the pattern of the formed contact pad is easily deformed during the preparation of the contact pad, which further affects the electrical transmission performance of the interconnect structure.

In view of the above, the present invention provides a semiconductor structure to improve the problem that the contact pad in the interconnect structure is prone to pattern deformation.

The semiconductor structure and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.

Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, as shown in fig. 1, the semiconductor structure includes:

the semiconductor device structure comprises a substrate 100, wherein at least one semiconductor device and an interlayer dielectric layer 300 are formed on the substrate 100, and the interlayer dielectric layer 300 covers the semiconductor device;

an interconnect structure 400, the interconnect structure 400 including a contact plug 410 and a first contact pad 420, the contact plug 410 penetrating the interlayer dielectric layer 300 and extending to the semiconductor device to electrically connect with the semiconductor device, the first contact pad 420 covering the top of the contact plug 410 and extending laterally to cover a portion of the top surface of the interlayer dielectric layer 300; and the number of the first and second groups,

a second contact pad 500 is formed on the top surface of the interlayer dielectric layer 300 and is located at a side of the first contact pad 420.

In this embodiment, the second contact pads 500 are distributed on the sidewalls of the first contact pads 420, so that the first contact pads 420 are prevented from being exposed in a larger spatial area, which is beneficial to improving the profile of the formed first contact pads 420. For example, when the first contact pad 420 is prepared, the second contact pad 500 is also formed on the side of the first contact pad 420, so that under the protection of the second contact pad 500, the first contact pad 420 can be relieved from a large etching attack, and defects such as etching gaps or deformation of the formed first contact pad 420 can be avoided.

The first contact pad 420 and the second contact pad 500 may be formed by using the same conductive material layer, that is, the material of the first contact pad 420 and the second contact pad 500 is the same. In this embodiment, each of the first contact pad 420 and the second contact pad 500 includes a first conductive layer 710 and a second conductive layer 720, and the second conductive layer 720 is formed on the first conductive layer 710. Also, the material of the first conductive layer 710 in the first contact pad 420 and the material of the first conductive layer 710 in the second contact pad 500 are the same, and the material of the second conductive layer 720 in the first contact pad 420 and the material of the second conductive layer 720 in the second contact pad 500 are the same. The material of the first conductive layer 710 includes, for example, titanium nitride, and the material of the second conductive layer 720 includes, for example, tungsten.

Further, the contact plug 410 and the first contact pad 420 in the interconnect structure 400 may be formed at the same time and have the same material. Specifically, a contact hole is formed in the interlayer dielectric layer 300, and the contact plug 410 is formed in the contact hole. And, the first conductive layer 710 in the contact plug 410 covers the inner wall of the contact hole, and the second conductive layer 720 in the contact plug 410 fills the contact hole.

As still referring to fig. 1, in an alternative scheme, a recess 600a is further formed between the first contact pad 420 and the second contact pad 500, and the recess 600a further extends downward to stop in the interlayer dielectric layer 300.

Specifically, when the first contact pad 420 and the second contact pad 500 are simultaneously prepared by using the same conductive material layer, in order to ensure the electrical isolation between the formed first contact pad 420 and the formed second contact pad 500, the interlayer dielectric layer 300 between the first contact pad 420 and the second contact pad 500 may be further etched after etching the conductive material layer, so as to ensure that the first contact pad 420 and the second contact pad 500 are disconnected from each other, and the recess 600a is formed.

In this embodiment, the semiconductor structure further includes an insulating filling layer 600, and the insulating filling layer 600 is filled in the groove 600a and covers the sidewalls of the first contact pad 420 and the second contact pad 500 exposed in the groove 600 a.

Further, a void 610 may be formed in the insulating filling layer 600 filled in the groove 600 a. In this embodiment, the gap 610 vertically extends in the middle region of the groove 600a in the height direction.

Optionally, the gap 610 is higher than the top surface of the interlayer dielectric layer 300, so that the gap 610 has a portion between the first contact pad 420 and the second contact pad 500. That is, the insulating filling layer 600 filled in the region where the first contact pad 420 and the second contact pad 500 are opposite to each other is formed with the gap 610, so that the dielectric constant of the dielectric material between the first contact pad 420 and the second contact pad 500 can be reduced, and thus the parasitic capacitance between the first contact pad 420 and the second contact pad 500 can be effectively alleviated. In this embodiment, the void 610 vertically extends downward from the top surface of the insulating fill layer 600.

In addition, since the insulating filling layer 600 is formed with the void 610, it is also beneficial to relieve internal stress of the insulating filling layer 600 so as to avoid damage to adjacent contact pads and semiconductor devices due to high-strength internal stress in the insulating filling layer 600. For example, when a high temperature process is performed on the semiconductor structure, the insulating filling layer 600 can achieve stress relief by using the gap 610, thereby avoiding the problem that other elements are damaged due to the high strength stress of the insulating filling layer 600 pressing the other elements.

In particular, when the insulating filling layer 600 is formed directly above the semiconductor device, the semiconductor device may be damaged by high-strength internal stress in the insulating filling layer 600. As shown in fig. 1, in the present embodiment, the insulating filling layer 600 is formed directly above the semiconductor device.

With continued reference to fig. 1, in the present embodiment, the semiconductor device includes at least one transistor, for example. Wherein the transistor includes a gate conductive layer 200 formed on a top surface of the substrate 100, and a first source/drain region 110 and a second source/drain region 120 formed in the substrate 100, the first source/drain region 110 and the second source/drain region 120 being respectively located at both sides of the gate conductive layer 200.

In this embodiment, the gate conductive layer 200 includes a third conductive layer 210, a fourth conductive layer 220, and a fifth conductive layer 230 stacked. The material of the third conductive layer 210 includes, for example, polysilicon, the material of the fourth conductive layer 220 includes, for example, titanium nitride, and the material of the fifth conductive layer 230 includes, for example, tungsten.

Further, the interlayer dielectric layer 300 includes a shielding layer 310 covering the top surface of the gate conductive layer 200. Wherein the contact plugs 410 are formed at the side of the gate conductive layer 200, and the bottoms of the contact plugs 410 vertically extend to the first source/drain region 110 and the second source/drain region 120 of the substrate 100, so as to connect the first source/drain region 110 and the second source/drain region 120 with at least two contact plugs 410 in a one-to-one correspondence manner, and the tops of the contact plugs 410 are higher than the top of the gate conductive layer. And, the first contact pad 420 extends laterally from a side of the gate conductive layer 200 onto the shielding layer 310. That is, the first contact pad 420 is located directly above the gate conductive layer 200 at an upper portion thereof.

In this embodiment, the second contact pad 500 may also be formed on the shielding layer 310 and spaced apart from the first contact pad 420. In this embodiment, the recess 600a between the first contact pad 420 and the second contact pad 500 is formed in the shielding layer 310, and the insulating filling layer 600 is also partially filled in the shielding layer 310. That is, projections of the insulating fill layer 600 and the gate conductive layer 200 in the height direction have regions overlapping each other.

The size of the space between the first contact pad 420 and the second contact pad 500 and the width of the first contact pad 420 and the second contact pad 500 can be adjusted according to the actual situation. Specifically, the space size between the first contact pad 420 and the second contact pad 500 and the width size of the first contact pad 420 and the second contact pad 500 may be adjusted according to the resolution precision of the current photolithography process and the current etching process, as long as the corresponding pattern density under the resolution precision of the current process is satisfied.

For example, the space between the first contact pad 420 and the second contact pad 500 may be smaller than the width of the gate conductive layer 200, so that the second contact pad 500 can protect the pattern of the first contact pad 420 during the process of preparing the first contact pad 420.

In this embodiment, the width of the first contact pad 420 covering the shielding layer 310 is smaller than the width of the second contact pad 500. Since the first contact pad 420 extends from the edge of the shielding layer 310 to the center of the shielding layer 310, and the second contact pad 500 is formed on the shielding layer 310, when the width dimension of the first contact pad 420 covering the shielding layer 310 is smaller than the width dimension of the second contact pad 500, it is equivalent to that the groove 600a between the first contact pad 420 and the second contact pad 500 is offset from the central region of the shielding layer 310, and the groove 600a is offset from the central region of the shielding layer 310 in a direction close to the first contact pad 420.

With continued reference to fig. 1, the interlayer dielectric layer 300 further includes an isolation sidewall spacer 320 covering the sidewall of the gate conductive layer 200. In this embodiment, the isolation sidewall 320 further covers the sidewall of the shielding layer 310. And, the contact plug 410 is formed on one side of the isolation sidewall 320 far away from the gate conductive layer 200, and the first contact pad 420 extends laterally and covers the isolation sidewall 320 adjacent to the contact plug 410.

Specifically, the isolation sidewall spacers 320 are, for example, stacked structures sequentially covering the gate conductive layer 200. In this embodiment, the isolation sidewall spacer 320 includes a first isolation layer 321, a second isolation layer 322, and a third isolation layer 323 sequentially covering the gate conductive layer 200. The first isolation layer 321 and the third isolation layer 323 may be formed of the same material, for example, both include silicon oxide, and the second isolation layer 322 includes silicon nitride, for example, so that the isolation sidewall 320 of the ONO structure may be formed.

Further, the interlayer dielectric layer 300 further includes an isolation dielectric layer 330, and the isolation dielectric layer 330 is formed on the periphery of the gate conductive layer 200. In this embodiment, the isolation dielectric layer 330 surrounds the periphery of the isolation sidewall spacer 320, and the contact plug 410 penetrates through the isolation dielectric layer 330.

Furthermore, in a specific embodiment, at least two transistors may be formed on the substrate 100. Only two transistors are schematically illustrated in fig. 1 of the present embodiment, and the two transistors may share the first source/drain region 110. The contact plug 410 electrically connected to the common first source/drain region 110 is formed between the two transistors, and the corresponding first contact pad 420 laterally extends to the two transistors to be above the gate conductive layers of the two transistors, respectively.

The method of forming the semiconductor structure in this embodiment will be described in detail below. Fig. 2 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention, and fig. 3a to 3f are schematic structural diagrams of a method for forming a semiconductor structure according to an embodiment of the present invention in a manufacturing process thereof.

First, step S100 is performed, and referring to fig. 3a specifically, a substrate 100 is provided, and at least one semiconductor device and an interlayer dielectric layer 300 covering the semiconductor device are formed on the substrate 100.

In this embodiment, the semiconductor device includes a transistor. The transistor further includes a gate conductive layer 200 formed on the top surface of the substrate 100, and first and second source/ drain regions 110 and 120 formed in the substrate 100.

Further, the interlayer dielectric layer 300 includes a shielding layer 310 covering the top surface of the gate conductive layer 200. In this embodiment, the shielding layer 310 and the gate conductive layer 200 may be formed based on the same photolithography process.

Specifically, the method for forming the shielding layer 310 in the interlayer dielectric layer 300 and the gate conductive layer 200 includes:

step one, sequentially forming a gate material layer and a shielding material layer on the substrate 100;

step two, performing a photoetching process and an etching process, and patterning the shielding material layer to form the shielding layer 310;

step three, the gate material layer may be etched by using the shielding layer 310 as a mask layer to form the gate conductive layer 200.

In this embodiment, the gate material layer includes a plurality of stacked material layers, and the plurality of material layers are sequentially etched when the gate material layer is etched, so as to form a third conductive layer 210, a fourth conductive layer 220, and a fifth conductive layer 230, respectively, thereby forming the gate conductive layer 200.

In a further aspect, the method for forming the interlayer dielectric layer 300 further includes: the isolation spacers 320 are formed on the sidewalls of the gate conductive layer 200 and the shielding layer 310.

With continued reference to fig. 3a, the method for forming the interlayer dielectric layer 300 further includes: an isolation dielectric layer 330 is formed on the periphery of the gate conductive layer 200. In this embodiment, the isolation dielectric layer 330 surrounds the periphery of the isolation sidewall spacer 320.

Wherein the isolation dielectric layer 330 may be formed using a planarization process. Specifically, after depositing the isolation dielectric material layer, a chemical mechanical polishing process is performed on the isolation dielectric material layer by using the shielding layer 310 as a polishing stop layer, so that the top surface of the formed isolation dielectric layer 330 is flush with the top surface of the shielding layer 310.

Next, step S200 is performed, and referring to fig. 3b in particular, a contact hole 700a is formed in the interlayer dielectric layer 300, wherein the contact hole 700a penetrates through the interlayer dielectric layer 300 and extends to the semiconductor device.

In this embodiment, the contact hole 700a penetrates through the isolation dielectric layer 330 and extends to the top surface of the substrate 100 to expose the substrate 100.

Next, step S300 is performed, and referring to fig. 3c in particular, a conductive material layer 700 is formed on the interlayer dielectric layer 300, wherein the conductive material layer 700 fills the contact hole 700a and covers the top surface of the interlayer dielectric layer 300.

Specifically, the conductive material layer 700 may be formed using a deposition process and a planarization process. Specifically, the method for forming the conductive material layer 700 includes:

a first step of depositing a first conductive layer 710 on the interlayer dielectric layer 300, wherein the first conductive layer 710 conformally covers the inner wall of the contact hole 700a and the top surface of the interlayer dielectric layer 300;

a second step of forming a second conductive layer 720 on the first conductive layer 710, the second conductive layer 720 filling the contact hole 700a and covering the top surface of the interlayer dielectric layer 300. The second conductive layer 720 is a planarized film layer, so that the second conductive layer 720 has a planar top surface.

Next, step S400 is performed, and referring to fig. 3d in particular, the conductive material layer 700 is patterned to form the interconnect structure 400 and the second contact pad 500. Wherein the interconnect structure 400 includes a contact plug 410 filled in the contact hole and a first contact pad 420 covering the top of the contact plug 410, and the second contact pad 500 is located at a side of the first contact pad 420.

Specifically, the method of patterning the conductive material layer 700 to form the interconnect structure 400 and the second contact pad 500 includes:

first, a mask layer (not shown) having a first mask pattern and a second mask pattern is formed on the conductive material layer 700. Wherein the first mask pattern corresponds to a pattern of the interconnect structure, and the second mask pattern corresponds to a pattern of the second contact pad. Namely, the first mask pattern covers the area of the contact hole and covers the partial area of the periphery of the contact hole; the second mask pattern is positioned on the side edge of the first mask pattern and is separated from the first mask pattern by a preset size;

next, the conductive material layer 700 is etched using the mask layer as a mask to form the interconnect structure 400 corresponding to the first mask pattern and the second contact pad 500 corresponding to the second mask pattern.

In this embodiment, the first contact pad 420 further extends laterally from the contact plug 410 onto the shielding layer 310, and the second contact pad 500 is also at least partially formed on the shielding layer 310 and spaced apart from the first contact pad 420 by a predetermined size.

In an alternative, specifically referring to fig. 3e, after the etching the conductive material layer 700, the method further includes: the interlayer dielectric layer 300 between the first contact pad 420 and the second contact pad 500 is further etched, and the etching stops in the interlayer dielectric layer 300 to form a groove 600a, so that the first contact pad 420 and the second contact pad 500 can be ensured to be mutually disconnected.

Specifically, the first contact pad 420 and the second contact pad 500 may be used as masks to etch the exposed interlayer dielectric layer 300, so as to form the groove 600 a. In this embodiment, the recess 600a extends from between the first contact pad 420 and the second contact pad 500 to the shielding layer 310 and is located right above the gate conductive layer 200. In addition, in this embodiment, a groove may be formed on a side of the second contact pad 500 away from the first contact pad 420.

Further, specifically referring to fig. 3f, the method for forming the semiconductor structure further includes: an insulating filling layer 600 is filled in the groove 600a, and the insulating filling layer 600 also covers sidewalls of the first contact pad 420 and the second contact pad 500 exposed to the groove 600 a.

In this embodiment, a gap 610 may also be formed in the insulating filling layer 600, and the gap 610 is favorable for achieving stress release of the insulating filling layer 600. The gap 610, for example, vertically extends along the height direction in the middle area of the groove 600 a.

In summary, in the semiconductor structure provided in this embodiment, the second contact pad is disposed on the side of the first contact pad of the interconnect structure, so that the first contact pad is prevented from being exposed in a larger spatial area. Therefore, when the interconnection structure is prepared, the first contact pad formed through the patterning processing is not exposed in a larger space area in an isolated manner, but under the protection of the second contact pad, the problem that the first contact pad is over-analyzed is avoided, the pattern precision of the formed first contact pad is improved, and the electrical transmission performance of the formed interconnection structure is further ensured. Alternatively, it can be understood that, in the embodiment, the pattern density of the area corresponding to the first contact pad is adjusted to improve the pattern resolution corresponding to the first contact pad, so as to form the first contact pad with a good pattern profile.

It should be noted that although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. To anyone skilled in the art, without departing from the scope of the present invention, the technical solution disclosed above can be used to make many possible variations and modifications to the technical solution of the present invention, or to modify equivalent embodiments with equivalent variations. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention all still belong to the protection scope of the technical solution of the present invention, where the technical entity does not depart from the content of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims (12)

1. A semiconductor structure, comprising:

the semiconductor device comprises a substrate, wherein at least one semiconductor device and an interlayer dielectric layer are formed on the substrate, and the interlayer dielectric layer covers the semiconductor device;

an interconnect structure including a contact plug extending through the interlevel dielectric layer and to the semiconductor device and a first contact pad covering a top portion of the contact plug and extending over a portion of a top surface of the interlevel dielectric layer; and the number of the first and second groups,

and the second contact pad is formed on the top surface of the interlayer dielectric layer and is positioned at the side of the first contact pad.

2. The semiconductor structure of claim 1, wherein the semiconductor device comprises a gate conductive layer formed on the top surface of the substrate, the interlevel dielectric layer comprising a shield layer covering the top surface of the gate conductive layer; the contact plug is formed on the side edge of the gate conducting layer, and the first contact pad transversely extends from the side edge of the gate conducting layer to the shielding layer.

3. The semiconductor structure of claim 2, wherein the second contact pad is formed on the masking layer and spaced apart from the first contact pad.

4. The semiconductor structure of claim 3, wherein a width dimension of the first contact pad overlying the masking layer is less than a width dimension of the second contact pad.

5. The semiconductor structure of claim 2, wherein the interlevel dielectric layer further comprises an isolation sidewall spacer covering a sidewall of the gate conductive layer, the contact plug is formed on a side of the isolation sidewall spacer away from the gate conductive layer, and the first contact pad extends laterally and covers the isolation sidewall spacer adjacent to the contact plug.

6. The semiconductor structure of claim 2, wherein the interlevel dielectric layer further comprises an isolation dielectric layer formed at a periphery of the gate conductive layer, and the contact plug penetrates through the isolation dielectric layer.

7. The semiconductor structure of claim 1, in which a material of the first contact pad and the second contact pad is the same.

8. The semiconductor structure of claim 7, wherein the first contact pad and the second contact pad each comprise a first conductive layer and a second conductive layer formed on the first conductive layer, and wherein the material of the first conductive layer in the first contact pad and the first conductive layer in the second contact pad is the same, and the material of the second conductive layer in the first contact pad and the second conductive layer in the second contact pad is the same.

9. A semiconductor structure, comprising:

the semiconductor device comprises a substrate, wherein at least one semiconductor device and an interlayer dielectric layer are formed on the substrate, and the interlayer dielectric layer covers the semiconductor device;

an interconnect structure including a contact plug extending through the interlevel dielectric layer and to the semiconductor device and a first contact pad covering a top portion of the contact plug and extending over a portion of a top surface of the interlevel dielectric layer; and the number of the first and second groups,

a second contact pad formed on a top surface of the interlayer dielectric layer and located at a periphery of the first contact pad; and the number of the first and second groups,

a recess between the first contact pad and the second contact pad, the recess further extending downward to stop in the interlevel dielectric layer.

10. The semiconductor structure of claim 9, further comprising:

and the insulating filling layer is filled in the groove and covers the side walls of the first contact pad and the second contact pad exposed to the groove.

11. The semiconductor structure of claim 10, wherein a void is formed in the insulating fill layer.

12. The semiconductor structure of claim 9, wherein the semiconductor device comprises a gate conductive layer formed on the top surface of the substrate, the interlevel dielectric layer comprising a shield layer covering the top surface of the gate conductive layer;

the contact plug is formed on the side of the gate conductive layer, the first contact pad extends from the side of the gate conductive layer to the shielding layer, the second contact pad is formed on the shielding layer and spaced from the first contact pad, and the groove extends downward between the first contact pad and the second contact pad and stops in the shielding layer.

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