CN210199219U - Electric energy quality governs device sampling board test platform - Google Patents

Electric energy quality governs device sampling board test platform Download PDF

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CN210199219U
CN210199219U CN201920770522.8U CN201920770522U CN210199219U CN 210199219 U CN210199219 U CN 210199219U CN 201920770522 U CN201920770522 U CN 201920770522U CN 210199219 U CN210199219 U CN 210199219U
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test
sampling
board
data
circuit
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Guoqi Sun
孙国歧
Xiaobin Wei
魏晓宾
Peibo Sun
孙珮博
Lingyan Zhang
张玲艳
Enkai Xiao
肖恩恺
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Shandong Deyou Electric Corp Ltd
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Shandong Deyou Electric Corp Ltd
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Abstract

A sampling plate test platform of an electric energy quality control device comprises an upper computer, a control plate, a test plate and a sampling plate fixing and detecting platform; the upper computer is communicated with the control panel to realize human-computer interface functions of sending test instructions, receiving test data, analyzing and displaying test results, managing data and the like; the control board is connected with the upper computer and the test board and is used for completing test program control and data receiving, registering and sending; the test board is connected with the control board and the sampling board fixing and detecting platform and used for supplying power to the platform, providing a sampling board test circuit, generating a sampling board input signal and reading a sampling board output signal; the sampling plate fixing and detecting platform is used for placing a sampling plate to be detected, completing the electrical connection between the testing plate and the sampling plate and providing a communication and data transmission channel. The utility model discloses can realize whole preface automatic test and data management of sampling board.

Description

Electric energy quality governs device sampling board test platform
Technical Field
The utility model relates to a power electronic device test platform, concretely relates to device sampling board test platform is administered to electric energy quality.
Background
At present, an intelligent novel power electronic device is developed by an electric energy quality comprehensive treatment optimizing device, and the intelligent novel power electronic device adopts a high-efficiency power electronic topological structure and an advanced full-digital control technology and is mainly used for dynamically compensating reactive current, harmonic current and unbalanced current of a system.
Along with the greatly increased of the electric energy quality comprehensive treatment optimizing device market demand, production enterprises need the circuit board inside the mass production device module. In order to ensure the delivery quality of the module, a test platform for the sampling plate of the electric energy quality treatment device needs to be designed and developed, so as to verify whether the functions of the working power supply, alternating current, voltage sampling, communication and the like of the produced sampling plate are normal or not and whether the sampling precision meets the requirements of the power industry standard or not.
The sampling board test platform in the prior art generally adopts a test mechanism that after an upper computer serial port sends a test instruction, a test signal of a receiving sampling board is sent back synchronously, and because the serial port communication speed is not matched with the A/D (analog-to-digital conversion) speed, the data width and the receiving and sending speed of the sampling board, when a plurality of sampling channels of the sampling board and the sampling points of different types are more, the chaos and the abnormity of data receiving are easily caused, and the prior art fails to provide a corresponding management scheme and a technical scheme for receiving and sending test data.
Disclosure of Invention
The aforesaid to prior art exist not enough, the to-be-solved technical problem of the utility model is: the design provides a device sampling board test platform is administered to electric energy quality, realizes the automatic sampling of whole preface and data management of sampling board, improves the reliability of test, reduces troubleshooting time by a wide margin, improves efficiency of software testing.
The technical scheme of the utility model is that:
the utility model provides a device sampling board test platform is administered to electric energy quality, includes: the upper computer, the control board, the test board and the sampling board fix the detection platform;
the upper computer is communicated with the control panel to realize human-computer interface functions of sending test instructions, receiving test data, analyzing and displaying test results, managing data and the like;
the control board is connected with the upper computer and the test board and is used for finishing control of a test program and receiving, registering and sending of data;
the test board is connected with the control board and the sampling board fixing and detecting platform and used for supplying power to the platform, providing a sampling board test circuit, generating a sampling board input signal and reading a sampling board output signal;
the sampling plate fixing and detecting platform is used for placing a sampling plate of the electric energy quality treatment device to be tested, completing the electrical connection between the testing plate and the sampling plate and providing a communication and data transmission channel;
the control panel comprises a control program module, an A/D module, a data storage module, an interface circuit and a digital clock module, wherein the A/D module, the data storage module, the interface circuit and the digital clock module are respectively connected with the control program module, and the control panel comprises:
the control program module receives the instructions of the upper computer and controls the test flow, and controls the test board to complete the corresponding test function; thirdly, receiving and registering test data, and sending the data to an upper computer according to a preset format;
the A/D module is used for converting direct-current voltage, ripple waves and alternating-current reference waveforms of all power supply test points on the sampling board into digital sampling signals, analyzing and judging whether the sampling board circuit is switched on to normally work or not, converting alternating-current reference waveforms generated by the test board into digital sampling signals, and comparing and judging the sampling function and the precision of an A/D channel of the sampling board;
the data storage module comprises a power signal sampling storage FIFO, an alternating current reference waveform sampling storage FIFO and a communication and digital quantity sampling storage FIFO, and is respectively used for registering power signal test data, alternating current reference waveform data and communication and digital quantity test data;
the interface circuit is used for switching a circuit interface and a data channel between the test board and the control board;
the digital clock module is used for generating a series of sampling frequency clocks required by the control program module;
the test board comprises a power supply circuit, a power supply voltage ripple test circuit, an alternating current signal sampling test circuit, a communication and digital quantity test circuit, wherein:
the power supply circuit receives an external input alternating current 220V power supply and outputs alternating current low voltage signals for supplying power to each circuit and chip of the platform and testing;
the power supply voltage ripple test circuit is used for collecting and processing analog quantity signals of each power supply test point on the sampling board; the sampling data is transmitted to the control panel A/D module through the connecting circuit, the power supply voltage and the ripple signal are converted into digital sampling signals, and the digital sampling signals are registered in a power supply signal sampling storage FIFO;
the alternating current signal sampling test circuit is used for providing sampling plate upper source side current, compensating current, source side voltage sampling alternating current voltage of an A/D channel, current input signals, generating alternating current reference sine wave signals and circuit connection of the alternating current signal sampling test circuit and the current input signals; the AC signal sampling data is transmitted to a corresponding storage FIFO chip in the control panel data storage module through a connecting circuit for registering;
the communication and digital quantity test circuit is used for providing input test signals of a digital quantity input and output channel on the sampling plate, receiving output test signals and being in circuit connection with the input test signals and the output test signals, and sampling data of the communication and digital quantity channel is transmitted to a communication and digital quantity sampling storage FIFO chip in the control plate data storage module through the connecting circuit to be registered.
Compared with the prior art, the utility model discloses the beneficial effect who has is:
(1) the utility model provides a device sampling board test platform is administered to electric energy quality can realize improving the reliability of test to the whole preface test of sampling board, reduces troubleshooting time by a wide margin, improves efficiency of software testing.
(2) The automatic test of presetting test items and test points to the sampling board of the electric energy quality control device can be realized, and the management of the test data of the sampling board is realized through data retransmission to the upper computer.
(3) Through using the data to deposit FIFO, the data width and data transmission matching problem that one end is A/D board data acquisition and the other end is between two different clock domains for host computer serial port communication is solved.
Drawings
FIG. 1 is a circuit block diagram of an embodiment of a test platform of a sampling plate of the electric energy quality control device of the present invention;
FIG. 2 is a schematic diagram of communication and data flow of an embodiment of a test platform of a sampling plate of the electric energy quality control device of the present invention;
fig. 3 is a block diagram showing a brief flow of the test of the embodiment of the test method for the sampling plate of the electric energy quality control device of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
The utility model provides a device sampling board test platform is administered to electric energy quality for realize whole preface automatic test and the data management of data.
Referring to fig. 1, the utility model discloses electric energy quality administers device sampling board test platform, include: the upper computer, the control board, the test board and the sampling board fix the detection platform; the upper computer is connected with the control panel and is communicated with the control panel to realize the man-machine interface functions of upgrading of a control program in the control program module, parameter setting, analysis of test data, sending of test instructions, receiving of test data, analysis and display of test results, management of test data and the like; the control board is connected with the upper computer and the test board and is used for receiving the test instruction of the upper computer and completing program control and data receiving, storing and sending; the test board is connected with the control board and the sampling board fixing and detecting platform and used for supplying power to the platform, providing a sampling board test circuit, generating a sampling board input signal and reading a sampling board output signal; the sampling plate fixing and detecting platform is used for placing the sampling plate of the electric energy quality treatment device to be tested, completing the electrical connection between the testing plate and the sampling plate and providing a communication and data transmission channel.
Specifically, the control panel of this embodiment includes a control program module, an a/D module, a data storage module, an interface circuit, and a digital clock module, where the a/D module, the data storage module, the interface circuit, and the digital clock module are respectively connected to the control program module, where:
(1) the control program module comprises an FPGA (field programmable gate array) chip and a basic working circuit thereof, an interface circuit and a serial port circuit, and specifically, the embodiment adopts an XC6SLX4-3TQG144I chip, a power supply and alternating current signal sampling test module driving program, a communication port and a digital I/O test module driving program are embedded, the A/D module, a data storage module and the interface circuit are controlled by utilizing the I/O port of the chip through enabling signals, and the chip is communicated with an upper computer through a serial port communication mode, so that firstly, the command of the upper computer is received, the test flow is controlled, and secondly, the test board is controlled to complete the corresponding test function; and thirdly, receiving and storing the test data, and sending the data to the upper computer according to a preset format. In the embodiment, the abundant resources of the FPGA chip are utilized to configure independent driving programs for each A/D channel of the control panel A/D module and the sampling panel, so that a large number of decoding circuits brought by multiplexing programs are avoided, and synchronous sampling is supported. Because the functions to be completed by AC and DC sampling are basically consistent, the power supply and AC signal sampling test share one driving program module, and the related signals are generated by decoding to distinguish.
(2) The a/D module includes an ADC chip and a basic working circuit, and specifically, this embodiment adopts a high-speed 12-bit ADC module, which is used to convert the voltage and ripple of each power supply test point on the sampling board into a digital sampling signal, to analyze and judge whether the sampling board circuit is normally connected and the ripple is large or small, and to convert an ac reference waveform signal generated by the test board into a digital sampling signal, which is used as a sampling function and precision judgment of an a/D channel of the sampling board;
(3) and the data storage module comprises a power signal sampling storage FIFO, an alternating current reference waveform sampling storage FIFO and a communication and digital quantity sampling storage FIFO, and is respectively used for registering power signal test data, alternating current reference waveform data and communication and digital quantity test data. In view of the test mechanism that synchronous receipt sampling board test signal was sent back after host computer serial ports adopted prior art to send test instruction, because serial port communication speed and sampling board AD (analog-to-digital conversion) speed, data receiving and dispatching speed mismatch, when the sampling point number of a plurality of sampling passageways of sampling board, different grade type was more, very easily caused the confusion and the anomaly of data reception, the utility model provides an among test platform technical scheme and the test scheme, the sampling storage does not adopt the mechanism that sampling and sending back go on in step, but carries out the mode of prestore to the sampling data, and after every test item test point accomplished the test promptly, the end storage after writing the memory full earlier, then reads the memory and sends back data. Synchronous FIFO is used in the selection of memory rather than using RAM, because if use RAM, then need increase the address and produce the circuit, the utility model discloses a test scheme sampling storage data only need send back the host computer completely and need not the index addressing RAM, consequently use FIFO can save the address and produce the circuit, the automatic address increase and decrease after accomplishing read-write operation of FIFO, the mark is accomplished as the sampling to Full signal that uses FIFO simultaneously, and Empty has sent the mark to the host computer completely as data, is favorable to the simplification of procedure. Specifically, the dc sampling memory of the present embodiment uses an FIFO chip with a depth of 1024 and a width of 12 bits, and all 1024 sampling values are effectively transmitted to the upper computer; the alternating current signal and the alternating current reference waveform sampling storage respectively use an FIFO chip with the depth of 256 and the width of 12 bits, but the actual effective sampling number of the retransmission upper computer is 255 sampling values respectively, so that the design can be realized by shielding the received invalid data in the upper computer; the design width of the FIFO chip of the communication and digital quantity test sampling memory is 8 bits, the depth is selected according to the register quantity of the sampled data, and the data1-data5 is selected in the embodiment. The ac signal and the ac reference signal are both power frequency sine waves, and therefore, it is necessary to sample waveforms within 20ms of a power frequency cycle. In this embodiment, the time for the a/D module to complete one sampling conversion is about 1.9 μ s, the capacity of the ac signal sampling storage FIFO is 256, and the actual sampling time corresponding to 256 points is about 19.5ms and is approximately 1 power frequency cycle when the a/D module completes 40 times of storage each time.
(4) Interface circuit for survey circuit connection and the data channel between board and the control panel switch, specifically, HPC FMC interface module and relay switch array that receive FPGA control are selected for use to this embodiment, and FPGA enable signal passes through HPC FMC interface module control switch array, realizes that the data channel between sampling board and control panel AD module, data storage module, the FPGA switches. With specific reference to fig. 2, an embodiment of the present invention provides a communication and data flow diagram.
(5) And the digital clock module is used for generating a series of sampling frequency clocks required by the control program module. Specifically, the present embodiment selects a digital clock management DCM module embedded in the Xilinx FPGA to establish a reliable system clock.
Further, the test board of this embodiment, including supply circuit, mains voltage ripple test circuit, alternating current signal sampling test circuit, communication and digital quantity test circuit, wherein:
(1) the power supply circuit receives an external input alternating current 220V power supply, outputs power supplies for the sampling board, circuits of the control board and the chip, comprises 3.3V, + 8V and +5VS circuits, internal power supplies comprise 5V, 12V, 24V and the like, and also comprises alternating current voltage and current signals for testing;
(2) the power supply voltage ripple test circuit is used for collecting and processing +/-8V, +5VA and +5VS signals of each power supply test point on a sampling board, specifically, a 0x10 series test instruction of an upper computer enables a power supply signal sampling test program module in a control board FPGA, according to the FPGA instruction, the amplitude proportion of a collected signal is adjusted to be close to 5V, a voltage ripple signal is amplified by 101 times, a data channel is switched to a control board A/D module through an interface circuit, the power supply voltage and the ripple signal are converted into digital sampling signals, and the digital sampling signals are registered to a power supply signal sampling storage FIFO;
(3) the alternating current signal sampling test circuit is used for providing sampling plate upper source side current, compensating current, source side voltage sampling alternating current voltage of an A/D channel, current input signals, generating alternating current reference sine waveform signals and circuit connection of the alternating current signal sampling test circuit and the current input signals. The circuit is required to output 2A sine wave current signals by an alternating current test, the 2A sine wave current signals are sent to an A/D channel of a tested sampling plate, specifically, a 0x20 series test instruction of an upper computer enables a control panel to control an alternating current signal sampling test program module in an FPGA (field programmable gate array), according to the FPGA instruction, six paths of tested current signals (three-phase source side current and three-phase compensation current) of the sampling plate are connected in series, the positive end and the negative end of the tested current are connected with an alternating current low voltage output by a 220V-5V transformer (50Hz), and 2.5 ohm resistors are connected in series to realize the input of the 2A sine wave current signals; for the alternating voltage test requiring circuit to output 220V alternating voltage, the sampling board source side voltage is connected in parallel in three phases, the power supply circuit is connected to input 220V alternating voltage, the introduced 220V alternating current is connected with a relay, the switch is controlled by a control board FPGA, when an alternating signal sampling test program module is enabled, the relay is controlled to be switched on, in order to avoid serious heating of a series resistor of a circuit board of a test board, the alternating current 220V is not suitable for long-time access, and the relay is synchronously controlled to be switched off after a test item is finished; the output of the source side current, the compensation current and the source side voltage sampling A/D channel of the tested sampling plate are respectively registered by an alternating current signal sampling storage FIFO chip in the data storage module through switching a data channel by a connecting circuit; the generation of AC reference sine waveform signals adopts the prior art to meet the requirement that AC voltage and current can be transmitted to the input end of an A/D module of a control panel through an interface circuit for sampling, and reference waveform sampling values after A/D conversion are transmitted to an AC reference waveform sampling storage FIFO for registering;
(4) the communication and digital quantity test circuit is used for providing input test signals of the digital quantity input and output channels on the sampling board, receiving output test signals and connecting the circuits. The FPGA adopts a parallel mechanism for a driving program configured for 2 232 communication ports, 2 485 communication ports and 4 digital I/O channels of a tested sampling board, and completes functions of test enabling, communication and digital testing circuit work, test data register after respective test, FPGA data sending upper computer and the like by utilizing the time sequence beat of an FPGA counter. Specifically, the upper computer 0x30 test instruction enables the control panel communication port and the digital I/O test program module in the FPGA, and according to the FPGA instruction, the 232 communication port, the 485 communication port and the digital I/O test are synchronously performed. For accurate testing, 0x00, 0x55, 0xAA and 0xFF are used as test data, 232com1 is tested to send data, 232com2 receives the data to obtain test data1, 232com2 is tested to send data, and 232com1 receives the data to obtain test data 2; and the 485 communication port test and the 232 communication port test are carried out to obtain test data3 and data 4. Digital quantity I/O test scheme: the digital output channel firstly sends '0000', the digital output channel is configured by a digital quantity test circuit, the digital output channel inputs '1111' after time delay and phase reversal, then '1111' sent by the next digital output channel is read into another digital input channel in a time delay and phase reversal mode, the read data is tested to be '0000', then the two four-digit numbers are spliced into 0xF0, if the digital channel is abnormal, the test data is not 0xF0, and the test data5 is obtained; after the sampling board communication and digital quantity channel test is finished, the test data1-data5 switches the data channel to the communication and digital quantity sampling storage FIFO chip for registering through the interface circuit.
The embodiment of the utility model provides a technical scheme, after putting into the fixed testing platform of sampling board with the electric energy quality treatment device sampling board, electrical connection is accomplished to sampling board and test platform, provides normal operating condition of sampling board, peripheral test circuit, communication and data transmission passageway. The upper computer sends out a test instruction, the test board is controlled by a control board internal program to automatically complete the functional tests of the sampling board such as power supply, communication and sampling channels according to preset test items and test points, the test result is analyzed and displayed by data back-transferring to the upper computer, and the data is stored in an Excel file in a preset format, so that the management of the test data of the sampling board is realized.
Referring to fig. 2, the utility model discloses electric energy quality administers communication and the data flow schematic diagram of device sampling board test platform embodiment.
(1) And designing a communication protocol between the upper computer and the control panel.
The whole testing process of the platform is determined by the communication protocols of the FPGA and the upper computer, and one embodiment of the communication protocol is shown in tables 1 and 2.
Table 1: basic communication protocol
Physical layer protocol RS232
Baud rate 115200bps
Checking mode Without verification
Data bit width 8bits
Command word length Single byte
Table 2: instruction meaning, test item and return test data
Figure BDA0002073073590000061
Figure BDA0002073073590000071
(2) Control program master control mechanism
The mechanism of the FPGA for responding to the upper computer is single instruction response, namely, the FPGA only responds to the latest new instruction, and after the response, the FPGA immediately erases and receives a new instruction mark signal; in the test process, the FPGA does not respond to the instruction of the upper computer any more. After the FPGA responds to the instruction, the FPGA enters a decoding state, corresponding control signals are generated through decoding, corresponding test modules and circuits on the control board and the test board are enabled, after the enabled test modules are tested, corresponding storage FIFO is stored in data, and Full/Empty marks of the storage FIFO are used as control values of the FPGA (Full signals are used as sampling completion marks, Empty marks are used as marks for data to be completely sent to an upper computer). After receiving the test completion signal, the FPGA controls the state machine to enter a data return state, determines the data type of the upper computer according to the current response instruction, and sends test register data back to the upper computer one by one.
During specific testing, the sampling plate of the electric energy quality treatment device to be tested is placed into the sampling plate fixing detection platform, a power supply is turned on, the power supply circuit works, and the platform is powered on. The upper computer is opened, a serial port communication address and a serial port communication format are selected, connection with the control panel is established, the upper computer sends a connection test instruction 0x77 (whether the communication between the FPGA and the upper computer is normal or not is confirmed through the instruction), and after the FPGA receives the connection test instruction of the upper computer, the FPGA sends back 0x77 as it is and enters an idle state to start receiving the test instruction. According to the received upper computer instruction, a control signal is generated by decoding, a corresponding test module is enabled, the test process is controlled, and an interface circuit is enabled to connect the output data of each test circuit of the test board to an input data port of an A/D module of a control board (a sampling board direct current power supply and alternating current reference waveform sampling data are firstly converted by the A/D module and then registered) or a corresponding data storage FIFO port (a sampling board alternating current, voltage sampling data and communication and digital quantity sampling data are registered).
(3) FPGA (field programmable Gate array) control feedback DC power supply sampling value
Firstly, sending back an instruction head such as 0x10, then reading a direct current sampling storage FIFO, splitting 12-bit data read out by each sampling value into two bytes, splicing the data "10" before the high six bits, splicing the data "01" before the low six bits, respectively writing the data into a serial port in sequence, and sending the high six bits firstly and then sending the low six bits.
(4) FPGA (field programmable Gate array) control feedback alternating current signal sampling value
When the A/D of the tested sampling board is normal, firstly sending back an instruction head such as 0x20, then reading the FIFO of the reference waveform memory until the data of the FIFO of the reference waveform memory is empty and sent to the upper computer, and then starting reading the FIFO of the alternating current sampling memory until the memory is empty. Each sampling value of the alternating current signal is 12 bit wide, and when the alternating current signal is transmitted, the data splitting method is transmitted back with the direct current power supply data.
(5) FPGA control return communication port and digital I/O test data
The data is sent back by the following steps: the command head 0x30+232com1 sends data +232com2 sends data +485 receives data + digital quantity I/0 test data.
The utility model discloses the brief flow block diagram of test of device sampling board test method embodiment is administered to electric energy quality refers to figure 3, include:
step 1, an upper computer sends a communication instruction;
step 2, the control panel control program module receives the instruction, sends the instruction back and confirms that the communication is normal;
step 3, the upper computer sends a test instruction;
step 4, the control panel control program module receives the instruction, decodes and generates a control signal, and enables the corresponding test module;
step 5, the test module executes the test, and the test data is stored in the corresponding control board data storage module;
step 6, the control panel receives the test ending signal and sends back test data to the upper computer;
step 7, continuing the loop test from the step 3 to the step 6 until all test items of the communication protocol are preset;
and 8, generating a data table by the upper computer, analyzing, judging and displaying the test result.
To sum up, the embodiment of the utility model provides a technical scheme can realize administering the automatic test that device sampling board predetermine test item and test point to electric energy quality, passes back the management that the host computer realized sampling board test data through the data, and further, through using data to deposit FIFO, solved one end and be AD board data acquisition, the other end is the data transmission matching problem between two different clock domains of host computer serial port communication.

Claims (1)

1. The utility model provides a device sampling board test platform is administered to electric energy quality which characterized in that includes: the upper computer, the control board, the test board and the sampling board fix the detection platform;
the upper computer is communicated with the control panel to realize human-computer interface functions of sending test instructions, receiving test data, analyzing and displaying test results, managing data and the like;
the control board is connected with the upper computer and the test board and is used for finishing control of a test program and receiving, registering and sending of data;
the test board is connected with the control board and the sampling board fixing and detecting platform and used for supplying power to the platform, providing a sampling board test circuit, generating a sampling board input signal and reading a sampling board output signal;
the sampling plate fixing and detecting platform is used for placing a sampling plate of the electric energy quality treatment device to be tested, completing the electrical connection between the testing plate and the sampling plate and providing a communication and data transmission channel;
the control panel comprises a control program module, an A/D module, a data storage module, an interface circuit and a digital clock module, wherein the A/D module, the data storage module, the interface circuit and the digital clock module are respectively connected with the control program module, and the control panel comprises:
the control program module receives the instructions of the upper computer and controls the test flow, and controls the test board to complete the corresponding test function; thirdly, receiving and registering test data, and sending the data to an upper computer according to a preset format;
the A/D module is used for converting direct-current voltage and ripple waves of each power supply test point on the sampling board into digital sampling signals, analyzing and judging whether the sampling board circuit is connected to normally work or not, converting alternating-current reference waveforms generated by the test board into the digital sampling signals, and comparing and judging the sampling function and the precision of an A/D channel of the sampling board;
the data storage module comprises a power signal sampling storage FIFO, an alternating current reference waveform sampling storage FIFO and a communication and digital quantity sampling storage FIFO, and is respectively used for registering power signal test data, alternating current reference waveform data and communication and digital quantity test data;
the interface circuit is used for switching a circuit interface and a data channel between the test board and the control board;
the digital clock module is used for generating a series of sampling frequency clocks required by the control program module;
the test board comprises a power supply circuit, a power supply voltage ripple test circuit, an alternating current signal sampling test circuit, a communication and digital quantity test circuit, wherein:
the power supply circuit receives an external input alternating current 220V power supply and outputs alternating current low voltage signals for supplying power to each circuit and chip of the platform and testing;
the power supply voltage ripple test circuit is used for collecting and processing analog quantity signals of each power supply test point on the sampling board; the sampling data is transmitted to the control panel A/D module through the connecting circuit, the power supply voltage and the ripple signal are converted into digital sampling signals, and the digital sampling signals are registered in a power supply signal sampling storage FIFO;
the alternating current signal sampling test circuit is used for providing sampling plate upper source side current, compensating current, source side voltage sampling alternating current voltage of an A/D channel, current input signals, generating alternating current reference sine wave signals and circuit connection of the alternating current signal sampling test circuit and the current input signals; the AC signal sampling data is transmitted to a corresponding storage FIFO chip in the control panel data storage module through a connecting circuit for registering;
the communication and digital quantity test circuit is used for providing input test signals of a digital quantity input and output channel on the sampling plate, receiving output test signals and being in circuit connection with the input test signals and the output test signals, and sampling data of the communication and digital quantity channel is transmitted to a communication and digital quantity sampling storage FIFO chip in the control plate data storage module through the connecting circuit to be registered.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110108965A (en) * 2019-05-27 2019-08-09 山东德佑电气股份有限公司 Power quality controlling device sampling plate test platform and its test method
CN117012258A (en) * 2023-09-26 2023-11-07 合肥康芯威存储技术有限公司 Analysis device, method and medium for storing chip state data

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110108965A (en) * 2019-05-27 2019-08-09 山东德佑电气股份有限公司 Power quality controlling device sampling plate test platform and its test method
CN117012258A (en) * 2023-09-26 2023-11-07 合肥康芯威存储技术有限公司 Analysis device, method and medium for storing chip state data
CN117012258B (en) * 2023-09-26 2024-01-02 合肥康芯威存储技术有限公司 Analysis device, method and medium for storing chip state data

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