CN210192175U - Silicon chip packing box - Google Patents
Silicon chip packing box Download PDFInfo
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- CN210192175U CN210192175U CN201921186289.5U CN201921186289U CN210192175U CN 210192175 U CN210192175 U CN 210192175U CN 201921186289 U CN201921186289 U CN 201921186289U CN 210192175 U CN210192175 U CN 210192175U
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Abstract
The utility model discloses a silicon chip packing box, which comprises a box body which is open and used for placing silicon chips; the box cover is used for covering the box body; the box body is internally provided with a first separator, and the first separator divides the inner space of the box body into a plurality of placing grooves for placing silicon wafers. Many piles of silicon chips can be placed in the above-mentioned silicon chip packing box, and the problem of silicon chip packing inefficiency has been solved in the transportation of the silicon chip of being convenient for.
Description
Technical Field
The utility model relates to a packing transportation technical field especially relates to a silicon chip packing box.
Background
The single crystal silicon wafer refers to a single crystal of silicon in a sheet form, which is a good semiconductor material and is mainly used for manufacturing semiconductor devices, solar cells, and the like.
At present, the packaging mode of the monocrystalline silicon wafers is a packaging combination of a paper box and six packaging boxes, specifically, only one pile of monocrystalline silicon wafers is packaged in each packaging box, and then the six packaged packaging boxes are packaged in one paper box.
However, in the packaging process, each packaging box needs to be sealed by using an adhesive tape, and then the carton is sealed, namely, seven times of sealing actions are needed for packaging six stacks of monocrystalline silicon wafers; in addition, six operations of placing the packing box in the carton are required. Accordingly, if six stacks of the single crystal silicon wafers in the carton need to be taken out, seven unsealing operations and six taking out operations of the package box from the carton are required.
It can be seen that the conventional method for packing and unpacking the monocrystalline silicon wafers has the defects of complicated steps, large workload and long time consumption, and therefore, how to provide a packing box convenient for packing the monocrystalline silicon wafers is a problem to be solved urgently by technical personnel in the field.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a silicon chip packing box can place many piles of silicon chips in this silicon chip packing box, and the silicon chip of being convenient for is transported, has solved the problem that silicon chip packing is inefficient.
In order to achieve the above object, the utility model provides a silicon chip packing box, include: the box body is in an open shape and used for placing the silicon wafer; the box cover is used for covering the box body; the box body is internally provided with a first separator, and the first separator divides the inner space of the box body into a plurality of placing grooves for placing silicon wafers.
Preferably, the cross section of the inner surface of the box body is square, so that the section of the placing groove is square and is used for placing square silicon wafers.
Preferably, the first partition has a cross-shaped cross section so as to divide the inner space of the cabinet into four placement grooves.
Preferably, the central intersection of the first separator is concave; the part of the first separator close to the inner surface of the box body is equal to the height of the box body.
Preferably, both the box body and the box cover are made of EPS material or PPS material.
Preferably, the bottom of the box body is provided with a carrying groove for being held up by a human hand.
Preferably, the bottom of the box body is provided with a supporting and positioning foot; and the top of the box cover is provided with a positioning groove used for being matched with the supporting and positioning pin.
Preferably, the case lid is for the uncovered form, wherein, the port of case lid with the port of box coincide, just the port of case lid is equipped with female ladder face, the port of box be equipped with female ladder face complex sub-ladder face.
Preferably, the box cover is internally provided with a second separator for separating the inner space of the box cover into an expansion groove for placing a silicon wafer; wherein the shape of the containing groove is the same as that of the placing groove and is communicated with the placing groove.
Compared with the prior art, the utility model provides a silicon chip packing box forms the packing efficiency that a plurality of standing grooves improve the silicon chip through set up first partition part in the box. Particularly, because the inner space of box has a plurality of standing grooves, consequently can place many piles of silicon chips in the box, that is to say this silicon chip packing box can directly pack many piles of silicon chips, and then only need carry out the packing and the bale breaking that the action of a involution and the bale breaking can accomplish the silicon chip.
Therefore, the silicon wafer packaging box can contain a plurality of stacks of silicon wafers at one time, and can package the silicon wafers only by sealing once, so that the packaging efficiency of the silicon wafers can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a box body in a silicon wafer packaging box provided by the present invention;
fig. 2 is a schematic structural diagram of a box cover in a silicon wafer packaging box according to the present invention;
wherein the content of the first and second substances,
1-box body, 11-first separator, 12-placing groove, 2-box cover, 21-second separator and 22-containing groove.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In order to make the technical field of the present invention better understand, the present invention will be described in detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a box body in a silicon wafer packaging box according to the present invention; fig. 2 is a schematic structural diagram of a box cover in a silicon wafer packaging box according to the present invention.
The utility model provides a silicon chip packing box, as shown in figure 1 and figure 2, this silicon chip packing box includes box 1 and case lid 2.
The box body 1 is designed to be in an open shape, the space inside the box body 1 is used for placing silicon wafers, the first partition 11 is arranged in the space inside the box body 1 and divides the space inside the box body 1 into a plurality of placing grooves 12, the silicon wafers are placed in the placing grooves 12 through the opening of the box body 1, and each placing groove 12 is used for containing a stack of silicon wafers.
The box cover 2 is used for covering the box body 1 to shield the port of the box body 1, and further sealing of the silicon wafer packaging box is achieved.
Compared with the prior art, the silicon wafer packaging box can intensively package a plurality of stacks of silicon wafers at one time, so that each stack of silicon wafers does not need to be intensively packaged for the second time, the times of sealing actions by using an adhesive tape are reduced, the flow operation of packaging the silicon wafers is simplified, and the packaging efficiency of the silicon wafers is improved; correspondingly, the operation of the silicon wafer unpacking process is simplified, and the unpacking efficiency of the silicon wafer is improved. In other words, the core of the present application is to provide the first partitions 11 in the cabinet 1 to form a plurality of placing slots 12 for receiving silicon wafers.
In the first embodiment, in order to fully utilize the internal space of the box 1, the placement groove 12 is preferably surrounded by the inner wall of the box 1 and the first divider 11, so as to fully utilize the internal space of the box 1, and the volume of the silicon wafer packing box can be designed as small as possible. Of course, the placement groove 12 may be defined by only the first partition 11, but it is ensured that at least two of the first partitions 11, which individually define the placement groove 12, are provided in the box 1.
On the basis of the first exemplary embodiment, the following embodiments are given here for the structural configuration of the housing 1:
in the second embodiment, in order to pack the square silicon wafers, as shown in fig. 1, the cross section of the inner surface of the case 1 is designed to be square, so that the inner surface of the case 1 and the first partition 11 together enclose a square placing groove 12 for placing the square silicon wafers.
It should be noted that, if silicon wafers in other shapes need to be packed, the shape of the inner surface of the box 1 needs to be designed correspondingly; for example, a circular silicon wafer is preferably used, and the cross section of the inner surface of the case 1 is formed in a circular arc shape, so that the first partition 11 and the inner surface of the case 1 form a circular placing groove 12 for placing the circular silicon wafer.
On the basis of the second embodiment, the following specific examples are given here again for the structural configuration of the first partitioning member 11:
in the third embodiment, as shown in fig. 1, the first separating member 11 is preferably in a cross shape, wherein four ends of the first separating member 11 are connected to the inner surface of the box body 1, and the extending direction of each end of the first separating member 11 is perpendicular to the inner surface of the box body 1 connected with the first separating member, so that the inner space of the box body 1 is divided into four placing grooves 12 with square cross sections, thereby enabling the present silicon wafer packing box to pack four stacks of silicon wafers at one time.
It should be noted that the first separating element 11 may also be designed in the shape of a plate, a groined shape or a Chinese character feng, etc. to form different numbers and rows of the placing slots 12 in the box 1.
It can be understood that the silicon wafer packaging box provided by the embodiment only needs to place four stacks of silicon wafers in the four placing grooves 12 respectively, and then the box cover 2 is covered and the adhesive tape is used for sealing once, so that the four stacks of silicon wafers can be packaged.
In addition, for the convenience of comparison with the packing manner of "one carton and six packing boxes" in the prior art, it is assumed that the silicon wafer packing boxes provided by three embodiments are used for packing twelve stacks of silicon wafers. Compare in prior art's packing process, the silicon chip packing box that this embodiment provided need not to carry out totally twelve transport actions "place six packing boxes in a carton" to and "utilize the sticky tape to carry out the involution totally fourteen times involution actions of involution" to each packing carton, and then simplified the packing process flow of silicon chip, make the packing efficiency of silicon chip obtain showing and promote.
In the fourth embodiment, in order to facilitate picking and placing the stacked silicon wafers in the placing slots 12, as shown in fig. 1, a cross-shaped intersection at the center of the first separating member 11 in the third embodiment is recessed, and the portion of the first separating member 11 close to the inner surface of the box body 1 is designed to be as high as the box body 1, so that each placing slot 12 can expose a portion of the entire stack of silicon wafers in the placing slot 12 on the basis of fixing the entire stack of silicon wafers by the right-angled portion formed by the first separating member 11 and the inner surface of the box body 1, thereby facilitating the manual or picking and placing tool to place the silicon wafers in the placing slots 12 and take out the silicon wafers in the placing slots 12; furthermore, the above-described recessing process also saves the amount of material used to produce the first separator 11.
It should be noted that, in addition to the central cross, the first separating member 11 may be recessed at another portion away from the inner surface of the box 1; the shape formed by the recessing process on the first spacer 11 may be an arc shape or other shapes as long as a part of the silicon wafer can be exposed to facilitate the handling of the silicon wafer by a human hand or the like.
In a fifth embodiment, the box body 1 and the box cover 2 are preferably made of EPS materials or PPS materials, so as to ensure that the silicon wafer packaging box is not easy to damage and deform, and further, the silicon wafer packaging box can be stacked along the height direction by a worker and placed on a transportation device such as a heavy-duty flat trolley, so that the worker can transport a plurality of silicon wafers in the silicon wafer packaging box at one time.
It should be noted that the EPS (Expanded Polystyrene) material has the characteristics of small water absorption, good heat insulation, light weight, high mechanical strength, and the like; the PPS (Polyphenylene sulfide) material is a novel high-performance thermoplastic resin and has the advantages of high mechanical strength, high temperature resistance, chemical resistance, flame retardancy, good thermal stability and the like.
In a sixth embodiment, in order to facilitate the worker to carry the silicon wafer packing box manually, a carrying groove is preferably arranged at the bottom of the box body 1, and the carrying groove is preferably arranged at the edge of the bottom of the box body 1 and is higher than the bottom surface of the box body 1, so that the worker can apply force to the carrying groove and hold the silicon wafer packing box.
The carrying grooves may be linearly formed along the bottom of the box 1 in the horizontal direction, or may be formed only on the wide sides (i.e., the short sides) of the bottom of the box 1 without penetrating the bottom of the box 1.
In the seventh embodiment, the bottom of the box body 1 is provided with supporting and positioning legs, and the top of the box cover 2 is provided with positioning grooves matched with the supporting and positioning legs. When two silicon wafer packing boxes are stacked, the box body 1 positioned on the upper layer of the silicon wafer packing box presses the box cover 2 of the lower layer of the silicon wafer packing box, and the supporting and positioning feet at the bottom of the box body 1 are matched with the positioning grooves, so that the freedom degree of the upper layer of the silicon wafer packing box moving along the horizontal direction is zero, and the situation that the silicon wafer packing boxes can still be kept stable and cannot shake or even topple over after being stacked into multiple layers is ensured.
It should be noted that the shape and structure of the positioning support legs and the positioning grooves are not specifically limited, as long as the positioning grooves can be used for completely inserting all the positioning support legs or the positioning support legs to prevent two adjacent layers of the silicon wafer packaging boxes along the height direction from shaking along the horizontal direction; in addition, the supporting and positioning legs can also be disposed on the top of the case cover 2, and the positioning grooves are correspondingly disposed on the bottom of the case body 1.
In the eighth embodiment, in order to facilitate the working personnel to seal the contact surface between the box cover 2 and the box body 1 by using the adhesive tape, the box cover 2 is preferably designed in an open shape, and the shape of the port of the box cover 2 is identical to that of the port of the box body 1, wherein the port of the box cover 2 is provided with a female stepped surface, and the port of the box body 1 is provided with a sub stepped surface matched with the female stepped surface, so as to avoid dislocation along the horizontal direction between the box cover 2 and the box body 1 due to stress, and further improve the sealing effect of the silicon wafer packaging box.
In a ninth embodiment, as shown in fig. 2, a second partition 21 is preferably provided in the case cover 2 in the eighth embodiment, and the second partition 21 divides the inner space of the case cover 2 into a plurality of expansion slots 22 for placing silicon wafers. In order to increase the capacity of the present silicon wafer packaging box, the shape of the accommodating groove 22 is the same as the shape of the placing groove 12 and is communicated in the height direction, so that the part of the stack of silicon wafers in the placing groove 12 higher than the placing groove 12 can be placed in the accommodating groove 22.
It should be noted that, in order to realize the shape of the containing slot 22 and the placing slot 12 being the same and communicating with each other, the design structure of the second partition 21 should always be the same as the design structure of the first partition 11 in the box 1, for example, if the first partition 11 is designed in a cross shape, the second partition 21 is also designed in a cross shape, and the position of the cross intersection of the two is the same; it can be understood that, since the cover 2 is covered on the upper side of the case 1, there is no problem that it is inconvenient to take and place the silicon wafer in the expansion tank 22, that is, the second partitioning member 21 may not need to be recessed.
It is noted that, in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities.
It is right above that the utility model provides a silicon chip packing box has carried out detailed introduction. The principles and embodiments of the present invention have been explained herein using specific examples, and the above descriptions of the embodiments are only used to help understand the method and its core ideas of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.
Claims (9)
1. A silicon wafer packing case, comprising:
the box body (1) is in an open shape and is used for placing the silicon chip;
a box cover (2) used for covering the box body (1);
the box body (1) is internally provided with a first separating piece (11), and the first separating piece (11) separates the inner space of the box body (1) into a plurality of placing grooves (12) for placing silicon wafers.
2. The silicon wafer packing box of claim 1, wherein the cross section of the inner surface of the box body (1) is square, so that the section of the placing groove (12) is square and is used for placing square silicon wafers.
3. The packing box of silicon wafers as claimed in claim 2, wherein the first partition (11) has a cross-shaped cross-section for the first partition (11) to divide the inner space of the box body (1) into four placing grooves (12).
4. The packaging box of silicon wafers as claimed in claim 3, characterized in that the central intersection of said first partitions (11) is concave; the part of the first separator (11) close to the inner surface of the box body (1) is equal to the height of the box body (1).
5. The packaging box for silicon wafers according to claim 1, characterized in that both the box body (1) and the box cover (2) are made of EPS material or PPS material.
6. The silicon chip packing box of claim 1, wherein the bottom of the box body (1) is provided with a carrying groove for being held by a human hand.
7. The silicon wafer packaging box according to claim 1,
the bottom of the box body (1) is provided with a supporting and positioning foot;
the top of the box cover (2) is provided with a positioning groove used for being matched with the supporting and positioning foot.
8. The packaging box for silicon wafers as claimed in any one of claims 1 to 7,
case lid (2) are uncovered form, wherein, the port of case lid (2) with the port of box (1) coincide, just the port of case lid (2) is equipped with female ladder face, the port of box (1) be equipped with female ladder face complex sub-ladder face.
9. The silicon wafer packing box of claim 8, wherein the box cover (2) is provided with a second partition member (21) therein to partition the inner space of the box cover (2) into an expansion slot (22) for placing silicon wafers; wherein the shape of the containing groove (22) is the same as that of the placing groove (12) and is communicated with the placing groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921186289.5U CN210192175U (en) | 2019-07-25 | 2019-07-25 | Silicon chip packing box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921186289.5U CN210192175U (en) | 2019-07-25 | 2019-07-25 | Silicon chip packing box |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210192175U true CN210192175U (en) | 2020-03-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921186289.5U Active CN210192175U (en) | 2019-07-25 | 2019-07-25 | Silicon chip packing box |
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| CN (1) | CN210192175U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115197461A (en) * | 2022-08-11 | 2022-10-18 | 无锡道石新材料有限公司 | Preparation method and application of composite high-elastic foaming beads |
-
2019
- 2019-07-25 CN CN201921186289.5U patent/CN210192175U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115197461A (en) * | 2022-08-11 | 2022-10-18 | 无锡道石新材料有限公司 | Preparation method and application of composite high-elastic foaming beads |
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