CN210181605U

CN210181605U - Information processing board

Info

Publication number: CN210181605U
Application number: CN201921681316.6U
Authority: CN
Inventors: Hong Xiao; 肖红; Qiang Huang; 黄强
Original assignee: Sichuan Di Information Technology Co Ltd
Current assignee: Sichuan Di Information Technology Co Ltd
Priority date: 2019-10-09
Filing date: 2019-10-09
Publication date: 2020-03-24
Anticipated expiration: 2029-10-09

Abstract

The utility model discloses an information processing board, including the FPGA chip and with FLASH chip, RS422 serial ports, difference output interface, IO output interface, digital output interface, FPGA test IO mouth, voltage input end, voltage output end, AD signal input end, DA output that the FPGA chip is connected respectively. An information processing board is provided, which uses a high-speed Digital Signal Processing (DSP) board when applied, and has a high maximum operation speed. The high-speed synchronous memory is configured on the board, so that a user can be guaranteed to have enough large storage space and enough high access speed. A plurality of interfaces are provided on the board, and the external interfaces are compatible with 5V TTL level, so that the device is convenient to be compatible with other external devices.

Description

Information processing board

Technical Field

The utility model relates to a computer hardware field, concretely relates to information processing board.

Background

The information processing board can work in an independent mode or can be inserted into a PCI slot of a PC to work. The core of the intelligent information processing system is that a DSP device is adopted, the running speed of the existing information processing board is low, a user does not have a large enough storage space and a fast enough access speed, external interfaces are few, the intelligent information processing system is not easy to be compatible with other equipment, input and output can not be adjusted, and the intelligent information processing system is inconvenient to use.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems, an information processing board is provided, and a high-speed Digital Signal Processing (DSP) board is adopted in application, so that the highest operation speed is high. The high-speed synchronous memory is configured on the board, so that a user can be guaranteed to have enough large storage space and enough high access speed. A plurality of interfaces are provided on the board, and the external interfaces are compatible with 5V TTL level, so that the device is convenient to be compatible with other external devices.

The utility model discloses a following technical scheme realizes:

the information processing board comprises an FPGA chip, and an FLASH chip, an RS422 serial port, a differential output interface, an IO output interface, a digital output interface, an FPGA test IO port, a voltage input end, a voltage output end, an AD signal input end and a DA output end which are respectively connected with the FPGA chip.

Further, the information processing board further comprises a crystal oscillator connected with the FPGA chip.

Further, the oscillation frequency of the crystal oscillator is 40 MHz.

Further, the RS422 serial port of the information processing board comprises 1 path of 3.3V RS422 serial ports isolated from the outside.

Further, the differential output interface of the information processing board comprises a 1-path isolation 5V differential output interface.

Further, the IO output interface of the information processing board includes 2 paths of IO outputs.

Further, the digital output interface of the information processing board comprises a 2-path digital output interface.

Furthermore, the FPGA test IO port comprises 5 paths of FPGA test IO ports.

Furthermore, the voltage input end of the information processing board adopts 5V input, the current is less than or equal to 3A, the ripple wave is less than or equal to 50mV, and the power consumption is less than or equal to 10W; the voltage output end adopts 1-path 12V output, and the current is 250-300 mA.

Further, the AD signal input end of the information processing board comprises 4 paths of AD signal inputs; the DA output terminal comprises 2 paths of DA output.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

1. the utility model discloses adopt high-speed digital signal processing board during the application, the highest functioning speed is fast.

2. The utility model discloses the high-speed synchronous memory has been disposed on the board, guarantees that the user has enough big memory space, fast enough access speed.

3. The utility model discloses provide multiple interface on the board, the equal compatible 5V TTL level of external interface, other external equipment of convenient compatibility.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a schematic structural diagram of the present invention.

Reference numbers and corresponding part names in the drawings:

Detailed Description

To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.

Examples

As shown in fig. 1, the information processing board includes an FPGA chip, and a FLASH chip, an RS422 serial port, a differential output interface, an IO output interface, a digital output interface, an FPGA test IO port, a voltage input terminal, a voltage output terminal, an AD signal input terminal, and a DA output terminal, which are respectively connected to the FPGA chip.

The FPGA chip is connected with the chip through the chip.

The oscillation frequency of the crystal oscillator is 40 MHz.

The RS422 serial port comprises 1 path of 3.3V RS422 serial ports isolated from the outside.

The differential output interface comprises a 1-path isolation 5V differential output interface.

The IO output interface comprises 2 paths of IO output.

The digital output interface comprises a 2-way digital output interface.

The FPGA test IO port comprises 5 paths of FPGA test IO ports.

The voltage input end adopts 5V input, the current is less than or equal to 3A, the ripple wave is less than or equal to 50mV, and the power consumption is less than or equal to 10W; the voltage output end adopts 1-path 12V output, and the current is 250-300 mA.

The AD signal input end comprises 4 paths of AD signal inputs; the DA output terminal comprises 2 paths of DA output.

The FPGA chip controls the working states of the AD and the DA; the FLASH chip adopts 1 high-capacity FLASH to store solidified data and is controlled by the FPGA; 1 path of 3.3V RS422 serial ports isolated from the outside (isolated RS422 in FIG. 1); the circuit is provided with 1 path of isolated 5V differential output interfaces, signals come from an FPGA, and the FPGA is required to control the physical connection or disconnection of the external interfaces, so that possible external interference is avoided (isolated 5V differential output in figure 1); 2 paths of IO output are provided, and the IO output of the FPGA is connected to an external interface pad (2 paths of analog output in figure 1) through an amplifying circuit output 12V; 2 paths of digital output are provided and are output by the FPGA; the test device is provided with 5 FPGA test IO ports and is connected to an external interface pad (5 test IO ports in figure 1); has FPGA JTAG interface connected to the external interface pad (JTAG in FIG. 1); 1 path of 5V input is provided, the current is less than or equal to 3A, the ripple wave is less than or equal to 50mV, and the power consumption is less than or equal to 10W; has 1 path of 12V output, and the current is 250-300 mA; having 4 AD signal inputs (4 analog inputs in FIG. 1); provide 2 DA outputs, 1 control 603 gain, and 1 connection to pad sparing.

Major hardware model requirements

FPGA: XC7A200T-2SBG484I is selected;

crystal oscillator: selecting Yuxuxing TC53-NAGIC-40MHz, working temperature of-40 to +85 ℃ and frequency stability of +/-1 ppm;

flash: selecting S29GL 512P;

the external 5V differential output adopts MAX488, and an isolation optocoupler is self-defined to ensure that the rising edge time is as small as possible;

in the embodiment, the FPGA chip adopts an ARTIX 7 series chip of XILINX company, the specific model is XC7A200T-2SBG484I, the FPGA integrates 6I/O BANK, the starting mode is an SPI loading mode, the configuration chip selects N25Q256A, the crystal oscillator selects TC53-NAGIC-40MHz, the working temperature is-40 ℃ to +85 ℃, and the frequency stability is +/-1 ppm. Outputting a 40MHz clock to a global clock pin of the FPGA to be used as a working clock of the FPGA; meanwhile, a200 MHz differential LVDS clock is output inside the FPGA through a phase-locked loop to serve as a sampling clock of the four-channel ADC.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The information processing board is characterized by comprising an FPGA chip, and an FLASH chip, an RS422 serial port, a differential output interface, an IO output interface, a digital output interface, an FPGA test IO port, a voltage input end, a voltage output end, an AD signal input end and a DA output end which are respectively connected with the FPGA chip.

2. The information processing board according to claim 1, further comprising a crystal oscillator connected to the FPGA chip.

3. The information processing board according to claim 2, wherein an oscillation frequency of the crystal oscillator is 40 MHz.

4. The information processing board of claim 1, wherein the RS422 serial port comprises a 1-way isolated 3.3V RS422 serial port.

5. The information processing board of claim 1, wherein the differential output interface comprises a 1-way isolated 5V differential output interface.

6. The information processing board according to claim 1, wherein the IO output interface includes a 2-way IO output.

7. The information processing board of claim 1, wherein the digital output interface comprises a 2-way digital output interface.

8. The information processing board of claim 1, wherein the FPGA test IO port comprises a 5-way FPGA test IO port.

9. The information processing board of claim 1, wherein the voltage input terminal adopts 5V input, current is less than or equal to 3A, ripple is less than or equal to 50mV, and power consumption is less than or equal to 10W input voltage; the voltage output end adopts 1-path 12V output, and the current is 250-300 mA.

10. The information processing board according to claim 1, wherein the AD signal input terminal includes 4-way AD signal inputs; the DA output terminal comprises 2 paths of DA output.