CN210167800U

CN210167800U - Structure for carrying out chip over-temperature protection by using temperature characteristic of triode

Info

Publication number: CN210167800U
Application number: CN201920933694.2U
Authority: CN
Inventors: 郭虎; 王照新; 李建伟; 蔡彩银
Original assignee: Zhejiang Dexin Space Information Technology Co Ltd
Current assignee: Zhejiang Dexin Space Information Technology Co Ltd
Priority date: 2019-06-20
Filing date: 2019-06-20
Publication date: 2020-03-20
Anticipated expiration: 2029-06-20

Abstract

The utility model relates to an use triode temperature characteristic to carry out structure of chip excess temperature protection, chip excess temperature protection architecture, include: a chip; the temperature detection assembly is arranged on a temperature detection component on the surface of the chip and is used for detecting the working temperature of the chip; the transistor characteristic over-temperature protection circuit is arranged on one side of the chip, and the temperature sensing resistor is arranged on the surface of the chip and has different resistance values at different temperatures; the sensor is connected with the temperature-sensing resistor and used for detecting the resistance value of the temperature-sensing resistor, the working temperature of the chip is determined according to the resistance value, the determined working temperature value is transmitted to the triode characteristic over-temperature protection circuit, the temperature-sensing resistor can be fixedly mounted on the surface of the chip through insulating glue, the insulating glue can play a role in fixing the temperature-sensing resistor on one hand, on the other hand, the temperature-sensing resistor can be electrically insulated from a surface circuit and components of the chip, and unnecessary interference of an electric signal in the chip to the signal in the temperature-sensing resistor is avoided.

Description

Structure for carrying out chip over-temperature protection by using temperature characteristic of triode

Technical Field

The utility model relates to a technical field is used to triode temperature characteristic, in particular to use triode temperature characteristic to carry out the structure of chip excess temperature protection.

Background

In electronic circuits, a transistor is a ubiquitous transistor, and the transistor is widely used in various circuits due to its functions of amplification, current expansion, and substitution.

In the development and design stage of Integrated Circuit (IC) circuits, the operating temperature of the IC varies with its operating state and operating time. As the degree of integration of the chip is higher and the function is more and more complex, the influence of the working temperature of the chip on the chip is larger and larger. For the chip of the display screen, if the working temperature of the chip is too high, the chip can be damaged, when the damage degree is relatively low, a plurality of problems such as vertical stripes, black screen, flash lines and the like can be generated, and when the damage degree is serious, the chip can be burnt out, and even fire disasters are caused.

The above information disclosed in the background section is only for enhancement of understanding of the background of the present invention, and therefore it may contain information that does not form the prior art that is known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

In view of this, embodiments of the present invention are directed to a structure for performing over-temperature protection of a chip by using the temperature characteristic of a transistor, so as to solve or alleviate the technical problems in the prior art, and at least provide a useful choice.

The embodiment of the utility model provides a technical scheme is so realized:

according to the utility model discloses an embodiment provides an use triode temperature characteristic to carry out the structure of chip excess temperature protection, chip excess temperature protection architecture, include:

a chip;

the temperature detection assembly is arranged on a temperature detection component on the surface of the chip and is used for detecting the working temperature of the chip;

the triode characteristic over-temperature protection circuit is arranged on one side of the chip and used for measuring and controlling the over-temperature protection of the chip;

the comparator is arranged between the chip and the triode characteristic over-temperature protection circuit and connected with the chip and the triode characteristic over-temperature protection circuit, and the comparator comprises a positive input end, a negative input end and an output end.

In some embodiments, the temperature detection assembly includes a temperature-sensing resistor fixedly mounted on the surface of the chip through an insulating adhesive, and the temperature-sensing resistor has different resistance values at different temperatures;

and the sensor is connected with the temperature sensing resistor and is used for detecting the resistance value of the temperature sensing resistor, determining the working temperature of the chip according to the resistance value and transmitting the determined working temperature value to the triode characteristic over-temperature protection circuit.

In some embodiments, a heat-insulating film is fixed on the bottom of the sensor, and the sensor and the heat-insulating film are adhered to the surface of the chip through an insulating adhesive.

In some embodiments, the triode characteristic over-temperature protection circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a capacitor C1, a capacitor C2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first NPN transistor Q1, a second NPN transistor Q2, a resistor R1, a resistor R2, a resistor R3, and an output shaping circuit.

In some embodiments, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and to the drain of the second PMOS transistor MP2, the gate of the second PMOS transistor MP2 is connected to the drain of the second PMOS transistor MP2, the anode of the capacitor C2 is connected to the gate of the second PMOS transistor MP2, the cathode of the capacitor C2 is connected to the gate of the first NMOS transistor MN1, the gate of the second NMOS transistor MN2, the base of the first NPN transistor Q1 and the base of the second NPN transistor Q2, the gate of the first NMOS transistor MN 84 and the gate of the second NMOS transistor MN2, the base of the first NPN transistor Q1 and the base of the second NPN transistor Q2 are connected, the capacitor C1 is connected in parallel with the capacitor C375, the drain of the PMOS transistor MP2 is connected to the source of the second NMOS transistor MN 5857324, the drain of the first NMOS transistor MN1 is connected to one end of a resistor R1, the source of the second NMOS transistor MN2 is connected to the gate of the second NMOS transistor MN2, the collector of the second NPN transistor Q2 is connected to the base of the second NPN transistor Q2 and the drain of the second NMOS transistor MN2, the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and the source of the second NMOS transistor MN2 are all connected to one end of the output shaping circuit, the other end of the output shaping circuit is connected to a resistor R2, a resistor R3, a chip and a comparator, which are connected in series with each other, the source of the first PMOS transistor MP1 is connected to a power supply voltage VCC, and the emitters of the resistor R1, the other end of the resistor R3 and the second NMOS transistor Q2 are all grounded.

In some embodiments, the comparator is a hysteresis comparator, the output end outputs an over-temperature protection signal, the first NPN transistor Q1 and the second NPN transistor Q2 are control switching tubes, and the conduction voltage drop V thereof_BEHas a negative temperature coefficient.

In some embodiments, the output shaping circuit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6, the gate of the third PMOS transistor MP3 is respectively connected to the gate of the first PMOS transistor MP1 and the drain of the first PMOS transistor MP2, and is connected with the gate of the fifth PMOS transistor MP5, the gate of the first PMOS transistor MP4 is connected with the gate of the first PMOS transistor MP4 and the drain of the first PMOS transistor MP2, and is connected with the grid of the first PMOS transistor MP4, the drain of the third PMOS transistor MP3 is connected with the source of the fourth PMOS transistor MP4, the drain electrode of the fourth PMOS transistor MP4 is respectively connected to the source electrode and the gate electrode of the second NMOS transistor MN2, the drain of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6, the drain electrode of the sixth PMOS tube MP6 is connected with the negative input end of the comparator and one end of the resistor R2, and the source electrode of the fifth PMOS tube MP5 is connected with the chip.

The embodiment of the utility model provides a owing to adopt above technical scheme, it has following advantage: the temperature-sensitive resistor is arranged on the surface of the chip and has different resistance values at different temperatures; the sensor is connected with the temperature-sensing resistor and used for detecting the resistance value of the temperature-sensing resistor, the working temperature of the chip is determined according to the resistance value, the determined working temperature value is transmitted to the triode characteristic over-temperature protection circuit, the temperature-sensing resistor can be fixedly mounted on the surface of the chip through insulating glue, the insulating glue can play a role in fixing the temperature-sensing resistor on one hand, on the other hand, the temperature-sensing resistor can be electrically insulated from a surface circuit and components of the chip, and unnecessary interference of an electric signal in the chip to the signal in the temperature-sensing resistor is avoided.

The sensor can be installed on the surface of the chip and also can be installed outside the chip, and the resistance value of the temperature-sensitive resistor detected by the sensor is not influenced. Taking the sensor mounted on the surface of the chip as an example, in order to avoid the heat on the chip from being conducted to the sensor and affecting the sensitivity and accuracy of the detection of the sensor, a heat-insulating film is fixed at the bottom of the sensor (i.e. the side of the sensor facing the surface of the chip), that is, a heat-insulating film is arranged between the sensor and the chip to isolate the sensor from the chip; the heat insulation film can be adhered to the bottom of the sensor through the insulating adhesive, and the heat insulation film can be adhered to the chip through the insulating adhesive, so that the sensor is fixedly mounted on the chip.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

Fig. 1 is a structural diagram of the embodiment of the present invention, which applies the temperature characteristic of the transistor to perform the over-temperature protection of the chip;

fig. 2 is a schematic diagram of an over-temperature protection circuit for protecting a chip from over-temperature by using the temperature characteristic of a transistor according to an embodiment of the present invention;

fig. 3 the utility model discloses an use triode temperature characteristic to carry out the temperature-detecting element mounting structure cross-sectional view of the structure of chip excess temperature protection.

In the figure: 100. a chip over-temperature protection structure; 10. a temperature detection assembly; 101. a temperature-sensitive resistor; a sensor; 13. 15, insulating glue; 14. a heat insulating film; 20. the temperature characteristic over-temperature protection circuit of the triode; 201. an output shaping circuit.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, are not to be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

As shown in fig. 1-3, an embodiment of the present invention provides a structure for chip over-temperature protection by using the temperature characteristic of a transistor, the chip over-temperature protection structure 100, including:

a chip 30;

a temperature detection assembly 10, a temperature detection component mounted on the surface of the chip 30, for detecting the working temperature of the chip 30;

the triode characteristic over-temperature protection circuit 20 is arranged on one side of the chip 30 and used for measuring and controlling over-temperature protection of the chip;

and the comparator is arranged between the chip 30 and the triode characteristic over-temperature protection circuit 20 and connected with the chip and the triode characteristic over-temperature protection circuit, and comprises a positive input end, a negative input end and an output end.

Specifically, the temperature detection assembly comprises a temperature sensing resistor 101 and a sensor 102 which are fixed through an insulating glue 13. The temperature-sensitive resistor 101 is mounted on the surface of the chip 30, and exhibits different resistance values at different temperatures; the sensor 102 is connected with the temperature-sensing resistor 101 and used for detecting the resistance value of the temperature-sensing resistor 101, thereby determining the working temperature of the chip 30, and transmitting the determined working temperature value to the triode characteristic over-temperature protection circuit 20, the temperature-sensing resistor 11 can be fixedly installed on the surface of the chip 30 through the insulating glue 13, the insulating glue 103 can play a role in fixing the temperature-sensing resistor 101 on one hand, and on the other hand, the temperature-sensing resistor 101 can be electrically insulated from the surface circuit and the components of the chip 30, so that unnecessary interference of an electric signal in the chip 30 to the signal in the temperature-sensing resistor 101 is avoided.

The sensor 102 may be mounted on the surface of the chip 30, or may be mounted outside the chip 30, which does not affect the resistance of the temperature-sensitive resistor 101. Taking the sensor 102 mounted on the surface of the chip 30 as an example, in order to avoid heat on the chip 30 from being conducted to the sensor 102 and affecting the sensitivity and accuracy of detection of the sensor 102, the heat-insulating film 104 is fixed on the bottom of the sensor 102 (i.e. the side of the sensor 102 facing the surface of the chip 30), that is, the heat-insulating film 104 is disposed between the sensor 102 and the chip 30 to isolate the sensor 102 from the chip 30; the heat insulating film 14 may be attached to the bottom of the sensor 102 by an insulating adhesive 105, and the heat insulating film 104 may be attached to the chip 30 by an insulating adhesive 103, thereby fixedly mounting the sensor 102 to the chip 30.

And a heat insulation film is fixed at the bottom of the sensor, and the sensor and the heat insulation film are adhered to the surface of the chip through an insulation adhesive.

Specifically, the triode characteristic over-temperature protection circuit comprises a first PMOS tube MP1, a second PMOS tube MP2, a capacitor C1, a capacitor C2, a first NMOS tube MN1, a second NMOS tube MN2, a first NPN transistor Q1, a second NPN transistor Q2, a resistor R1, a resistor R2, a resistor R3 and an output shaping circuit.

Specifically, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and is connected to the drain of the second PMOS transistor MP2, the gate of the second PMOS transistor MP2 is connected to the drain of the second PMOS transistor MP2, the anode of the capacitor C2 is connected to the gate of the second PMOS transistor MP2, the cathode of the capacitor C2 is connected to the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2, the base of the first NPN transistor Q1 is connected to the base of the second NPN transistor Q2, the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are connected to each other, the base of the first NPN transistor Q1 is connected to the base of the second NPN transistor Q2, the capacitor C1 is connected to the capacitor C2, the drain of the second PMOS transistor MP 5962 is connected to the drain of the first NMOS transistor MN 828653, and the drain of the first NMOS transistor MN 828653 is connected to the drain of the first NMOS transistor MN 8286 1, the source of the second NMOS transistor MN2 is connected to the gate of the second NMOS transistor MN2, the collector of the second NPN transistor Q2 is connected to the base of the second NPN transistor Q2 and the drain of the second NMOS transistor MN2, the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and the source of the second NMOS transistor MN2 are all connected to one end of the output shaping circuit, the other end of the output shaping circuit is connected to a resistor R2, a resistor R3, a chip and a comparator, which are connected in series with each other, the source of the first PMOS transistor MP1 is connected to a power supply voltage VCC, and the other ends of the resistor R1, the resistor R3 and the emitter of the second NPN transistor Q2 are all grounded.

Specifically, the comparator is a hysteresis comparator, the output end outputs an over-temperature protection signal, the first NPN transistor Q1 and the second NPN transistor Q2 are control switching tubes, and the conduction voltage drop VBE of the control switching tubes has a negative temperature coefficient.

Specifically, the output shaping circuit comprises a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6, the gate of the third PMOS transistor MP3 is respectively connected to the gate of the first PMOS transistor MP1 and the drain of the first PMOS transistor MP2, and is connected with the gate of the fifth PMOS transistor MP5, the gate of the first PMOS transistor MP4 is connected with the gate of the first PMOS transistor MP4 and the drain of the first PMOS transistor MP2, and is connected with the grid of the first PMOS transistor MP4, the drain of the third PMOS transistor MP3 is connected with the source of the fourth PMOS transistor MP4, the drain electrode of the fourth PMOS transistor MP4 is respectively connected to the source electrode and the gate electrode of the second NMOS transistor MN2, the drain of the fifth PMOS transistor MP5 is connected to the source of the sixth PMOS transistor MP6, the drain electrode of the sixth PMOS tube MP6 is connected with the negative input end of the comparator and one end of the resistor R2, and the source electrode of the fifth PMOS tube MP5 is connected with the chip.

Temperature characteristics of the transistor the effect of temperature on the amplification factor β:

1. the β value of the triode increases with the temperature rise, and the β value increases by about 0.5-1% for each rise of the temperature, so that the collector current IC increases with the temperature rise under the same IB condition.

2. Effect of temperature on reverse saturation current ICEO:

icoo is formed by the drift motion of minority carriers, which is strongly dependent on ambient temperature, with the icoo increasing dramatically with increasing temperature. The temperature was raised by 10 ℃ and ICEO was doubled. Since the silicon tube ICEO is small, the temperature does not have much effect on the silicon tube ICEO.

3. The temperature of the emitter junction voltage ube is influenced by 1 ℃ rise, and ube drops by 2-2.5 mV

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the present invention, which should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The utility model provides an use triode temperature characteristic to carry out structure of chip excess temperature protection which characterized in that, chip excess temperature protection structure includes:

a chip;

2. The structure for chip over-temperature protection by using triode temperature characteristic as claimed in claim 1, wherein the temperature detection assembly comprises a temperature sensing resistor fixedly mounted on the surface of the chip through an insulating glue, and the temperature sensing resistor has different resistance values at different temperatures;

3. The structure for chip over-temperature protection by using triode temperature characteristic as claimed in claim 2, wherein a heat insulating film is fixed on the bottom of the sensor, and the sensor and the heat insulating film are adhered to the surface of the chip by an insulating adhesive.

4. The structure of claim 1, wherein the triode characteristic over-temperature protection circuit comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a capacitor C1, a capacitor C2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first NPN transistor Q1, a second NPN transistor Q2, a resistor R1, a resistor R2, a resistor R3 and an output shaping circuit.

5. The structure of claim 4, wherein a drain of the first PMOS transistor MP1 is connected to a source of the second PMOS transistor MP2, a gate of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP2 and to a drain of the second PMOS transistor MP2, a gate of the second PMOS transistor MP2 is connected to a drain of the second PMOS transistor MP2, a positive electrode of the capacitor C2 is connected to a gate of the second PMOS transistor MP2, a negative electrode of the capacitor C2 is connected to a gate of the first NMOS transistor MN1 and a gate of the second NMOS transistor MN2, a base of the first NPN transistor Q1 is connected to a base of the second NPN transistor Q2, a gate of the first NMOS transistor MN1 and a gate of the second NMOS transistor MN2 are connected to each other, a base of the first NPN transistor Q1 and a base of the second NPN transistor Q2 are connected to a gate of the capacitor C1, the drain of the second PMOS transistor MP2 is connected to the source of the first NMOS transistor MN1, the drain of the first NMOS transistor MN1 is connected to one end of a resistor R1, the source of the second NMOS transistor MN2 is connected to the gate of the second NMOS transistor MN2, the collector of the second NPN transistor Q2 is connected to the base of the second NPN transistor Q2 and the drain of the second NMOS transistor MN2, the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the source of the second NMOS transistor MN2 are all connected to one end of the output shaping circuit, the other end of the output shaping circuit is connected to a resistor R2, a resistor R3, a chip, and a comparator, which are connected in series, the source of the first PMOS transistor MP1 is connected to a power supply voltage VCC, and the other ends of the resistor R1, the resistor R3, and the emitter of the second NPN transistor Q2 are all grounded.

6. The structure of claim 4 or 5, wherein the comparator is a hysteresis comparator, the output end of the comparator outputs an over-temperature protection signal, the first NPN transistor Q1 and the second NPN transistor Q2 are control switching transistors, and the first NPN transistor Q1 and the second NPN transistor Q2 have conduction voltage drops V_BEHas a negative temperature coefficient.

7. The structure of claim 5, wherein the output shaping circuit includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6, a gate of the third PMOS transistor MP3 is connected to the gate of the first PMOS transistor MP1 and the drain of the first PMOS transistor MP2, respectively, and is connected to the gate of the fifth PMOS transistor MP5, a gate of the first PMOS transistor MP4 is connected to the gate of the first PMOS transistor MP4 and the drain of the first PMOS transistor MP2, respectively, and is connected to the gate of the first PMOS transistor MP4, a drain of the third PMOS transistor MP3 is connected to the source of the fourth PMOS transistor MP4, a drain of the fourth PMOS transistor MP4 is connected to the drain of the second PMOS transistor MN2 and the gate, a drain of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6, and a negative comparator MP 36 are connected to the drain of the sixth PMOS 6, respectively, One end of the resistor R2 is connected, and the source of the fifth PMOS tube MP5 is connected with the chip.