CN210157150U - Differential input structure capable of improving performance of operational amplifier - Google Patents
Differential input structure capable of improving performance of operational amplifier Download PDFInfo
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Abstract
The utility model relates to a differential input structure capable of improving the performance of an operational amplifier, which comprises a main body part, an auxiliary part and a voltage transmission pipe group, wherein, the MOS pipes in the main body differential pair pipe in the main body part all adopt thin gate oxide MOS pipes, the MOS pipes in the auxiliary differential pair pipe in the auxiliary part all adopt thick gate oxide MOS pipes, the gate terminal of an auxiliary first thick gate oxide MOS pipe receives an input signal VP +, the gate terminal of an auxiliary second thick gate oxide MOS pipe receives an input signal VN-, the auxiliary first thick gate oxide MOS pipe and the auxiliary second thick gate oxide MOS pipe are utilized to avoid the larger difference between the input signal VP + and the input signal VN-to cause the larger damage of the differential pair pipe VGS to the MOS pipe, when the main body differential pair pipe adopts the thin gate oxide MOS pipe, the performance of the operational amplifier can be ensured, after the voltage transmission is carried out by the voltage transmission pipe group, the difference value between the gate terminal voltage of the main body first thin gate oxide MOS pipe and the gate terminal voltage of the main body second thin gate oxide MOS pipe can be ensured, is safe and reliable.
Description
Technical Field
The utility model relates to a differential input structure, especially a can improve differential input structure of operational amplifier performance belongs to operational amplifier's technical field.
Background
As shown in fig. 1, the schematic diagram of the differential input structure of the conventional operational amplifier includes a PMOS transistor MP1, a PMOS transistor MP3, a PMOS transistor MP4, an NMOS transistor NM3, and an NMOS transistor NM4, wherein a source terminal of the PMOS transistor MP1 is connected to a power supply VDD, a gate terminal of the PMOS transistor MP1 is connected to a gate terminal voltage Vbp, a drain terminal of the PMOS transistor MP1 is connected to a source terminal of the PMOS transistor MP3 and a source terminal of the PMOS transistor MP4, a drain terminal of the PMOS transistor MP3 is connected to a drain terminal of the NMOS transistor MN3, a drain terminal of the PMOS transistor MP4 is connected to a drain terminal of the NMOS transistor MN4, a gate terminal of the NMOS transistor MN4, and a gate terminal of the NMOS transistor MN3, a source terminal of the NMOS transistor MN3 and a source terminal of the NMOS transistor MN4 are grounded, a gate terminal of the PMOS transistor MP3 is connected to an input.
In the differential input structure, the PMOS transistor MP3 and the PMOS transistor MP4 are differential pair transistors of thin gate oxide, and the thin gate oxide generally means that the thickness of the oxide layer of the MOS transistor is relatively thin, and for the MOS transistor of thin gate oxide, the advantages are low threshold voltage, good voltage-current characteristics, low noise, small relative area, and the disadvantage is low VGS voltage resistance. The thick gate oxide generally means that the thickness of the oxide layer of the MOS transistor is relatively thick, the thick gate oxide MOS transistor has the advantages of high VGS withstand voltage and the disadvantages of large threshold voltage, poor current-voltage characteristics, large noise and large relative area, and the thickness of the oxide layer of the thick gate oxide is generally about five times that of the oxide layer of the thin gate oxide.
Normally, the conduction of the differential pair transistor is related to VGS of the differential pair transistor, and normally, the voltage of the input signal VP + and the voltage of the input signal VN-are relatively close to each other, but in a special case, the voltage between the input signal VP + and the input signal VN-is relatively large, which results in that the VGS withstand voltages of the PMOS transistor MP3 and the PMOS transistor MP4 are large enough to ensure that the PMOS transistor MP3 and the PMOS transistor MP4 do not break down due to the voltage between the input signal VP + and the input signal VN-, therefore, the PMOS transistor MP3 and the PMOS transistor MP4 in this case must select a MOS transistor with thick gate oxide to ensure that the MOS transistor will not break down in the case that the voltage between the input signal VP + and the input signal VN-is relatively large, and when the PMOS transistor MP3 and the PMOS transistor MP4 are selected as MOS transistors with thick gate oxide, the characteristics of the MOS transistor with thick gate oxide are not good as the thin gate oxide, which results in poor characteristics of the operational amplifier, the noise and area are too large.
Disclosure of Invention
The utility model aims at overcoming the not enough that exists among the prior art, provide a can improve the difference input structure of operational amplifier performance, it is guaranteeing under the condition of operational amplifier characteristic, can avoid because leading to the condition that the difference input geminate transistor is punctured under the great condition of voltage deviation between input signal VP + and the input signal VN-.
According to the technical scheme provided by the utility model, can improve the difference input structure of operational amplifier performance, including the main part, the main part includes main part difference geminate transistors and with the main part galvanometer of main part difference geminate transistor adaptation connection, MOS pipe in the main part difference geminate transistors is thin gate oxide MOS pipe, main part difference geminate transistors include main part first thin gate oxide MOS pipe and with the main part second thin gate oxide MOS pipe of main part first thin gate oxide MOS pipe adaptation;
the auxiliary differential pair transistors comprise auxiliary first thick gate oxide MOS transistors and auxiliary second thick gate oxide MOS transistors matched with the auxiliary first thick gate oxide MOS transistors, and the conductive channel types of the auxiliary first thick gate oxide MOS transistors and the auxiliary second thick gate oxide MOS transistors are consistent with the conductive channel types of the main first thin gate oxide MOS transistors and the main second thin gate oxide MOS transistors;
the voltage transmission tube group comprises a voltage transmission first MOS tube and a voltage transmission second MOS tube, the grid end of the auxiliary first thick gate oxide MOS tube is connected with the grid end of the main body second thin gate oxide MOS tube through the voltage transmission first MOS tube, the grid end of the auxiliary second thick gate oxide MOS tube is connected with the grid end of the main body first thin gate oxide MOS tube through the voltage transmission second MOS tube, and the grid end of the voltage transmission first MOS tube and the grid end of the voltage transmission second MOS tube are connected with the source end of the auxiliary first thick gate oxide MOS tube and the source end of the auxiliary second thick gate oxide MOS tube;
the grid end of the first thick grid oxygen MOS tube is assisted to receive an input signal VP +, the grid end of the second thick grid oxygen MOS tube is assisted to receive an input signal VN-, the grid end voltage of the first MOS tube is transmitted by voltage, the grid end voltage of the second MOS tube is transmitted by voltage can follow the input signal VP + or the input signal VN-, and after the first MOS tube is transmitted by voltage and the second MOS tube is transmitted by voltage, the difference value between the grid end voltage of the first thin grid oxygen MOS tube of the main body and the grid end voltage of the second thin grid oxygen MOS tube of the main body can be kept stable.
The type of a conducting channel of the voltage transmission first MOS tube is consistent with that of a conducting channel of the voltage transmission second MOS tube, and the type of the conducting channel of the voltage transmission first MOS tube is opposite to that of the conducting channel of the auxiliary first thick gate oxide MOS tube and that of the main first thin gate oxide MOS tube.
When the conduction channel type of the first thin gate oxide MOS tube of the main body and the conduction channel type of the second thin gate oxide MOS tube of the main body are both P channels,
the main body part further comprises a PMOS tube MP1, the main body part current mirror comprises an NMOS tube MN3 and an NMOS tube MN4, the drain end of the PMOS tube is connected with the source end of the first thin gate oxide MOS tube of the main body and the source end of the second thin gate oxide MOS tube of the main body, and the source end of the PMOS tube MP1 is connected with a power supply VDD; the drain end of the first thin gate oxide MOS tube of the main body is connected with the drain end of the NMOS tube NM3, the grid end of the NMOS tube MN3 and the grid end of the NMOS tube MN4, the drain end of the second thin gate oxide MOS tube of the main body is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN3 and the source end of the NMOS tube MN4 are both grounded; the voltage of the grid end of the first MOS tube is transmitted, and the voltage of the grid end of the second MOS tube is transmitted according to the smaller value of the input signal VP + and the input signal VN-;
the auxiliary part also comprises a PMOS tube MP2, the auxiliary part current mirror comprises an NMOS tube MN5 and an NMOS tube MN6, the source base of the PMOS tube MP2 is connected with a power supply VDD, the grid terminal of the PMOS tube MP2 is connected with the grid terminal of the PMOS tube MP1, the drain terminal of the PMOS tube MP2 is connected with the grid terminal of the first voltage transmission MOS tube, the grid terminal of the second voltage transmission MOS tube, the source terminal of the first auxiliary thick gate oxide MOS tube and the source terminal of the second auxiliary thick gate oxide MOS tube; the drain end of the auxiliary first thick gate oxide MOS tube is connected with the drain end of the NMOS tube MN5, the drain end of the auxiliary thick gate oxide second MOS tube is connected with the drain end of the NMOS tube MN6, the grid end of the NMOS tube MN6 and the grid end of the NMOS tube MN5, and the source end of the NMOS tube MN5 and the source end of the NMOS tube MN6 are both grounded.
The drain end of the PMOS transistor MP2 is connected to one end of the resistor R1, the gate end of the first voltage-transfer MOS transistor and the gate end of the second voltage-transfer MOS transistor, and the other end of the resistor R1 is connected to the source end of the auxiliary first thick-gate oxide MOS transistor and the source end of the auxiliary second thick-gate oxide MOS transistor.
When the conduction channel type of the first thin gate oxide MOS tube of the main body and the conduction channel type of the second thin gate oxide MOS tube of the main body are both N channels,
the main body part further comprises an NMOS tube MN12, the main body part current mirror comprises a PMOS tube MP7 and a PMOS tube MP8, the source end of the NMOS tube MN12 is grounded, the drain end of the NMOS tube MN12 is connected with the source end of a first thin-gate oxide MOS tube of the main body and the source end of a second thin-gate oxide MOS tube of the main body, the drain end of the first thin-gate oxide MOS tube of the main body is connected with the drain end of a PMOS tube MP7, the gate end of the PMOS tube MP7 and the gate end of the PMOS tube MP8, and the source end of the PMOS tube MP7 and the source end of a PMOS tube MP8 are connected with a; the voltage is transmitted to the larger value of the grid end voltage of the first MOS tube and the grid end voltage of the second MOS tube following the input signal VP + and the input signal VN-;
the auxiliary part further comprises an NMOS tube MN11, the current mirror of the auxiliary part comprises a PMOS tube MP11 and a PMOS tube MP12, the source end of the NMOS tube MN11 is grounded, the gate end of the NMOS tube MN11 is connected with the gate end of the NMOS tube MN12, the drain end of the NMOS tube MN11 is connected with the gate end of the first voltage transmission MOS tube, the gate end of the second voltage transmission MOS tube, the source end of the first auxiliary thick gate oxide MOS tube and the source end of the second auxiliary thick gate oxide MOS tube, the drain end of the first auxiliary thick gate oxide MOS tube is connected with the drain end of the PMOS tube MP11, the drain end of the second auxiliary thick gate oxide MOS tube is connected with the drain end of the PMOS tube MP12, the gate end of the PMOS tube MP12 and the gate end of the PMOS tube MP11, and the source ends of the PMOS tube MP11 and the PMOS tube 12 are connected with a power supply VDD.
The drain end of the NMOS transistor MN11 is connected with one end of a resistor R2, the grid end of a voltage transmission first MOS transistor and the grid end of a voltage transmission second MOS transistor, and the other end of the resistor R2 is connected with the source end of an auxiliary first thick gate oxide MOS transistor and the source end of an auxiliary second thick gate oxide MOS transistor.
The utility model has the advantages that: the differential input structure comprises a main body part, an auxiliary part and a voltage transmission pipe group, wherein the MOS pipes in the main body differential pair pipe in the main body part all adopt thin gate oxide MOS pipes, the MOS pipes in the auxiliary differential pair pipe in the auxiliary part all adopt thick gate oxide MOS pipes, the gate terminal of an auxiliary first thick gate oxide MOS pipe receives an input signal VP +, the gate terminal of an auxiliary second thick gate oxide MOS pipe receives an input signal VN-, the auxiliary first thick gate oxide MOS pipe and the auxiliary second thick gate oxide MOS pipe are utilized to avoid the damage of the MOS pipes caused by the larger difference between the input signal VP + and the input signal VN-and the larger differential pair pipe VGS, when the main body differential pair pipe adopts the thin gate oxide MOS pipe, the performance of an operational amplifier can be ensured, after the voltage transmission is carried out by the voltage transmission pipe group, the difference value between the gate terminal voltage of the main body first thin gate oxide MOS pipe and the gate terminal voltage of the main body second thin gate oxide MOS pipe can be ensured to be kept, is safe and reliable.
Drawings
Fig. 1 is a schematic diagram of a differential input structure of a conventional operational amplifier.
Fig. 2 is a schematic diagram of an implementation of the differential input structure of the present invention.
Fig. 3 is a schematic diagram of a second implementation of the differential input structure of the present invention.
Fig. 4 is a schematic diagram of a third embodiment of the differential input structure of the present invention.
Detailed Description
The invention is further described with reference to the following specific drawings and examples.
Under the condition of ensuring the characteristics of the operational amplifier, in order to avoid the condition that differential input geminate transistors are punctured under the condition that the voltage deviation between an input signal VP + and an input signal VN-is larger, the utility model discloses a main part, the main part comprises main part differential geminate transistors and main part current mirrors which are in adaptive connection with the main part differential geminate transistors, MOS (metal oxide semiconductor) tubes in the main part differential geminate transistors are thin gate oxide MOS tubes, and the main part differential geminate transistors comprise main part first thin gate oxide MOS tubes and main part second thin gate oxide MOS tubes which are adaptive to the main part first thin gate oxide MOS tubes;
the auxiliary differential pair transistors comprise auxiliary first thick gate oxide MOS transistors and auxiliary second thick gate oxide MOS transistors matched with the auxiliary first thick gate oxide MOS transistors, and the conductive channel types of the auxiliary first thick gate oxide MOS transistors and the auxiliary second thick gate oxide MOS transistors are consistent with the conductive channel types of the main first thin gate oxide MOS transistors and the main second thin gate oxide MOS transistors;
the voltage transmission tube group comprises a voltage transmission first MOS tube and a voltage transmission second MOS tube, the grid end of the auxiliary first thick gate oxide MOS tube is connected with the grid end of the main body second thin gate oxide MOS tube through the voltage transmission first MOS tube, the grid end of the auxiliary second thick gate oxide MOS tube is connected with the grid end of the main body first thin gate oxide MOS tube through the voltage transmission second MOS tube, and the grid end of the voltage transmission first MOS tube and the grid end of the voltage transmission second MOS tube are connected with the source end of the auxiliary first thick gate oxide MOS tube and the source end of the auxiliary second thick gate oxide MOS tube;
the grid end of the first thick grid oxygen MOS tube is assisted to receive an input signal VP +, the grid end of the second thick grid oxygen MOS tube is assisted to receive an input signal VN-, the grid end voltage of the first MOS tube is transmitted by voltage, the grid end voltage of the second MOS tube is transmitted by voltage can follow the input signal VP + or the input signal VN-, and after the first MOS tube is transmitted by voltage and the second MOS tube is transmitted by voltage, the difference value between the grid end voltage of the first thin grid oxygen MOS tube of the main body and the grid end voltage of the second thin grid oxygen MOS tube of the main body can be kept stable.
Specifically, the main body portion adopts an existing commonly-used differential input structure, namely the main body portion comprises main body differential pair transistors and a main body current mirror, the MOS transistors in the main body differential pair transistors all adopt thin gate oxide MOS transistors, and the main body differential pair transistors adopting the thin gate oxide MOS transistors can ensure that the operational amplifier has lower threshold voltage, good voltage-current characteristics, low noise and small relative area. The MOS tube in the main differential pair tube comprises a main first thin gate oxide MOS tube and a main second thin gate oxide MOS tube, namely the main first thin gate oxide MOS tube and the main second thin gate oxide MOS tube can form the differential pair tube, the main first thin gate oxide MOS tube and the main second thin gate oxide MOS tube are both thin gate oxide MOS tubes, and the main current mirror can be used as a load of the main differential pair tube.
The embodiment of the utility model provides an in, still include the auxiliary part with the main part adaptation, the auxiliary part forms operational amplifier's difference input structure with main part adaptation connection, wherein, operational amplifier's main parameter and performance are all decided by the main part (because whole operational amplifier's output signal is provided by the main part, the auxiliary part does not have other extra outputs except the voltage that provides node VA, thereby operational amplifier's main parameter and performance all are decided by the main part), and can not do too much requirement to the parameter and the performance of the device in the auxiliary part. When the specific structural form of the main body part is consistent with the differential input structure of the existing operational amplifier, namely the MOS tube in the main body differential pair tube of the main body part adopts a thin gate oxide MOS tube, the performance of the operational amplifier is consistent with that of the existing operational amplifier, and therefore the performance of the operational amplifier is ensured.
In a specific implementation, the auxiliary part comprises an auxiliary differential pair transistor and an auxiliary current mirror, and the auxiliary current mirror can be used as a load of the auxiliary differential pair transistor. The MOS tubes in the auxiliary differential pair tubes are all thick-gate oxygen MOS tubes, the auxiliary differential pair tubes are formed by an auxiliary first thick-gate oxygen MOS tube and an auxiliary second thick-gate oxygen MOS tube, the conducting channel types of the auxiliary first thick-gate oxygen MOS tube and the auxiliary second thick-gate oxygen MOS tube are consistent with the conducting channel type of the main first thin-gate oxygen MOS tube and the conducting communication type of the main second thin-gate oxygen MOS tube, namely when the conducting channel types of the main first thin-gate oxygen MOS tube and the main second thin-gate oxygen MOS tube are P-type, the conducting channel types corresponding to the auxiliary first thick-gate oxygen MOS tube and the auxiliary second thick-gate oxygen MOS tube are both P-type, and when the conducting channel types of the main first thin-gate oxygen MOS tube and the main second thin-gate oxygen MOS tube are N-type, the conducting channel types corresponding to the auxiliary first thick-gate oxygen MOS tube and the auxiliary second thick-gate oxygen MOS tube are both N-type.
The connection between the auxiliary part and the main body part can be realized through a voltage transmission pipe group, namely, the voltage transmission can be realized through the voltage transmission pipe group, the voltage transmission pipe group is composed of a voltage transmission first MOS pipe and a voltage transmission second MOS pipe, wherein the grid terminal of the auxiliary first thick gate oxide MOS pipe is connected with the grid terminal of the main body first thin gate oxide MOS pipe through the voltage transmission first MOS pipe, and the grid terminal of the auxiliary second thick gate oxide MOS pipe is connected with the grid terminal of the main body second thin gate oxide MOS pipe through the voltage transmission second MOS pipe. The grid terminal of the first voltage transmission MOS tube and the grid terminal of the second voltage transmission MOS tube are mutually connected with the source terminal of the auxiliary first thick gate oxide MOS tube and the source terminal of the auxiliary second thick gate oxide MOS tube, and the VA node can be formed after the grid terminal of the first voltage transmission MOS tube and the grid terminal of the second voltage transmission MOS tube are mutually connected.
The embodiment of the utility model provides an in, gate through supplementary first thick gate oxygen MOS pipe receives input signal VP +, gate through supplementary second thick gate oxygen MOS pipe receives input signal VN-, when input signal VP +, input signal VN-can make supplementary difference geminate transistors switch on, the grid end voltage of the first MOS pipe of voltage transmission, input signal VP + or input signal VN can be followed to the grid end voltage of the second MOS pipe of voltage transmission, through the first MOS pipe of voltage transmission, after voltage transmission second MOS pipe carries out voltage transmission, can make the grid end voltage of the first thin gate oxygen MOS pipe of main part and the difference of the grid end voltage of the thin gate oxygen MOS pipe of main part second remain stable. The specific selection of the gate terminal voltage of the voltage transmission first MOS transistor, the gate terminal voltage of the voltage transmission second MOS transistor following the input signal VP + and the input signal VN-is related to the specific magnitude of the input signal VP +, the specific magnitude of the input signal VN-, the conductive communication type of the voltage transmission first MOS transistor, and the conductive channel type of the main body first thin gate oxide MOS transistor, and is specifically described below through specific cases.
In specific implementation, the gate end voltage of the main first thin gate oxide MOS transistor and the gate end voltage of the main second thin gate oxide MOS transistor are kept stable, specifically, the gate end voltage of the main first thin gate oxide MOS transistor is close to the gate end voltage of the main second thin gate oxide MOS transistor, that is, the gate end voltage of the main first thin gate oxide MOS transistor and the gate end voltage of the main second thin gate oxide MOS transistor change within an allowable range (the specific allowable change range and the characteristic parameters of the operational amplifier are well known to those skilled in the art, and are not described herein again), so that the situation that the main first thin gate oxide MOS transistor and the main second thin gate oxide MOS transistor are broken down when the voltage between the input signal VP + and the input signal VN-is large is avoided.
The embodiment of the utility model provides an in, because supplementary first thick gate oxygen MOS pipe, supplementary second thick gate oxygen MOS pipe are thick gate oxygen MOS pipe, the VGS of the supplementary difference geminate transistor of constitution has higher withstand voltage, and the thick gate oxygen MOS pipe of supplementary difference geminate transistor can not influence operational amplifier's characteristic, thereby under the condition of guaranteeing the operational amplifier characteristic, in order to avoid because leading to the condition that the difference input geminate transistor is punctured under the great condition of voltage deviation between input signal VP + and the input signal VN-.
Furthermore, the type of the conduction channel of the voltage transmission first MOS tube is consistent with that of the voltage transmission second MOS tube, and the type of the conduction channel of the voltage transmission first MOS tube is opposite to that of the auxiliary first thick gate oxide MOS tube and that of the main body first thin gate oxide MOS tube.
As shown in fig. 2, when the conduction channel type of the bulk first thin-gate oxide MOS transistor and the conduction channel type of the bulk second thin-gate oxide MOS transistor are both P-channel,
the main body part further comprises a PMOS tube MP1, the main body part current mirror comprises an NMOS tube MN3 and an NMOS tube MN4, the drain end of the PMOS tube is connected with the source end of the first thin gate oxide MOS tube of the main body and the source end of the second thin gate oxide MOS tube of the main body, and the source end of the PMOS tube MP1 is connected with a power supply VDD; the drain end of the first thin gate oxide MOS tube of the main body is connected with the drain end of the NMOS tube NM3, the grid end of the NMOS tube MN3 and the grid end of the NMOS tube MN4, the drain end of the second thin gate oxide MOS tube of the main body is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN3 and the source end of the NMOS tube MN4 are both grounded; the voltage of the grid end of the first MOS tube is transmitted, and the voltage of the grid end of the second MOS tube is transmitted according to the smaller value of the input signal VP + and the input signal VN-;
the auxiliary part also comprises a PMOS tube MP2, the auxiliary part current mirror comprises an NMOS tube MN5 and an NMOS tube MN6, the source base of the PMOS tube MP2 is connected with a power supply VDD, the grid terminal of the PMOS tube MP2 is connected with the grid terminal of the PMOS tube MP1, the drain terminal of the PMOS tube MP2 is connected with the grid terminal of the first voltage transmission MOS tube, the grid terminal of the second voltage transmission MOS tube, the source terminal of the first auxiliary thick gate oxide MOS tube and the source terminal of the second auxiliary thick gate oxide MOS tube; the drain end of the auxiliary first thick gate oxide MOS tube is connected with the drain end of the NMOS tube MN5, the drain end of the auxiliary thick gate oxide second MOS tube is connected with the drain end of the NMOS tube MN6, the grid end of the NMOS tube MN6 and the grid end of the NMOS tube MN5, and the source end of the NMOS tube MN5 and the source end of the NMOS tube MN6 are both grounded.
In the embodiment of the present invention, the first thin gate oxide MOS transistor of the main body is the PMOS transistor MP4 in fig. 2, the second thin gate oxide MOS transistor of the main body is the PMOS transistor MP3 in fig. 2, the first thick gate oxide MOS transistor of the auxiliary body is the PMOS transistor MP5 in fig. 2, and the second thick gate oxide MOS transistor of the auxiliary body is the PMOS transistor MP6 in fig. 2. The first MOS transistor for voltage transmission is an NMOS transistor MN1 in fig. 2, and the second MOS transistor for voltage transmission is an NMOS transistor MN2 in fig. 2. The voltage Vbp is the gate terminal voltage of the PMOS transistor MP1 and the gate terminal voltage of the PMOS transistor MP2, and the bias current of the main differential pair transistor can be provided through the PMOS transistor MP1 and the bias current of the auxiliary differential pair transistor can be provided through the PMOS transistor MP 2. The drain electrode of the NMOS tube MN1 is connected with the gate terminal of the PMOS tube MP5, the source terminal of the NMOS tube MN1 is connected with the gate terminal of the PMOS tube MP4, the drain terminal of the NMOS tube MN2 is connected with the gate terminal of the PMOS tube MP6, and the source terminal of the NMOS tube MN2 is connected with the gate terminal of the PMOS tube MP 3.
When the differential input structure works specifically, the drain end of the PMOS tube MP4 and the drain end of the NMOS tube MN4 are connected with each other and then can be used as the output of the whole differential input structure, the PMOS tube MP1 and the PMOS tube MP2 can be conducted through the voltage Vbp, the input signal VP + and the input signal VN-are respectively loaded to the gate end of the PMOS tube MP5 and the gate end of the PMOS tube MP6, the PMOS tube MP5 and the PMOS tube MP6 are conducted through the input signal VP + and the input signal VN-, the gate end voltage of the NMOS tube MN1 and the gate end voltage of the NOMS tube MN2 follow the smaller value of the input signal VP + and the input signal VN-and lead the input signal VP + and the input signal VN-to be respectively transmitted to the gate end of the PMOS tube MP4 and the gate end of the PMOS tube MP3 through the NMOS tubes 96MN 37 and 2 according to enable the gate end voltage of the PMOS tube MP 48 and the PMOS tube MN4 to be close to the gate end voltage of the PMOS tube MP3 and the PMOS tube MP2 + and the input signal VP, When the input signal VN-deviation is large, large VGS withstand voltage is not needed, the situation that when the input signal VP + and the input signal VN-deviation is large, the PMOS tube MP3 and the PMOS tube MP4 of the thin gate oxide are damaged is avoided, and the safety of the PMOS tube MP3 and the PMOS tube MP4 which form the main body differential pair is ensured.
As shown in fig. 3, the drain terminal of the PMOS transistor MP2 is connected to one terminal of the resistor R1, the gate terminal of the first voltage-transfer MOS transistor and the gate terminal of the second voltage-transfer MOS transistor, and the other terminal of the resistor R1 is connected to the source terminal of the auxiliary first thick-gate MOS transistor and the source terminal of the auxiliary second thick-gate MOS transistor.
The embodiment of the utility model provides an in, can improve node VA's voltage through resistance R1, after node VA voltage increase, can make input signal VP +, input signal VN-pass through NMOS pipe MN1, the voltage of NMOS pipe MN2 transmission just bigger.
When the input signal VP + is close to the voltage of the input signal VN-, the voltage at the node VA is greater than the voltage of the input signal VP +, and the voltage at the node VA can be set by adjusting the voltage of the resistor R1. Generally, the voltage at the node VA is slightly larger than the sum of the threshold voltages of the input signal VP + and the NMOS transistor MN1 or the sum of the threshold voltages of the input signal VN-and the NMOS transistor MN2, which is related to the specific magnitude of the input signal VP + and the input signal VN-. From the voltage transfer characteristics of the NMOS, it can be understood that: the input signal VP +, VN-signal can completely pass through the NMOS transistor MN1 and the NMOS transistor MN2, i.e., the input signal VP +, VN-signal is not applied to the main differential pair transistor of the main body portion.
However, when the input signal VP + is greater than the input signal VN-, the voltage at the node VA is about the sum of the input signal VN-and the threshold voltage of the NMOS transistor MN2, and it can be understood from the voltage transfer characteristic of the NMOS transistor that: the input signal VN-can completely pass through the NMOS transistor MN2, that is, the voltage applied to the gate terminal of the PMOS transistor MP3 through the NMOS transistor MN2 approaches the input signal VN-. Since the voltage of the input signal VP + is greater than the voltage of the node VA (the difference between the input signal VP + and the input signal VN-is larger, and the voltage of the node VA is determined by the smaller voltage of the input signal VP + and the input signal VN-, the voltage of the input signal VP + is certainly greater than the voltage of the node VA when the input signal VP + is greater than the input signal VN +), according to the voltage transfer characteristics of the NMOS transistor, thus, the input signal VP + is limited by the NMOS transistor MN1 (limited to the input signal VN-or infinitely close to the input signal VN-, the specific case is related to the characteristic parameters of the NMOS transistor MN1 and the NMOS transistor MN2, when the characteristic parameters of the NMOS transistor MN1 and the NMOS transistor MN2 are the same, the specific case is limited to the input signal VN-, the specific case is well known by those skilled in the art and is not described herein in detail), the voltage applied to the gate terminal of PMOS transistor MP4 through NMOS transistor MN1 is close to the input signal VN-.
When the input signal VN-is greater than the input signal VP +, the transmission process of the input signal VP +, and the input signal VN-to the main differential pair of the main body is the same as described above, and will not be described herein again.
As shown in fig. 4, when the conduction channel type of the bulk first thin-gate oxide MOS transistor and the conduction channel type of the bulk second thin-gate oxide MOS transistor are both N-channels,
the main body part further comprises an NMOS tube MN12, the main body part current mirror comprises a PMOS tube MP7 and a PMOS tube MP8, the source end of the NMOS tube MN12 is grounded, the drain end of the NMOS tube MN12 is connected with the source end of a first thin-gate oxide MOS tube of the main body and the source end of a second thin-gate oxide MOS tube of the main body, the drain end of the first thin-gate oxide MOS tube of the main body is connected with the drain end of a PMOS tube MP7, the gate end of the PMOS tube MP7 and the gate end of the PMOS tube MP8, and the source end of the PMOS tube MP7 and the source end of a PMOS tube MP8 are connected with a; the voltage is transmitted to the larger value of the grid end voltage of the first MOS tube and the grid end voltage of the second MOS tube following the input signal VP + and the input signal VN-;
the auxiliary part further comprises an NMOS tube MN11, the current mirror of the auxiliary part comprises a PMOS tube MP11 and a PMOS tube MP12, the source end of the NMOS tube MN11 is grounded, the gate end of the NMOS tube MN11 is connected with the gate end of the NMOS tube MN12, the drain end of the NMOS tube MN11 is connected with the gate end of the first voltage transmission MOS tube, the gate end of the second voltage transmission MOS tube, the source end of the first auxiliary thick gate oxide MOS tube and the source end of the second auxiliary thick gate oxide MOS tube, the drain end of the first auxiliary thick gate oxide MOS tube is connected with the drain end of the PMOS tube MP11, the drain end of the second auxiliary thick gate oxide MOS tube is connected with the drain end of the PMOS tube MP12, the gate end of the PMOS tube MP12 and the gate end of the PMOS tube MP11, and the source ends of the PMOS tube MP11 and the PMOS tube 12 are connected with a power supply VDD.
In this embodiment, the main body first thin gate oxide MOS transistor is an NMOS transistor MN8 in fig. 4, the main body second thin gate oxide MOS transistor is an NMOS transistor MN7 in fig. 4, the auxiliary first thick gate oxide MOS transistor is an NMOS transistor MN9 in fig. 4, the auxiliary second thick gate oxide MOS transistor is an NMOS transistor MN10 in fig. 4, the voltage transmission first MOS transistor is a PMOS transistor MP9 in fig. 4, the voltage transmission second MOS transistor is a PMOS transistor MP10 in fig. 4, and Vbn is a gate terminal voltage of an NMOS transistor MN11 and an NMOS transistor MN 12. In specific implementation, the drain terminal of the NMOS transistor MN11 is connected to one end of the resistor R2, the gate terminal of the voltage transmission first MOS transistor, and the gate terminal of the voltage transmission second MOS transistor, and the other end of the resistor R2 is connected to the source terminal of the auxiliary first thick-gate oxide MOS transistor and the source terminal of the auxiliary second thick-gate oxide MOS transistor.
The embodiment of the utility model provides an in, the conducting channel type of the thin gate oxide MOS pipe of the first thin gate oxide MOS pipe of main part, the conducting channel type of the thin gate oxide MOS pipe of main part second are the N channel, and the voltage of node VA follows the great value in input signal VP +, the input signal VN-. The working process of the formed differential input structure is similar to the description that the conductive channel type of the main body first thin gate oxide MOS transistor is a P channel, and specific reference may be made to the description above, and details are not repeated here.
Claims (6)
1. A differential input structure capable of improving performance of an operational amplifier comprises a main body part, wherein the main body part comprises main body differential pair transistors and main body current mirrors in adaptive connection with the main body differential pair transistors, MOS (metal oxide semiconductor) tubes in the main body differential pair transistors are all thin gate oxide MOS tubes, and the main body differential pair transistors comprise main body first thin gate oxide MOS tubes and main body second thin gate oxide MOS tubes in adaptive connection with the main body first thin gate oxide MOS tubes; the method is characterized in that:
the auxiliary differential pair transistors comprise auxiliary first thick gate oxide MOS transistors and auxiliary second thick gate oxide MOS transistors matched with the auxiliary first thick gate oxide MOS transistors, and the conductive channel types of the auxiliary first thick gate oxide MOS transistors and the auxiliary second thick gate oxide MOS transistors are consistent with the conductive channel types of the main first thin gate oxide MOS transistors and the main second thin gate oxide MOS transistors;
the voltage transmission tube group comprises a voltage transmission first MOS tube and a voltage transmission second MOS tube, the grid end of the auxiliary first thick gate oxide MOS tube is connected with the grid end of the main body second thin gate oxide MOS tube through the voltage transmission first MOS tube, the grid end of the auxiliary second thick gate oxide MOS tube is connected with the grid end of the main body first thin gate oxide MOS tube through the voltage transmission second MOS tube, and the grid end of the voltage transmission first MOS tube and the grid end of the voltage transmission second MOS tube are connected with the source end of the auxiliary first thick gate oxide MOS tube and the source end of the auxiliary second thick gate oxide MOS tube;
the grid end of the first thick grid oxygen MOS tube is assisted to receive an input signal VP +, the grid end of the second thick grid oxygen MOS tube is assisted to receive an input signal VN-, the grid end voltage of the first MOS tube is transmitted by voltage, the grid end voltage of the second MOS tube is transmitted by voltage can follow the input signal VP + or the input signal VN-, and after the first MOS tube is transmitted by voltage and the second MOS tube is transmitted by voltage, the difference value between the grid end voltage of the first thin grid oxygen MOS tube of the main body and the grid end voltage of the second thin grid oxygen MOS tube of the main body can be kept stable.
2. A differential input structure capable of improving the performance of an operational amplifier as claimed in claim 1, wherein: the type of a conducting channel of the voltage transmission first MOS tube is consistent with that of a conducting channel of the voltage transmission second MOS tube, and the type of the conducting channel of the voltage transmission first MOS tube is opposite to that of the conducting channel of the auxiliary first thick gate oxide MOS tube and that of the main first thin gate oxide MOS tube.
3. A differential input structure capable of improving the performance of an operational amplifier as claimed in claim 2, wherein: when the conduction channel type of the first thin gate oxide MOS tube of the main body and the conduction channel type of the second thin gate oxide MOS tube of the main body are both P channels,
the main body part further comprises a PMOS tube MP1, the main body part current mirror comprises an NMOS tube MN3 and an NMOS tube MN4, the drain end of the PMOS tube is connected with the source end of the first thin gate oxide MOS tube of the main body and the source end of the second thin gate oxide MOS tube of the main body, and the source end of the PMOS tube MP1 is connected with a power supply VDD; the drain end of the first thin gate oxide MOS tube of the main body is connected with the drain end of the NMOS tube NM3, the grid end of the NMOS tube MN3 and the grid end of the NMOS tube MN4, the drain end of the second thin gate oxide MOS tube of the main body is connected with the drain end of the NMOS tube MN4, and the source end of the NMOS tube MN3 and the source end of the NMOS tube MN4 are both grounded; the voltage of the grid end of the first MOS tube is transmitted, and the voltage of the grid end of the second MOS tube is transmitted according to the smaller value of the input signal VP + and the input signal VN-;
the auxiliary part also comprises a PMOS tube MP2, the auxiliary part current mirror comprises an NMOS tube MN5 and an NMOS tube MN6, the source base of the PMOS tube MP2 is connected with a power supply VDD, the grid terminal of the PMOS tube MP2 is connected with the grid terminal of the PMOS tube MP1, the drain terminal of the PMOS tube MP2 is connected with the grid terminal of the first voltage transmission MOS tube, the grid terminal of the second voltage transmission MOS tube, the source terminal of the first auxiliary thick gate oxide MOS tube and the source terminal of the second auxiliary thick gate oxide MOS tube; the drain end of the auxiliary first thick gate oxide MOS tube is connected with the drain end of the NMOS tube MN5, the drain end of the auxiliary thick gate oxide second MOS tube is connected with the drain end of the NMOS tube MN6, the grid end of the NMOS tube MN6 and the grid end of the NMOS tube MN5, and the source end of the NMOS tube MN5 and the source end of the NMOS tube MN6 are both grounded.
4. A differential input structure capable of improving the performance of an operational amplifier as claimed in claim 3, wherein: the drain end of the PMOS transistor MP2 is connected to one end of the resistor R1, the gate end of the first voltage-transfer MOS transistor and the gate end of the second voltage-transfer MOS transistor, and the other end of the resistor R1 is connected to the source end of the auxiliary first thick-gate oxide MOS transistor and the source end of the auxiliary second thick-gate oxide MOS transistor.
5. A differential input structure capable of improving the performance of an operational amplifier as claimed in claim 2, wherein: when the conduction channel type of the first thin gate oxide MOS tube of the main body and the conduction channel type of the second thin gate oxide MOS tube of the main body are both N channels,
the main body part further comprises an NMOS tube MN12, the main body part current mirror comprises a PMOS tube MP7 and a PMOS tube MP8, the source end of the NMOS tube MN12 is grounded, the drain end of the NMOS tube MN12 is connected with the source end of a first thin-gate oxide MOS tube of the main body and the source end of a second thin-gate oxide MOS tube of the main body, the drain end of the first thin-gate oxide MOS tube of the main body is connected with the drain end of a PMOS tube MP7, the gate end of the PMOS tube MP7 and the gate end of the PMOS tube MP8, and the source end of the PMOS tube MP7 and the source end of a PMOS tube MP8 are connected with a; the voltage is transmitted to the larger value of the grid end voltage of the first MOS tube and the grid end voltage of the second MOS tube following the input signal VP + and the input signal VN-;
the auxiliary part further comprises an NMOS tube MN11, the current mirror of the auxiliary part comprises a PMOS tube MP11 and a PMOS tube MP12, the source end of the NMOS tube MN11 is grounded, the gate end of the NMOS tube MN11 is connected with the gate end of the NMOS tube MN12, the drain end of the NMOS tube MN11 is connected with the gate end of the first voltage transmission MOS tube, the gate end of the second voltage transmission MOS tube, the source end of the first auxiliary thick gate oxide MOS tube and the source end of the second auxiliary thick gate oxide MOS tube, the drain end of the first auxiliary thick gate oxide MOS tube is connected with the drain end of the PMOS tube MP11, the drain end of the second auxiliary thick gate oxide MOS tube is connected with the drain end of the PMOS tube MP12, the gate end of the PMOS tube MP12 and the gate end of the PMOS tube MP11, and the source ends of the PMOS tube MP11 and the PMOS tube 12 are connected with a power supply VDD.
6. The differential input structure capable of improving the performance of an operational amplifier according to claim 5, wherein: the drain end of the NMOS transistor MN11 is connected with one end of a resistor R2, the grid end of a voltage transmission first MOS transistor and the grid end of a voltage transmission second MOS transistor, and the other end of the resistor R2 is connected with the source end of an auxiliary first thick gate oxide MOS transistor and the source end of an auxiliary second thick gate oxide MOS transistor.
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| CN201921535325.4U CN210157150U (en) | 2019-09-17 | 2019-09-17 | Differential input structure capable of improving performance of operational amplifier |
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Cited By (1)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110492852A (en) * | 2019-09-17 | 2019-11-22 | 江苏润石科技有限公司 | The differential input structure of operational amplifier performance can be improved |
| CN110492852B (en) * | 2019-09-17 | 2024-05-17 | 江苏润石科技有限公司 | Differential input structure capable of improving operational amplifier performance |
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