CN210111018U

CN210111018U - Double-ridge waveguide and bare chip testing device

Info

Publication number: CN210111018U
Application number: CN201921186667.XU
Authority: CN
Inventors: 汪佳娣; 刘贵亚; 凌玲
Original assignee: Hefei Should Be Electronic Technology Co Ltd
Current assignee: Hefei Should Be Electronic Technology Co Ltd
Priority date: 2019-07-25
Filing date: 2019-07-25
Publication date: 2020-02-21
Anticipated expiration: 2029-07-25

Abstract

The utility model discloses a double-ridge waveguide and a bare chip testing device belongs to the chip test field. A double-ridge waveguide comprises an outer cavity and an inner cavity, the section of the outer cavity is an isosceles trapezoid, a pair of linear gradually-changed edges are symmetrically arranged in the inner cavity of the double-ridge waveguide, an input port of the double-ridge waveguide is a standard waveguide port with the height-to-width ratio of 2:1, and an output port of the double-ridge waveguide is a non-standard rectangular waveguide port with the height-to-width ratio of (5-10): 1. The utility model provides a bare chip testing arrangement, includes the anchor clamps body to and connect input ridge waveguide and output ridge waveguide at anchor clamps body both ends, input ridge waveguide and output ridge waveguide structure are the same and set up with the central axis symmetry of anchor clamps body, and input ridge waveguide and output ridge waveguide adopt foretell double-ridge waveguide. The utility model discloses a double-ridge waveguide improves through the cooperation to external cavity and inner chamber for testing arrangement can cover and exceed triple frequency ultra wide band frequency band scope, is showing and is improving efficiency of software testing.

Description

Double-ridge waveguide and bare chip testing device

Technical Field

The utility model belongs to the chip testing field, more specifically the utility model relates to a double-ridge waveguide and a bare chip testing arrangement.

Background

Chip processing needs to go through a series of process links such as chemistry, optics, metallurgy, hot working, and various defects can be introduced to every technology, if these trouble chips make the product, can cause the maintenance of whole product even change, and the cost is extremely high. Therefore, testing and screening of the chip at the early stage are essential and important links. The testing of the chip comprises bare chip testing and packaged chip testing, and the testing mainly analyzes the reliability and failure mechanism of the chip. At present, the reliability and failure mechanism test research of the packaged chip is relatively mature, and the methods for testing the bare chip mainly comprise a probe station test method and a clamp test method.

The probe station testing method is difficult to control the pressure of the probe, so that the chip is inevitably damaged, the probe station testing method can only realize the electrical characteristic test and can not carry out burn-in screening under the temperature and environment control, if a further reliable product is to be obtained, the method is limited, and burn-in life test can only be replaced by some testing methods and data analysis. The clamp test method is an important subject in bare chip test, has high flexibility, can perform various reliability tests, and is particularly suitable for the requirements of small-batch and multi-variety high-reliability products.

The existing test fixture or test device generally adopts the method that a chip is sintered on a detection carrier, the chip is disassembled through a sintering process after the detection is finished, the chip is used for the production of the next process, a small amount of traces are left on the chip through the repeated heating and sintering process, the reliability of the chip is adversely affected, and the chip is polluted by sintering residues in the process.

On the other hand, the detection of the chip has frequency band and power requirements on the testing device. The existing ultra-wideband high-power amplifier product generally needs to use a plurality of chips for power synthesis, the number of the chips is large (more than 10 chips), phase consistency of the chips used in three octave frequency band ranges needs to be ensured, how to obtain phase information of the chips is always a complicated and redundant process, and the traditional method is obtained by multiple frequency division band measurement through non-detachable chip testing equipment. Or to limit the chip lot to ensure that the phase consistency of the chips is as high as possible, but this approach is too radical and also has some uncertainty. Or the chip supplier performs a probe station test on each chip to obtain the phase information of each chip, but the cost is relatively high.

Meanwhile, for the test of a high-power amplifier chip, in order to meet the power requirement, the input connector and the output connector need to adopt waveguide structures, but a standard waveguide test device cannot simultaneously cover the frequency tripling ultra-wideband frequency range, a plurality of frequency division test equipment needs to be adopted, the problem that multiple tests are needed when a single chip is introduced is solved, and the operation process is complicated. Moreover, if the existing fixture which needs to be sintered, fixed and disassembled is used, the tested chip can also be subjected to multiple sintering processes in sequence, and the performance and reliability of the chip and the whole machine product are seriously influenced.

How to design a testing device which can not affect the performance of the chip obviously and can be conveniently used for testing the ultra-wideband high-power chip, the testing efficiency is improved, and the reliability of the product is improved, which is the research direction of the applicant.

Disclosure of Invention

1. Problems to be solved

To current bare chip testing arrangement, the coverage bandwidth scope is narrower, can't satisfy the high-power chip test demand of ultra wide band, leads to the high-power chip test of ultra wide band to need to carry out a lot of and measures, problem that efficiency of software testing is low, the utility model provides a two ridge waveguide and a bare chip testing arrangement. The utility model discloses a double-ridge waveguide improves through the cooperation to external cavity and inner chamber for testing arrangement can cover and exceed triple frequency ultra wide band frequency band scope, is showing and is improving efficiency of software testing.

2. Technical scheme

In order to solve the above problems, the utility model adopts the following technical proposal.

A double-ridge waveguide comprises an outer cavity and an inner cavity arranged in the outer cavity, the section of the outer cavity is an isosceles trapezoid, a pair of ridge edges is symmetrically arranged on the inner wall of the inner cavity, the thickness of each ridge edge is linearly reduced along the direction from the upper bottom end to the lower bottom end of the isosceles trapezoid, the port of the double-ridge waveguide at the upper bottom end of the isosceles trapezoid is a standard waveguide port with the height-to-width ratio of 2:1, and the port of the double-ridge waveguide at the lower bottom end of the isosceles trapezoid is a non-standard rectangular waveguide port with the height-to-width ratio of (5-10): 1.

Preferably, the ridge length is the same as the double ridge waveguide length.

A bare chip testing device comprises a clamp body, an input ridge waveguide and an output ridge waveguide, wherein the input ridge waveguide and the output ridge waveguide are identical in structure and are symmetrically arranged with the central axis of the clamp body, the input ridge waveguide and the output ridge waveguide adopt the double ridge waveguide, the lower bottom end of the input ridge waveguide in an isosceles trapezoid is connected with an inlet end of the clamp body, and the lower bottom end of the output ridge waveguide in the isosceles trapezoid is connected with an outlet end of the clamp body.

Preferably, the input ridge waveguide comprises a front cavity and a rear cavity which are processed in a split manner, the front cavity and the rear cavity are spliced to form an inner cavity, and the pair of ridges are respectively arranged on the opposite surfaces of the front cavity and the rear cavity.

Preferably, the pair of ridges are respectively disposed on central axes of the front cavity and the rear cavity opposite to each other.

Preferably, the clamp body comprises a waveguide upper cavity and a waveguide lower cavity which are connected, and the waveguide upper cavity and the waveguide lower cavity are spliced to form a first waveguide cavity;

and a space synthesis single card is movably arranged on the upper end surface of the waveguide lower cavity and is used for bearing a chip.

Preferably, the space synthesis single card comprises a chip bearing PCB board and a chip fixing caliper, the chip bearing PCB board is fixedly connected to the chip fixing caliper, and the chip fixing caliper is used for fixing a chip;

and a placing groove matched with the chip fixing caliper in shape is arranged on the upper end surface of the waveguide lower cavity.

Preferably, a hole communicated with the placing groove is formed in the side face of the lower waveguide cavity.

Preferably, the chip fixing caliper is provided with a first sintering groove matched with the chip bearing PCB in shape, and the chip fixing caliper is further provided with a second sintering groove matched with the chip.

Preferably, the first waveguide cavity is a non-standard rectangular waveguide cavity with the height-width ratio of (5-10): 1.

Preferably, the waveguide module further comprises an upper cavity shielding cover, and a first through hole matched with the upper cavity shielding cover in shape is formed in the upper cavity of the waveguide; and

and the lower cavity shielding cover is provided with a second through hole matched with the lower cavity shielding cover, and the upper end of the lower cavity shielding cover is abutted to the lower end of the chip fixing clamp.

Preferably, an input waveguide cavity is arranged in the input ridge waveguide, an output waveguide cavity is arranged in the output ridge waveguide, and the input waveguide cavity, the first waveguide cavity and the output waveguide cavity are sequentially connected and communicated.

3. Advantageous effects

Compared with the prior art, the beneficial effects of the utility model are that:

(1) the utility model discloses a double-ridge waveguide, including the outer cavity, and the inner chamber that sets up in the outer cavity, wherein the section of outer cavity is isosceles trapezoid, the thickness of ridge simultaneously reduces along isosceles trapezoid's upper bottom to lower bottom direction linearity, double-ridge waveguide inner chamber is by the standard waveguide mouth that aspect ratio is 2:1, to the waveguide chamber that the nonstandard rectangular waveguide mouth that aspect ratio is (5 ~ 10):1 passes through, the slow change of low impedance to high impedance has been realized, make the double-ridge waveguide that finally obtains can cover and exceed triple frequency ultra wide band frequency band scope, relative bandwidth reaches 100%, make chip no longer need through many times of tests in the high-power amplifier product of ultra wide band, show improvement efficiency of software testing;

(2) the utility model discloses an anchor clamps body, cavity under cavity and the waveguide on the waveguide that link to each other including the components of a whole that can function independently, still include the synthetic single card in space that sets up separately with cavity and waveguide under cavity on the waveguide, during the chip test, the chip is fixed the sintering earlier on the synthetic single card in space, place the synthetic single card activity in space that bears the weight of the chip on cavity under the waveguide again, after finishing detecting, the chip does not need the sintering to dismantle, the synthetic single card in space that sinters the chip directly produces as a part of complete machine product, save the chip of sintering dismantlement step, can not leave the residue, the performance and the reliability of chip can be guaranteed; the design also ensures the electrical property and reliability of the space synthesis single card while testing the chip, saves the independent detection of the space synthesis single card, obviously improves the production efficiency and also ensures the overall performance of the product;

(3) the utility model discloses a bare chip testing device has realized the combination of microwave passive device (two ridge waveguides) and active device (anchor clamps body), has expanded chip testing device's new field, has realized that high-power scene requires under the input-output structure be the waveguide structure condition, and single testing device covers the function that exceeds triple frequency range ultra wide band frequency band scope to improve test efficiency, assembly scheduling problem in the complete machine product production process, very big reduction product production cycle and cost; meanwhile, through high-power test, relevant aging tests are carried out, and the reliability requirement of the whole product is improved.

Drawings

FIG. 1 is an exploded view of the bare chip test apparatus of the present application;

FIG. 2 is an overall assembly view of the bare chip test apparatus of the present application;

FIG. 3 is a side cross-sectional view of a clamp body according to the present application.

In the figure:

1. a clamp body; 101. a waveguide upper cavity; 102. a waveguide lower cavity; 103. a first waveguide cavity; 104. an upper cavity shielding cover; 105. a lower cavity shielding cover;

2. an input ridge waveguide; 201. an input waveguide cavity; 202. ridge edges; 203. a front cavity; 204. a rear cavity;

3. an output ridge waveguide; 301. an output waveguide cavity;

4. spatially synthesizing a single card; 401. the chip bears the PCB board; 402. fixing the calipers by the chips; 403. and a second sintering groove.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Furthermore, the technical features mentioned in the embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

It should be noted that, in the description of the present invention, the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

Example 1

This embodiment provides a double-ridge waveguide, including outer cavity to and the inner chamber that sets up in the outer cavity, as shown in fig. 2, define the X direction and be this application length direction, Y direction are this application width direction, Z direction are this application direction of height. The profile of the outer cavity of the double-ridge waveguide, that is, the cross section perpendicular to the width direction, is an isosceles trapezoid, a pair of ridge edges 202 are symmetrically arranged in the inner cavity of the double-ridge waveguide, the thickness of the ridge edges 202 is linearly reduced along the direction from the upper bottom end to the lower bottom end of the isosceles trapezoid, the port of the double-ridge waveguide at the upper bottom end of the isosceles trapezoid is a standard waveguide port with the height-to-width ratio of 2:1, the height-to-width ratio refers to the ratio of the height to the dimension in the width direction, the port of the double-ridge waveguide at the lower bottom end of the isosceles trapezoid is a non-standard rectangular waveguide port with the height-to-width ratio of (5-10): 1, the inner cavity of the double-ridge waveguide is a waveguide cavity which is transited from the upper bottom end to the lower bottom end by the standard waveguide, which is different from the existing ridge waveguide, although the function of widening the broadband can be realized, and the working, through the fact that the outer cavity of the double-ridge waveguide gradually widens from the upper bottom end to the lower bottom end in a horn shape and the ridge edges 202 gradually change from the upper bottom end to the lower bottom end in a linear mode, the ratio of height to width of the port at the upper bottom end of the double-ridge waveguide to the port at the lower bottom end is from 2:1 to (5-10): 1, the inner structure and the outer structure are matched with each other to achieve slow change from low impedance to high impedance, and the finally obtained double-ridge waveguide can cover the range exceeding the triple octave ultra-wideband frequency band.

It should be noted that, in order to avoid abrupt change of impedance and realize slow transition of electromagnetic waves, the gradual change mode of the ridge 202 may adopt transition from linear gradual change to a nonlinear smooth curved surface.

The length of the ridge 202 of the present embodiment is the same as the length of the double-ridge waveguide, which is the height of the isosceles trapezoid, and this design avoids impedance abrupt change and further widens the frequency band range.

Example 2

As shown in fig. 1, the present embodiment provides a bare chip testing fixture, which includes a fixture body 1, where the fixture body 1 includes a waveguide upper cavity 101 and a waveguide lower cavity 102 connected to each other, where both the center inside the waveguide upper cavity 101 and the center inside the waveguide lower cavity 102 are provided with a groove, and when the waveguide upper cavity 101 and the waveguide lower cavity 102 are vertically assembled, the two grooves form a first waveguide cavity 103, and during assembly, the front and rear sides of the waveguide lower cavity 102 and the waveguide upper cavity 101 on the cavity are locked by screws. The space synthesis single card 4 is movably arranged on the upper end face of the waveguide lower cavity 102, and the space synthesis single card 4 is used for bearing a chip.

The space synthesis single card 4 is a part of a chip complete machine product, the complete machine product of the embodiment is specifically a power amplifier product, and meanwhile, the space synthesis single card 4 is also used as a chip test carrier for fixing a chip and carrying out a test, because the space synthesis single card 4 is movably placed on the waveguide lower cavity 102, after the chip test is completed, the chip does not need to be detached from the space synthesis single card 4, and the production of the complete machine product is carried out along with the space synthesis single card 4, the chip of a sintering and detaching process is omitted, no residue is left, and the performance and the reliability of the chip are ensured.

The space synthesis single card 4 comprises a chip bearing PCB board 401 and a chip fixing caliper 402, the chip bearing PCB board 401 is fixedly connected to the chip fixing caliper 402, concretely, a first sintering groove matched with the chip bearing PCB board 401 in shape is arranged on the chip fixing caliper 402, the chip bearing PCB board 401 is fixedly sintered on the upper end face of the chip fixing caliper 402 through welding fluxes, and a second sintering groove 403 matched with the chip is further arranged on the chip fixing caliper 402 and used for sintering the fixed chip. The space synthesis single card 4 sintered with the chip is placed in a placing groove formed in the upper end face of the waveguide lower cavity 102, as shown in fig. 3, the chip fixing caliper 402 of the embodiment is a long strip-shaped inclined single card, the thickness of the chip fixing caliper is gradually increased along the width direction, an inclined groove is formed in the upper end face of the waveguide lower cavity 102, the shape of the inclined groove is matched with the chip fixing caliper 402, and the flatness of the upper end face of the chip fixing caliper 402 is guaranteed. It should be noted here that the shape of the placement groove is determined according to the shape of the single card of the whole product. So as to ensure that the electromagnetic wave is symmetrically and uniformly propagated in the first waveguide cavity 103 and reduce energy loss.

It should be noted that the chip-carrying PCB 401 is provided with a microstrip circuit, connected to an external power source, excited by a power feeder, and the spatially-combined single card 4 is a conductor, so as to supply power to the chip, and thus the test fixture has testability on electrical performance of the chip. The specific structural design is that the side surface of the waveguide lower cavity 102 is provided with a hole and is communicated with the deeper part of the inclined placement groove, and the hole is provided with a power supply feeder excitation port. Therefore, through the design, the electrical performance and reliability of the space synthesis single card 4 are tested while the chip is tested, and when the detected space synthesis single card 4 sintered with the chip is directly used for the production of the whole product, the independent detection of the space synthesis single card 4 is saved, the production efficiency is obviously improved, and the overall performance of the product is also ensured.

The test fixture of this embodiment still includes lower chamber shield cover 105, under the waveguide under cavity 102 on the terminal surface seted up with the second through-hole of lower chamber shield cover 105 adaptation, during the assembly, lower chamber shield cover 105 link up the second through-hole, and lower chamber shield cover 105 upper end offsets with chip fixed caliper 402 bottom, and the rethread screw is installed lower chamber shield cover 105 under the waveguide on cavity 102 terminal surface, lower chamber shield cover 105 and chip fixed caliper 402 lower part regional abundant contact play make the regional ground connection effect in chip fixed caliper 402 lower part.

Example 3

The structure of the bare chip test fixture of the embodiment is basically the same as that of the embodiment 2, and further, the bare chip test fixture further comprises an upper cavity shielding cover 104, a first through hole matched with the upper cavity shielding cover 104 in shape is formed in the upper cavity 101 of the waveguide, during assembly, the upper cavity shielding cover 104 is inserted into the first through hole and is installed on the upper cavity 101 of the waveguide through 4 screws, the design can observe the test state of the chip by opening the upper cavity shielding cover 104 at any time, for example, the working temperature of the test chip and whether the chip is burnt or damaged or not, and can eliminate the resonance phenomenon in the first waveguide cavity 103 or control the generation of undesirable phenomena such as self-excitation of the chip. The stability and the security of chip test have further been guaranteed.

Example 4

The embodiment provides a bare chip testing device, which comprises a clamp body 1, an input ridge waveguide 2 and an output ridge waveguide 3, wherein the input ridge waveguide 2 and the output ridge waveguide 3 are identical in structure and symmetrically arranged with the central axis of the clamp body 1, and the input ridge waveguide 2 and the output ridge waveguide 3 are both double ridge waveguides of the embodiment 1.

The clamp body 1 comprises a waveguide upper cavity 101 and a waveguide lower cavity 102 which are connected, when the waveguide upper cavity 101 and the waveguide lower cavity 102 are vertically spliced, a first waveguide cavity 103 is formed, a space synthesis single card 4 is movably placed on the upper end face of the waveguide lower cavity 102, the space synthesis single card 4 is used for bearing a chip, the space synthesis single card 4 comprises a chip bearing PCB 401 and a chip fixing caliper 402, the chip bearing PCB 401 is sintered on the chip fixing caliper 402, and a second sintering groove 403 matched with the chip is further formed in the chip fixing caliper 402 and used for sintering the fixed chip. The space synthesis single card 4 sintered with the chip is placed in a placing groove formed in the upper end face of the waveguide lower cavity 102; the clamp body 1 further comprises a lower cavity shielding cover 105 and an upper cavity shielding cover 104, a second through hole matched with the lower cavity shielding cover 105 is formed in the waveguide lower cavity 102, and a first through hole matched with the upper cavity shielding cover 104 in shape is formed in the waveguide upper cavity 101.

Input ridge waveguide 2 is connected at first waveguide chamber 103 entry end, output ridge waveguide 3 is connected at first waveguide chamber 103 exit end, use input ridge waveguide 2 as an example, input ridge waveguide 2's outer cavity is the input in isosceles trapezoid's last bottom, isosceles trapezoid's lower bottom is the output, during the assembly, input ridge waveguide 2's lower bottom end is connected at anchor clamps body 1 entry end, output ridge waveguide 3's lower bottom end is connected at anchor clamps body 1 exit end, between input ridge waveguide 2 and the anchor clamps body 1, all lock and install fixedly through waveguide flange dish screw thread between anchor clamps body 1 and the output ridge waveguide 3, thereby accomplish whole bare chip testing arrangement's connection and fixed.

The bare chip testing device of the embodiment realizes the combination of the microwave passive device (the input ridge waveguide 2 and the output ridge waveguide 3) and the active device (the clamp body 1), and expands the new field of the chip testing device, so that the chip testing device with the design can realize the high-power bare chip testing work with wider frequency band, the bandwidth can reach three octaves, and the relative bandwidth reaches 100%.

The input ridge waveguide 2 and the output ridge waveguide 3 of the present embodiment are both manufactured by split processing, taking the input ridge waveguide 2 as an example, the outer cavity of the input ridge waveguide 2 includes a front cavity 203 and a rear cavity 204, and compared with an integrated processing technology, the split processing technology of the double ridge waveguide has lower cost, and the split processing technology is simpler and easier to operate aiming at the gradual change design of the double ridge waveguide of the present application. During processing, one of the pair of ridges 202 is arranged on the front cavity 203, the other ridge is arranged on the rear cavity 204, and the ridges are arranged on the central axes of the opposite surfaces of the front cavity 203 and the rear cavity 204, so that electromagnetic waves are symmetrically and uniformly propagated in the first waveguide cavity 103, and energy loss is reduced. The rear cavity 204 is provided with grooves on both sides of the ridge 202, the front cavity 203 is of a planar structure and only includes the ridge 202, the processed front cavity 203 and the rear cavity 204 are relatively spliced and fixed by screwing screws, and the grooves form the input waveguide cavity 201, that is, the inner cavity described in embodiment 1.

Similar to the input ridge waveguide 2, an output waveguide cavity 301 is arranged in the output ridge waveguide 3, and the input waveguide cavity 201, the first waveguide cavity 103 and the output waveguide cavity 301 are connected and communicated in sequence. In this case, the first waveguide cavity 103 is also designed as a non-standard rectangular waveguide cavity with an aspect ratio of (5-10): 1, in order to receive the output signal of the output waveguide cavity 301.

The working principle is as follows: after the whole bare chip testing device is assembled, a power supply feed line is connected to excite the chip bearing PCB board 401, a radio-frequency signal enters the input waveguide cavity 201 from the input port of the input ridge waveguide 2, the transition from low impedance to high impedance is realized by the gradual change section of the input waveguide cavity 201, the radio-frequency signal enters the first waveguide cavity 103 of the clamp body 1, the chip bearing PCB board 401 and a microstrip circuit above the chip bearing PCB board realize impedance transformation matching from high impedance to 50 ohms, and then the radio-frequency signal sequentially passes through the outlet end of the first waveguide cavity 103, the input port of the output ridge waveguide 3 and is finally output from the output port of the output ridge waveguide 3. And taking the tested chip and the space synthesis single card 4 out of the inclined placing groove together for the production of the whole machine product in the next step.

It will be understood by those skilled in the art that the foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

1. A double-ridge waveguide, characterized by: the double-ridge waveguide cavity comprises an outer cavity body and an inner cavity arranged in the outer cavity body, the section of the outer cavity body is an isosceles trapezoid, a pair of ridge edges (202) is symmetrically arranged on the inner wall of the inner cavity, the thickness of each ridge edge (202) is linearly reduced along the direction from the upper bottom end to the lower bottom end of the isosceles trapezoid, the port of the double-ridge waveguide at the upper bottom end of the isosceles trapezoid is a standard waveguide port with the height-to-width ratio of 2:1, and the port of the double-ridge waveguide at the lower bottom end of the isosceles trapezoid is a non-standard rectangular waveguide port with the height-to-width ratio of (5-.

2. The double-ridge waveguide of claim 1, wherein: the ridge (202) has the same length as the double-ridge waveguide.

3. A bare chip testing device, comprising: the clamp comprises a clamp body (1), an input ridge waveguide (2) and an output ridge waveguide (3), wherein the input ridge waveguide (2) and the output ridge waveguide (3) are identical in structure and are symmetrically arranged with the central axis of the clamp body (1), the input ridge waveguide (2) and the output ridge waveguide (3) adopt the double-ridge waveguide of claim 1 or 2, the input ridge waveguide (2) is connected with an inlet end of the clamp body (1) at the lower bottom end of an isosceles trapezoid, and the output ridge waveguide (3) is connected with an outlet end of the clamp body (1) at the lower bottom end of the isosceles trapezoid.

4. The die testing apparatus of claim 3, wherein: the input ridge waveguide (2) comprises a front cavity (203) and a rear cavity (204) which are formed by split machining, the front cavity (203) and the rear cavity (204) are spliced to form an inner cavity, and the pair of ridge edges (202) are respectively arranged on the opposite surfaces of the front cavity (203) and the rear cavity (204).

5. The die testing apparatus of claim 4, wherein: the pair of ridges (202) are respectively arranged on the central axes of the opposite surfaces of the front cavity (203) and the rear cavity (204).

6. The die testing apparatus of claim 5, wherein: the clamp body (1) comprises a waveguide upper cavity (101) and a waveguide lower cavity (102) which are connected, and the waveguide upper cavity (101) and the waveguide lower cavity (102) are spliced to form a first waveguide cavity (103);

a space synthesis single card (4) is movably arranged on the upper end face of the waveguide lower cavity (102), and the space synthesis single card (4) is used for bearing a chip.

7. The die testing apparatus of claim 6, wherein: the space synthesis single card (4) comprises a chip bearing PCB (401) and a chip fixing caliper (402), wherein the chip bearing PCB (401) is fixedly connected to the chip fixing caliper (402), and the chip fixing caliper (402) is used for fixing a chip;

and a placing groove matched with the chip fixing caliper (402) in shape is arranged on the upper end surface of the waveguide lower cavity (102).

8. The die testing apparatus of claim 6, wherein: the first waveguide cavity (103) is a non-standard rectangular waveguide cavity with the height-width ratio of (5-10): 1.

9. The die testing apparatus of claim 7, wherein: the waveguide cavity comprises a waveguide upper cavity body (101) and is characterized by further comprising an upper cavity shielding cover (104), wherein a first through hole matched with the upper cavity shielding cover (104) in shape is formed in the waveguide upper cavity body; and

the lower cavity shielding cover (105), a second through hole matched with the lower cavity shielding cover (105) is formed in the waveguide lower cavity (102), and the upper end of the lower cavity shielding cover (105) is abutted to the lower end of the chip fixing caliper (402).

10. The die testing apparatus of claim 8, wherein: an input waveguide cavity (201) is arranged in the input ridge waveguide (2), an output waveguide cavity (301) is arranged in the output ridge waveguide (3), and the input waveguide cavity (201), the first waveguide cavity (103) and the output waveguide cavity (301) are sequentially connected and communicated.