CN210110767U

CN210110767U - Semiconductor device with a plurality of transistors

Info

Publication number: CN210110767U
Application number: CN201921403319.3U
Authority: CN
Inventors: 刘志拯
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-08-27
Filing date: 2019-08-27
Publication date: 2020-02-21
Anticipated expiration: 2029-08-27

Abstract

The utility model relates to the technical field of semiconductors, and provides a semiconductor device which can comprise a substrate, a metal grid, a polysilicon grid and an insulating layer; a grid groove is arranged on the substrate; the metal grid is filled in the grid groove, the height of the metal grid is smaller than the depth of the grid groove, and a bulge is arranged on one side of the metal grid close to the opening direction of the grid groove; the polycrystalline silicon grid electrode is filled in the grid electrode groove, the polycrystalline silicon grid electrode is arranged between the protrusion and the inner wall of the grid electrode groove, and the polycrystalline silicon grid electrode does not protrude out of the grid electrode groove; the insulating layer is arranged on one side of the polysilicon grid electrode, which is far away from the metal grid electrode, and the insulating layer, the metal grid electrode and the polysilicon grid electrode completely fill the grid electrode groove. The grid has lower resistance, and simultaneously, the leakage current of the overlapping area of the grid and the source and the drain is reduced, so that the performance of the semiconductor device is improved.

Description

Semiconductor device with a plurality of transistors

Technical Field

The utility model relates to the field of semiconductor technology, especially, relate to a semiconductor device.

Background

Dynamic Random Access Memory (DRAM) is a well-known semiconductor Memory device, and is widely used in various electronic devices.

The word line of the existing dynamic random access memory is mostly formed by using a metal material, that is, the Gate of the storage transistor is mostly a metal Gate, and compared with a polysilicon Gate, the metal Gate has a low resistance characteristic and has a good control capability for a channel switch, however, when a channel is in an off state, the metal Gate causes a large Leakage current (such as Gate Induced Drain Leakage current (GIDL) and Gate Induced Drain Leakage) in an overlapping region of the Gate, a source and a Drain, which may cause a charge Leakage of a storage capacitor, and even cause a data access error of the DRAM.

Therefore, it is necessary to design a new semiconductor device.

The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art known to a person of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome above-mentioned prior art semiconductor device when the passageway is in the closed condition, metal grid can cause grid and source electrode, drain electrode overlap region's leakage current, can influence memory cell's efficiency and reliability, cause DRAM's data access mistake scheduling problem not enough even, provide one kind, can compatible metal grid and polysilicon grid's advantage, under the circumstances that the assurance grid has low resistance value, can also reduce grid and source electrode, drain electrode overlap region's leakage current, with the semiconductor device who improves device efficiency and reliability.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

According to an aspect of the present invention, a semiconductor device includes:

the semiconductor device comprises a substrate, a gate electrode and a gate electrode, wherein a grid electrode groove is formed in the substrate;

the metal grid electrode is filled in the grid electrode groove, the height of the metal grid electrode is smaller than the depth of the grid electrode groove, and a bulge is arranged on one side of the metal grid electrode close to the opening direction of the grid electrode groove;

the polycrystalline silicon grid is filled in the grid groove, the polycrystalline silicon grid is arranged between the protrusion and the inner wall of the grid groove, and the polycrystalline silicon grid does not protrude out of the grid groove;

and the insulating layer is arranged on one side of the polycrystalline silicon grid electrode, which is far away from the metal grid electrode, and completely fills the grid groove with the metal grid electrode and the polycrystalline silicon grid electrode.

In an exemplary embodiment of the present disclosure, the semiconductor device further includes:

and the gate dielectric layer is arranged on the inner wall of the gate groove, and the metal gate, the polysilicon gate and the insulating layer are in contact with the gate dielectric layer.

In an exemplary embodiment of the present disclosure, the width of the polysilicon gate disposed on both sides of the protrusion is 1/2-1/4 of the width of the gate trench where the protrusion is located.

In an exemplary embodiment of the present disclosure, the polysilicon gate completely covers the protrusion.

In an exemplary embodiment of the present disclosure, the polysilicon gate is disposed between the protrusion and the inner wall of the gate trench, and the protrusion penetrates through the polysilicon gate and does not protrude from the polysilicon gate.

According to an aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including:

providing a substrate, and forming a grid groove on the substrate;

forming a metal grid with the height smaller than the depth of the grid groove in the grid groove, wherein a bulge is arranged on one side of the metal grid close to the opening direction of the grid groove;

forming a polysilicon gate between the protrusion and the inner wall of the gate trench, wherein the polysilicon gate does not protrude from the gate trench;

and forming an insulating layer on one side of the polysilicon gate, which is far away from the metal gate, wherein the insulating layer, the metal gate and the polysilicon gate completely fill the gate groove.

In one exemplary embodiment of the present disclosure, forming a gate trench on a substrate includes:

completing doping on one side of the substrate, and dividing the substrate into a doped region and a non-doped region;

and a plurality of gate trenches are formed along the direction from the doped region to the non-doped region, and the opening direction of each gate trench faces to the doped region.

In an exemplary embodiment of the present disclosure, forming a metal gate having a height smaller than a depth of the gate trench in the gate trench, a side of the metal gate near an opening direction of the gate trench having a protrusion, includes:

filling a metal grid in the grid groove, wherein the height of the metal grid is smaller than that of the grid groove, and one side of the metal grid close to the opening direction of the grid groove is a plane;

and forming a bulge on one side of the metal gate close to the opening direction of the gate groove by dry etching or wet etching.

In an exemplary embodiment of the present disclosure, forming a protrusion on a side of the metal gate close to the gate trench opening direction by dry etching or wet etching includes:

depositing a sacrificial layer on one side of the metal grid close to the opening direction of the grid groove, wherein the sacrificial layer is of an annular structure, and the peripheral surface of the sacrificial layer is completely attached to the inner wall of the grid groove;

depositing a polysilicon barrier layer in an inner space formed by the inner peripheral surface of the sacrificial layer;

removing the sacrificial layer, and etching on the metal gate by taking the polycrystalline silicon barrier layer as an isolation layer to form a protrusion;

and removing the polysilicon barrier layer.

In an exemplary embodiment of the present disclosure, before forming a metal gate not protruding from a gate trench in the gate trench, the method further includes:

and forming a gate dielectric layer on the inner surface of the gate groove.

In an exemplary embodiment of the present disclosure, forming a polysilicon gate between the protrusion and an inner wall of the gate trench, the polysilicon gate not protruding from the gate trench, includes:

and forming a polysilicon grid between the protrusion and the inner wall of the grid groove, wherein the polysilicon grid completely covers the protrusion.

and forming a polysilicon gate between the protrusion and the inner wall of the gate groove, wherein the protrusion penetrates through the polysilicon gate and does not protrude out of the polysilicon gate.

According to the above technical scheme, the utility model discloses possess at least one in following advantage and the positive effect:

the utility model discloses a semiconductor device, be provided with the grid slot on the substrate, at first pack the metal grid in the grid slot, the metal grid does not bulge in the grid slot, and has the arch on one side that the metal grid is close to the grid slot opening direction, then pack between the arch and the inner wall of grid slot and have the polycrystalline silicon grid, is provided with the insulating layer on one side that the polycrystalline silicon grid keeps away from the metal grid, and the insulating layer is filled the grid slot completely with metal grid, polycrystalline silicon grid; compared with the prior art, at first, the utility model discloses at first through form the polycrystalline silicon grid on the metal gate, improved compound grid (metal gate and polycrystalline silicon grid) and source electrode, drain electrode overlap region's electric field distribution, the advantage that can compatible metal gate and polycrystalline silicon grid, under the circumstances that the assurance grid has low resistance value, can also reduce grid and source electrode, drain electrode overlap region's the induced drain leakage current of grid. Secondly, the utility model discloses in be close to at the metal gate one side of grid slot opening direction has the arch, then it has the polycrystalline silicon grid to fill between the inner wall of arch and grid slot, the resistance of metal gate is less than to polycrystalline silicon resistance, be provided with the arch, and set up the polycrystalline silicon grid around the arch, on the one hand, can guarantee that the content of the metal gate of transistor gate is enough, the transistor gate has lower resistance promptly, on the other hand has reduced transistor gate and source electrode, drain electrode overlapping region's bars induced drain leakage current, on the other hand again, also can reduce the parasitic resistance and the parasitic capacitance of metal gate, in order to improve semiconductor device's performance.

Drawings

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic structural view of a semiconductor device in the related art;

fig. 2 is a schematic structural diagram of a semiconductor device in an example embodiment of the invention;

FIG. 3 is a flow chart of a method of manufacturing a semiconductor of the present invention;

FIG. 4 is a schematic diagram of a metal gate structure formed in the semiconductor manufacturing method of the present invention;

fig. 5 is a schematic structural diagram of the present invention forming a sacrificial layer and polysilicon on a metal gate;

FIG. 6 is a schematic structural diagram of the present invention with the sacrificial layer removed by etching;

fig. 7 is a schematic structural view of the present invention after forming a protrusion on a metal gate;

fig. 8 is a schematic diagram of the formation of a polysilicon gate on a metal gate according to the present invention;

fig. 9 is a schematic structural diagram of a semiconductor device according to another exemplary embodiment of the present invention.

The reference numerals of the main elements in the figures are explained as follows:

1. a substrate; 11. a source electrode; 12. a drain electrode; 2. a metal gate electrode; 21. a protrusion;

3. a polysilicon gate; 4. an insulating layer; 5. a gate dielectric layer; 6. a polysilicon barrier layer;

7. a sacrificial layer; 8. a gate trench; A. an overlap region.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

In the related art, a Dynamic Random Access Memory (DRAM) is composed of a plurality of repetitive memory cells (cells), each of which is mainly composed of a transistor and a capacitor operated by the transistor, and the memory cells are arranged in an array. In order to increase the integration of Dynamic Random Access Memory (DRAM), increase the operation speed of devices, and meet the demand of consumers for miniaturized electronic devices, the design of the channel region length of the transistor in DRAM is continuously shortened, but the transistor will generate serious short channel effect (short channel effect) and on-current (on-current) decrease. One known solution is to change the structure of a Transistor in the horizontal direction in a Dynamic Random Access Memory (DRAM) to the structure of a Buried Channel Array Transistor (BCAT) in the vertical direction, which is the structure of a Dynamic Random Access Memory (DRAM) having a Buried Channel Array Transistor (BCAT).

Referring to fig. 1, a semiconductor device in the related art includes a semiconductor substrate 1, a metal Gate 2 and an insulating layer 4 covering the metal Gate 2, where the insulating layer 4 is disposed in a Gate trench 8 of the substrate 1 and insulated and isolated from the semiconductor substrate 1 by a Gate dielectric layer 5, and a source 11 and a Drain 12 are formed in the semiconductor substrate 1 on both sides of the Gate, respectively, but when a channel is in an off state, the metal Gate 2 may cause a large Leakage current (e.g., Gate Induced Drain Leakage current, GIDL, Gate Induced Drain Leakage) in an overlapping region a of the Gate and the source 11 and the Drain 12, which may cause charge Leakage of a storage capacitor, and even cause data access errors of a DRAM.

In view of the above disadvantages, the present invention first provides a semiconductor device, which may include a substrate 1, a metal gate 2, a polysilicon gate 3, an insulating layer 4, a source electrode 11, and a drain electrode 12, as shown in fig. 2; a grid groove 8 is arranged on the substrate 1; the metal grid 2 is filled in the grid groove 8, the height of the metal grid 2 is smaller than the depth of the grid groove 8, and a bulge 21 is arranged on one side of the metal grid 2 close to the opening direction of the grid groove 8; the polycrystalline silicon grid 3 is filled in the grid groove 8, the polycrystalline silicon grid 3 is arranged between the metal grid bulge 21 and the inner wall of the grid groove 8, and the polycrystalline silicon grid does not protrude out of the grid groove 8; the insulating layer 4 is disposed on a side of the polysilicon gate 3 away from the metal gate 2, and completely fills the gate trench 8 with the metal gate 2 and the polysilicon gate 3.

Compared with the prior art, at first, the utility model discloses at first through form polycrystalline silicon grid 3 on metal gate 2, improved compound grid (metal gate 2 and polycrystalline silicon grid 3) and source electrode 11, the electric field distribution of drain electrode 12 overlap region A, can compatible metal gate 2 and polycrystalline silicon grid 3's advantage, under the circumstances that guarantees that transistor gate has low resistance value, can also reduce grid and source electrode 11, the grid of drain electrode 12's overlap region A's the induced drain leakage current of grid. Secondly, in the utility model, the metal grid 2 is close to one side of 8 opening directions of grid groove has the arch 21, then it has polycrystalline silicon grid 3 to fill between the inner wall of arch 21 and grid groove 8, and the resistance of metal grid 2 is less than the resistance to polycrystalline silicon grid 3, is provided with the arch 21, and sets up polycrystalline silicon grid 3 around arch 21, on the one hand, can guarantee that the content of the metal grid 2 of transistor grid is enough, and the transistor grid has lower resistance promptly; on the other hand, the gate-induced drain leakage current of the overlap region a of the transistor gate and the source and drain

electrodes

11 and 12 is reduced, and on the other hand, the parasitic resistance and parasitic capacitance of the metal gate 2 can also be reduced to improve the performance of the semiconductor device.

The substrate 1 may be a rectangular parallelepiped structure, and the substrate 1 may be silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge), as long as it is a substrate capable of carrying constituent elements of a semiconductor integrated circuit, and is not particularly limited in this exemplary embodiment.

The substrate 1 may include a doped region and a non-doped region, the thickness of the doped region is less than that of the non-doped region, the doped region may be N + doped, a plurality of gate trenches 8 are disposed along the direction from the doped region to the non-doped region, and the number of the gate trenches 8 may be two, or three, four, or more. The shape of the gate trench 8 may be a rounded U shape, a right-angled U shape, or a trapezoid with a wide top and a narrow bottom, the gate trench 8 penetrates through the doped region, and since the electrical characteristics of the Buried Channel Array Transistor (BCAT) may vary according to the depth from the upper surface of the semiconductor substrate 1 to the bottom surface of the buried gate thereof, the depth of the gate trench 8 may be adjusted to achieve the desired electrical characteristics of the Buried Channel Array Transistor (BCAT), thereby improving the electrical performance and reliability of the finally formed semiconductor device.

In the present exemplary embodiment, the number of gate trenches 8 is two, and two gate trenches 8 are arranged side by side while forming a source electrode 11 and a drain electrode 12 in the doped region of the substrate 1.

The gate dielectric layer 5 may be disposed in the gate trench 8 of the substrate 1, the gate dielectric layer 5 is disposed on the inner surface of the gate trench 8, the gate dielectric layer 5 may be silicon dioxide, or may be other materials of high K dielectric (dielectric constant K is greater than 7), for example, Ta2O5, TiO2, TiN, Al2O3, Pr2O3, La2O3, LaAlO3, HfO2, ZrO2, or metal oxides of other components, and the like, which is not specifically limited herein.

A metal barrier layer can be formed on the surface of the gate dielectric layer 5, so that the ion diffusion of the metal gate 2 can be prevented, the gate dielectric layer 5 is prevented from being polluted, and the performance of the device is improved.

The metal grid 2 is arranged in the grid groove 8, the height of the metal grid 2 is smaller than the depth of the grid groove 8, a protrusion 21 is arranged at the position, close to the opening direction of the grid groove 8, of the metal grid 2, the protrusion 21 can be in a cuboid shape, the protrusion 21 is not in contact with the inner wall of the grid groove 8, and other parts of the metal grid 2 are in contact with the grid dielectric layer 5 arranged on the inner surface of the grid groove 8. The material of the metal gate 2 may be metal aluminum, metal titanium, metal tungsten, or the like.

The polysilicon gate 3 is disposed between the protrusion 21 of the metal gate 2 and the inner wall of the gate trench 8 and, in one example embodiment, referring to fig. 2, the protrusion 21 penetrates the polysilicon gate 3 but does not protrude from the polysilicon gate 3, i.e., the top surface of the polysilicon gate 3 is lower than the upper surface of the substrate 1, and the upper surface of the substrate 1 is the surface of the doped region on the side away from the undoped region, i.e., the metal gate 2 and the polysilicon gate 3 do not completely fill the gate trench 8, and in the direction parallel to the opening direction of the gate trench 8, the upper surface of the polysilicon gate 3 and the upper surface of the protrusion 21 are located on the same plane, the gate-induced drain leakage current of the overlapping region A of the transistor gate and the source electrode 11 and the drain electrode 12 can be effectively reduced while the smaller resistance of the transistor gate (including the metal gate 2 and the polysilicon gate 3) can be ensured.

In another example embodiment, referring to fig. 9, the polysilicon gate 3 completely covers the protrusion 21 of the metal gate 2, and in this embodiment, the resistance of the transistor gate (including the metal gate 2 and the polysilicon gate 3) may be slightly increased, but the gate induced drain leakage current may be further reduced.

The width of the polysilicon gate 3 disposed on both sides of the protrusion 21 is 1/2-1/4 of the width of the gate trench 8 where the protrusion 21 is located, and the height of the protrusion 21 in the opening direction of the gate trench 8 is about 1/4-1/3 of the total height of the metal gate 2.

Further, the present invention also provides a method for manufacturing a semiconductor device, which, as shown in fig. 3, may include the following steps:

step S110, providing a substrate 1, and forming a gate trench 8 on the substrate 1.

Step S120, forming a metal gate 2 with a height smaller than the depth of the gate trench 8 in the gate trench 8, where a protrusion 21 is formed on one side of the metal gate 2 close to the opening direction of the gate trench 8.

In step S130, a polysilicon gate 3 is formed between the protrusion 21 and the inner wall of the gate trench 8, and the polysilicon gate 3 does not protrude from the gate trench 8.

Step S140, forming an insulating layer 4 on a side of the polysilicon gate 3 away from the metal gate 2, wherein the insulating layer 4, the metal gate 2 and the polysilicon gate 3 completely fill the gate trench 8.

Compared with the prior art, firstly, the utility model discloses at first through form polycrystalline silicon grid 3 on metal gate 2, improved transistor grid and source 11, drain electrode 12's overlap area A's electric field distribution, can compatible metal gate 2 and polycrystalline silicon grid 3's advantage, under the circumstances that guarantees transistor grid and have low resistance value, can also reduce grid and source 11, drain electrode 12's overlap area A's the grid induced drain leakage current; secondly, the utility model discloses in metal grid 2 is close to one side of 8 opening directions of grid slot has protruding 21, then it has polycrystalline silicon grid 3 to fill between the inner wall of protruding 21 and grid slot 8, and the resistance of metal grid 2 is less than the resistance to polycrystalline silicon grid 3, is provided with protruding 21 to set up polycrystalline silicon grid 3 around protruding 21, on the one hand, can guarantee that the content of metal grid 2 at the grid is enough, and the transistor grid has lower resistance promptly; on the other hand, the gate-induced drain leakage current of the overlap region a of the transistor gate and the source and drain electrodes 11 and 12 is reduced, and on the other hand, the parasitic resistance and parasitic capacitance of the metal gate 2 can also be reduced to improve the performance of the semiconductor device.

The above steps are described in detail below.

In step S110, a substrate is provided, and a gate trench 8 is formed on the substrate 1.

The substrate 1 may be a rectangular parallelepiped structure, and the substrate 1 may be a silicon substrate, a silicon-on-insulator (SOI), a bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium on insulator, as long as the substrate can carry the components of the semiconductor integrated circuit device, which is not limited in this exemplary embodiment.

Referring to fig. 4, the substrate 1 may include a doped region having a thickness less than that of an undoped region and an undoped region, which may be N + doped. A plurality of gate trenches 8 are provided in a direction from the doped region to the undoped region, and the number of gate trenches 8 may be two or three, four or more. The shape of the gate trench 8 may be a rounded U shape, a right-angled U shape, or a trapezoid with a wide top and a narrow bottom, the gate trench 8 penetrates through the doped region, and since the electrical characteristics of the Buried Channel Array Transistor (BCAT) may vary according to the depth from the upper surface of the semiconductor substrate 1 to the bottom surface of the buried gate thereof, the depth of the gate trench 8 may be adjusted to achieve the desired electrical characteristics of the Buried Channel Array Transistor (BCAT), thereby improving the electrical performance and reliability of the finally formed semiconductor device.

Before forming the gate trench 8 on the substrate 1, an active region is formed on the substrate 1, and a Shallow Trench Isolation (STI) is included, and the gate trench 8 is formed in the active region.

In the present exemplary embodiment, the number of gate trenches 8 is two, two gate trenches 8 are arranged side by side, while the doped regions of the substrate 1 form the source 11 and the drain 12.

In step S120, a metal gate 2 having a height smaller than the depth of the gate trench 8 is formed in the gate trench 8, and a protrusion 21 is formed on one side of the metal gate 2 close to the opening direction of the gate trench 8.

First, referring to fig. 4, the gate trench 8 is filled with the metal gate 2, the height of the metal gate 2 is smaller than the depth of the gate trench 8, and one side of the metal gate 2 close to the opening direction of the gate trench 8 is a plane.

Then, referring to fig. 5, a sacrificial layer 7 is deposited on the metal gate 2 on the side close to the opening direction of the gate trench 8, the sacrificial layer 7 has an annular structure, the outer circumferential surface of the sacrificial layer 7 completely adheres to the inner wall of the gate trench 8, and a polysilicon barrier layer 6 is deposited in the inner space formed by the inner circumferential surface of the sacrificial layer 7.

Next, referring to fig. 6 and 7, the sacrificial layer 7 may be removed by etching, and a protrusion 21 is formed on the metal gate 2 by etching using the polysilicon barrier layer 6 as an isolation layer; the polysilicon is removed, and the height of the protrusion 21 in the opening direction of the gate trench 8 is about 1/4-1/3 of the total height of the metal gate 2.

The metal grid 2 is arranged in the grid groove 8, the height of the metal grid 2 is smaller than the depth of the grid groove 8, a protrusion 21 is arranged at the position, close to the opening direction of the grid groove 8, of the metal grid 2, the shape of the protrusion 21 can be a cuboid shape, and other prism structures can be adopted, such as a pentagonal prism, the protrusion 21 is not in contact with the inner wall of the grid groove 8, and other parts of the metal grid 2 are in contact with the grid dielectric layer 5 arranged on the inner surface of the grid groove 8.

The polysilicon gate 3 is disposed between the protrusion 21 of the metal gate 2 and the inner wall of the gate trench 8, in an exemplary embodiment, referring to fig. 2, the protrusion 21 penetrates through the polysilicon gate 3 but does not protrude from the polysilicon gate 3, that is, the top surface of the polysilicon gate 3 is lower than the upper surface of the substrate 1, the upper surface of the substrate 1 is the surface of the doped region on the side away from the undoped region, that is, the metal gate 2 and the polysilicon gate 3 do not completely fill the gate trench 8, and the upper surface of the polysilicon gate 3 and the upper surface of the protrusion 2 are located on the same plane in the opening direction parallel to the gate trench 8, so that the gate induced drain leakage current of the overlapping region a between the gate and the source 11 and the drain 12 can be effectively reduced while the transistor gate has a smaller resistance.

In another example embodiment, referring to fig. 8, the polysilicon gate 3 completely covers the protrusion 21 of the metal gate 2. In this embodiment, the resistance of the transistor gate (including the metal gate 2 and the polysilicon gate 3) will increase slightly, but the gate induced drain leakage current will decrease further. The resistance of the metal gate 2 is smaller than the resistance of the polysilicon gate 3, the protrusion 21 is arranged, and the polysilicon gate 3 is arranged around the protrusion 21, so that on one hand, under the condition that the content of the metal gate 2 of the transistor gate is enough, namely the gate has lower resistance, the gate induced drain leakage current of the overlap area A of the gate and the source electrode 11 and the drain electrode 12 is reduced, on the other hand, the parasitic resistance and parasitic capacitance of the metal gate 2 can also be reduced, and the performance of the semiconductor device is improved.

In step S140, an insulating layer 4 is formed on a side of the polysilicon gate 3 away from the metal gate 2, and the insulating layer 4 and the metal gate 2 and the polysilicon gate 3 completely fill the gate trench 8.

Referring to fig. 9, an insulating layer 4 is formed on a side of the polysilicon gate 3 away from the metal gate 2, the insulating layer 4, the metal gate 2 and the polysilicon gate 3 completely fill the gate trench 8, and the material of the insulating layer 4 may be silicon nitride, or may be other insulating nitride or oxide, which is not limited herein.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, and the features discussed in connection with the embodiments are interchangeable, if possible. In the description above, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high", "low", "top", "bottom", "front", "back", "left", "right", etc., are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The present invention is capable of other embodiments and of being practiced and carried out in a variety of ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present invention. The embodiments set forth herein explain the best modes known for practicing the invention and will enable others skilled in the art to utilize the invention.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device according to claim 1, further comprising:

3. The semiconductor device according to claim 1, wherein the width of the polysilicon gate disposed on both sides of the protrusion is 1/2-1/4 of the width of the gate trench where the protrusion is located.

4. The semiconductor device of claim 1, wherein the polysilicon gate completely wraps the bump.

5. The semiconductor device of claim 1, wherein the polysilicon gate is disposed between the protrusion and the inner wall of the gate trench, and the protrusion penetrates the polysilicon gate and does not protrude from the polysilicon gate.