CN210073834U - Integrated circuit photoetching structure and integrated circuit - Google Patents
Integrated circuit photoetching structure and integrated circuit Download PDFInfo
- Publication number
- CN210073834U CN210073834U CN201921169734.7U CN201921169734U CN210073834U CN 210073834 U CN210073834 U CN 210073834U CN 201921169734 U CN201921169734 U CN 201921169734U CN 210073834 U CN210073834 U CN 210073834U
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- conductor
- shielding
- mask
- photoetching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001259 photo etching Methods 0.000 title claims abstract description 78
- 239000004020 conductor Substances 0.000 claims abstract description 64
- 238000000206 photolithography Methods 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims 4
- 238000000034 method Methods 0.000 abstract description 29
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000002360 preparation method Methods 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 10
- 230000003287 optical effect Effects 0.000 abstract description 10
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012938 design process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Images
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses an integrated circuit photoetching structure, which comprises a first conductor and a second conductor, wherein the first conductor and the second conductor are both formed by photoetching a preset layout; the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding pattern comprises at least one shielding finger extending along a preset direction. The corners in the layout are distorted due to the optical proximity effect in the photoetching process, and the distortion has strong randomness due to the influence of random disturbance in the preparation process, so that the parasitic capacitance values of the photoetching structure of the integrated circuit are different. The integrated circuit photoetching structure can better capture the process random disturbance in the integrated circuit production process and can be used for generating the identification information of the integrated circuit; the manufacturing cost of the photoetching structure of the integrated circuit is low. The utility model also provides a preparation method and an integrated circuit, have above-mentioned beneficial effect equally.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to an integrated circuit photoetching structure and an integrated circuit.
Background
At present, during the design and production process of an integrated circuit, a layout insensitive to process parameters is usually required to be designed so as to improve the robustness of the design and ensure the yield. However, in the present stage, when the integrated circuit needs to identify its own features or implement functions such as physical unclonable, it is generally necessary to set its own identification information in the integrated circuit.
However, in the prior art, the setting of the identification information of the integrated circuit is usually realized through complicated circuits and devices, so that a person skilled in the art urgently needs to solve the problem how to simply set the identification information in the integrated circuit.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an integrated circuit photoetching structure which can simply and effectively provide the identification information of the integrated circuit; the utility model also provides an integrated circuit, the simple effectual identification information who provides integrated circuit.
In order to solve the above technical problem, the present invention provides an integrated circuit photo-etching structure, which includes a first conductor and a second conductor distributed along a horizontal direction and isolated from each other, wherein the first conductor and the second conductor are both formed by photo-etching a preset layout;
the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding pattern comprises at least one shielding finger extending along a preset direction.
Optionally, the first mask pattern includes a plurality of mask fingers, and the length values of the mask fingers are all the same.
Optionally, a gap is formed between the first shielding pattern and the second shielding pattern, and the width values of any position of the gap are the same.
Optionally, the length value of the shielding finger is larger than the width value of the gap.
Optionally, the second shielding pattern annularly surrounds the first shielding pattern, the first shielding pattern includes a shielding block and at least two shielding fingers extending in different directions, and the shielding fingers and the shielding block are in contact with each other.
Optionally, the first shielding pattern includes four shielding fingers, and the first shielding pattern is cross-shaped.
Optionally, the first shielding pattern includes a shielding block and at least two shielding fingers extending along the same direction, and the shielding fingers and the shielding block are in contact with each other.
Optionally, the second shielding pattern and the first shielding pattern form an interdigital pattern.
The utility model also provides an integrated circuit, include as above-mentioned arbitrary integrated circuit photoetching structure.
The utility model provides an integrated circuit photoetching structure, which comprises a first conductor and a second conductor which are distributed along the horizontal direction and are mutually isolated, wherein the first conductor and the second conductor are both formed by photoetching of a preset layout; the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding pattern comprises at least one shielding finger extending along a preset direction. Because the first conductor and the second conductor which form the integrated circuit photoetching structure are both formed by photoetching processes, corners in a layout are distorted due to optical proximity effect in the photoetching processes. The first shielding graph is provided with shielding fingers extending along the preset direction, so that the preset layout comprising the first shielding graph and the second shielding graph comprises corners. And the shape of the integrated circuit photoetching structure obtained by photoetching the preset layout can be distorted. The distortion has strong randomness due to the influence of random disturbance in the preparation process, so that the shapes of the integrated circuit photoetching structures photoetched by the same preset layout are different, and the parasitic capacitance values of the corresponding integrated circuit photoetching structures are different. The integrated circuit photoetching structure can better capture the process random disturbance in the integrated circuit production process and can be used for generating the identification information of the integrated circuit; the mark information has non-replicability, the manufacturing cost of the integrated circuit photoetching structure is low, and the appearance of the integrated circuit photoetching structure can be used for extracting the pattern of the preparation process characteristic.
The utility model also provides an integrated circuit has above-mentioned beneficial effect equally, no longer gives unnecessary details here.
Drawings
In order to clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an integrated circuit photolithography structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a preset layout according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first specific preset layout provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second specific preset layout provided in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a third specific preset layout provided in an embodiment of the present invention.
In the figure: 1. the circuit comprises a first conductor, 2. a second conductor, 3. a first shielding pattern, 31. a shielding finger, 32. a shielding block and 4. a second shielding pattern.
Detailed Description
The core of the utility model is to provide an integrated circuit photoetching structure. In the prior art, in order to implement the setting of the identification information in the integrated circuit, the setting is usually implemented by complicated circuits and devices, which greatly increases the cost of the integrated circuit and occupies a large space in the integrated circuit.
The utility model provides an integrated circuit photoetching structure, which comprises a first conductor and a second conductor which are distributed along the horizontal direction and are mutually isolated, wherein the first conductor and the second conductor are both formed by photoetching of a preset layout; the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding pattern comprises at least one shielding finger extending along a preset direction. Because the first conductor and the second conductor which form the integrated circuit photoetching structure are both formed by photoetching processes, corners in a layout are distorted due to optical proximity effect in the photoetching processes. The first shielding graph is provided with shielding fingers extending along the preset direction, so that the preset layout comprising the first shielding graph and the second shielding graph comprises corners. And the shape of the integrated circuit photoetching structure obtained by photoetching the preset layout can be distorted. The distortion has strong randomness due to the influence of random disturbance in the preparation process, so that the shapes of the integrated circuit photoetching structures photoetched by the same preset layout are different, and the parasitic capacitance values of the corresponding integrated circuit photoetching structures are different. The integrated circuit photoetching structure can better capture the process random disturbance in the integrated circuit production process and can be used for generating the identification information of the integrated circuit; the mark information has non-replicability, the manufacturing cost of the integrated circuit photoetching structure is low, and the appearance of the integrated circuit photoetching structure can be used for extracting the pattern of the preparation process characteristic.
In order to make the technical field better understand the solution of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings and the detailed description. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of an integrated circuit photolithography structure according to an embodiment of the present invention; fig. 2 is a schematic structural diagram of a preset layout provided in an embodiment of the present invention.
Referring to fig. 1 and fig. 2, in the embodiment of the present invention, the integrated circuit photoetching structure includes a first conductor 1 and a second conductor 2 distributed along a horizontal direction and isolated from each other, and both the first conductor 1 and the second conductor 2 are formed by photoetching a preset layout; the preset layout comprises a first shielding pattern 3 corresponding to the first conductor 1 and a second shielding pattern 4 corresponding to the second conductor 2; the first shading pattern 3 comprises at least one shading finger 31 extending in a predetermined direction.
The first conductor 1 and the second conductor 2 need to be isolated from each other, so that the first conductor 1 and the second conductor 2 can form an integrated circuit photoetching structure. The material of the first conductor 1 and the second conductor 2 may be metal or semiconductor, that is, the integrated circuit photo-etching structure may be made of metal or semiconductor, and the material of the first conductor 1 and the second conductor 2 is determined according to the specific situation, which is not limited in the embodiment of the present invention.
The first conductor 1 and the second conductor 2, i.e., the integrated circuit photoetching structure, are formed by etching through a preset layout by applying a photoetching process. The integrated circuit photoetching structure can be understood as a capacitor, and specific contents related to photoetching process can refer to the prior art, and are not described herein again. When the photoetching process is applied, due to the optical proximity effect and the random disturbance of the process in the preparation process, the appearances of the integrated circuit photoetching structures prepared by the same preset layout are different, so that the parasitic capacitance values of the integrated circuit photoetching structures are different. It should be noted that, in the actual process, the shape of the integrated circuit photo-etching structure prepared by using the preset layout shown in fig. 2 may still have a certain difference from that of fig. 1, and in the embodiment of the present invention, the influence of the optical proximity effect on the shape of the integrated circuit photo-etching structure can be seen by comparing fig. 1 with fig. 2.
Referring to fig. 2, the preset layout includes a first shielding pattern 3 corresponding to the first conductor 1 and a second shielding pattern 4 corresponding to the second conductor 2; the first mask pattern 3 includes at least one mask finger 31 extending in a predetermined direction. It should be noted that, in general, the first mask pattern 3 needs to have a mask block 32 in addition to the mask finger 31, and the mask finger 31 contacts the mask block 32, so that the mask finger 31 extends out of the mask block 32 in the horizontal direction to form at least a convex structure, so as to form a corner in the predetermined layout. It should be noted that, in the embodiment of the present invention, if the first shielding pattern 3 is only a rectangle, it is not generally considered to have the protruding structure of the shielding finger 31.
In the embodiment of the present invention, the specific shape of the second shielding pattern 4 is not specifically limited, and the second shielding pattern 4 may not have the structure of the shielding finger 31, that is, the second shielding pattern 4 may be only a rectangle. It should be noted that, a gap is required between the first shielding pattern 3 and the second shielding pattern 4 to ensure that the first conductor 1 and the second conductor 2 are isolated from each other to form a capacitor. The detailed features of the first shielding pattern 3 and the second shielding pattern 4 will be described in detail in the following embodiments, and will not be described herein.
Preferably, in the embodiment of the present invention, the first shielding pattern 3 may be provided with a plurality of shielding fingers 31, and the length values of the plurality of shielding fingers 31 may be all the same for facilitating the manufacturing of the preset layout and reducing the interference caused by the design.
Preferably, in order to increase the number of corners between the first and second mask patterns 3 and 4, the width of the gap between the first and second mask patterns 3 and 4 may be the same. Due to the existence of the shielding fingers 31, when the width values at any position of the gap between the first shielding pattern 3 and the second shielding pattern 4 are the same, the second shielding pattern 4 can also have the corners corresponding to the shielding fingers 31, so that the number of the corners in the preset layout is effectively increased.
It should be noted that, in general, in order to ensure that the preset layout has an obvious optical proximity effect in the photolithography process, the length value of the shielding finger 31 generally needs to be greater than the width value of the gap, so as to ensure that the first shielding pattern 3 has an obvious protrusion in a horizontal square, so that the preset layout has an obvious optical proximity effect, and at this time, the preset layout is a process-sensitive layout. It should be noted that, in order to ensure that the preset layout can generate different integrated circuit photolithography structures according to the optical proximity effect, the length value of the shielding finger 31 and the width value of the gap need to be greater than the minimum size of the photolithography process used.
The embodiment of the utility model provides an integrated circuit photoetching structure, including first conductor 1 and second conductor 2 that distribute along the horizontal direction and keep apart each other, first conductor 1 and second conductor 2 are all formed through the photoetching of preset territory; the preset layout comprises a first shielding pattern 3 corresponding to the first conductor 1 and a second shielding pattern 4 corresponding to the second conductor 2; the first mask pattern 3 includes at least one mask finger 31 extending in a predetermined direction. Since the first conductor 1 and the second conductor 2 which form the integrated circuit photoetching structure are both formed by photoetching process, the corners in the layout are distorted due to optical proximity effect in the photoetching process. Since the first shielding pattern 3 has the shielding finger 31 extending along the predetermined direction, the predetermined layout including the first shielding pattern 3 and the second shielding pattern 4 includes a corner. And the shape of the integrated circuit photoetching structure obtained by photoetching the preset layout can be distorted. Because the distortion has strong randomness, the shapes of the integrated circuit photoetching structures photoetched by the same preset layout are different, and the parasitic capacitance values of the corresponding integrated circuit photoetching structures are different. The integrated circuit photoetching structure can better capture the process random disturbance in the integrated circuit production process and can be used for generating the identification information of the integrated circuit; the mark information has non-replicability, the manufacturing cost of the integrated circuit photoetching structure is low, and the appearance of the integrated circuit photoetching structure can be used for extracting the pattern of the preparation process characteristic.
The detailed structure of the integrated circuit photolithography structure provided by the present invention will be described in detail in the following embodiments of the present invention.
Referring to fig. 3, fig. 4 and fig. 5, fig. 3 is a schematic structural diagram of a first specific preset layout according to an embodiment of the present invention; fig. 4 is a schematic structural diagram of a second specific preset layout provided in an embodiment of the present invention; fig. 5 is a schematic structural diagram of a third specific preset layout provided in an embodiment of the present invention.
Be different from above-mentioned utility model embodiment, the embodiment of the utility model provides a on the basis of above-mentioned utility model embodiment, further structure to integrated circuit photoetching structure, especially preparation integrated circuit photoetching structure required preset the territory carry out concrete limit. The rest of the contents have been described in detail in the above embodiments, and are not described again here.
The embodiment of the utility model provides an in, provide three kinds altogether and predetermine the structure of territory, these three kinds are predetermine territory structure and all can be guaranteed to predetermine the territory and be the sensitive territory of technology, can prepare out the different integrated circuit photoetching structure of parasitic capacitance value according to this predetermine the territory.
First, referring to fig. 3, the second shielding pattern 4 annularly surrounds the first shielding pattern 3, the first shielding pattern 3 includes a shielding block 32 and at least two shielding fingers 31 extending in different directions, and the shielding fingers 31 and the shielding block 32 contact each other.
The second shielding pattern 4 needs to surround the first shielding pattern 3 in a ring shape, and the first shielding pattern 3 needs to include at least two shielding fingers 31 extending from the shielding block 32 to the second shielding pattern 4 in different directions, and the shielding fingers 31 and the shielding block 32 need to contact each other. Specifically, since the angles in the layout for setting the integrated circuit at the present stage can only be set to 45 °, 90 °, 135 °, and 180 °, the preset layout of the structure is usually in an axisymmetric structure. In order to ensure that the preset layout of the structure can generate sufficient optical proximity effect in the using process, the first shielding pattern 3 is generally in a cross shape, and at this time, the first shielding pattern 3 includes four shielding fingers 31, and one end of each of the four shielding fingers 31 contacts with a shielding block 32 between the four shielding fingers 31 to jointly form the first shielding pattern 3 of the cross-shaped structure. At this time, the first mask pattern 3 and the second mask pattern 4 together form a pattern having a central symmetrical structure.
Secondly, referring to fig. 4, the preset layout of the structure is substantially similar to the preset layout shown in fig. 3, and the first shielding pattern 3 in the preset layout is also cross-shaped, except that in the preset layout structure, the width of the shielding finger 31 in the first shielding pattern 3 is smaller than the length of the side length of the shielding block 32. The shielding block 32 is generally square, and at this time, the shielding fingers 31 protrude from four corners of the shielding block 32, so that compared with fig. 3, more corners are added in a preset layout formed by the first shielding pattern 3 and the second shielding pattern 4 together, so as to increase the influence of random disturbance in the manufacturing process on the shape and appearance of the integrated circuit photoetching structure finally manufactured by the photoetching process.
Thirdly, referring to fig. 5, the first shielding pattern 3 includes a shielding block 32 and at least two shielding fingers 31 extending in the same direction, and the shielding fingers 31 and the shielding block 32 contact each other. The shielding blocks 32 in the first shielding pattern 3 are mainly rectangular, and the shielding fingers 31 are parallel to each other and have a certain distance therebetween, and normally, the shielding fingers 31 are distributed in parallel along the long sides of the shielding blocks 32. Specifically, in order to ensure sufficient corners between the first shielding pattern 3 and the second shielding pattern 4, the second shielding pattern 4 may have a structure similar to the first shielding pattern 3, and also have shielding fingers 31 extending along the same direction, and the first shielding pattern 3 and the second shielding pattern 4 are intersected with each other to form an interdigital pattern, i.e., the second shielding pattern 4 and the first shielding pattern 3 form an interdigital pattern, so that a large number of corners are provided in the predetermined layout.
The embodiment of the utility model provides a specifically provide three kinds of structures of predetermineeing the territory, these three kinds of territory structures of predetermineeing all can guarantee to predetermine the territory for the sensitive territory of technology, can prepare out the different integrated circuit photoetching structure of parasitic capacitance value according to this territory of predetermineeing.
The utility model also provides an integrated circuit, include with the integrated circuit photoetching structure that any above-mentioned utility model embodiment provided, can set up the integrated circuit photoetching structure that a plurality of above-mentioned utility model embodiments provided in integrated circuit under the general condition to make integrated circuit can generate the identification information of a multiple number according to a plurality of above-mentioned integrated circuit photoetching structure. For the rest of the structure of the integrated circuit, reference may be made to the prior art, and further description is omitted here.
Because above-mentioned utility model provides an integrated circuit photoetching structure can be better catch the random disturbance of technology in the integrated circuit production process, make integrated circuit generate random identification information according to the parasitic capacitance value of this integrated circuit photoetching structure, and the cost of preparation is very low, corresponding the embodiment of the utility model provides an integrated circuit can generate random identification information according to the parasitic capacitance value of above-mentioned integrated circuit photoetching structure, and effectively reduce integrated circuit's cost of preparation.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It is right above that the utility model provides an integrated circuit photoetching structure and an integrated circuit have introduced in detail. The principles and embodiments of the present invention have been explained herein using specific examples, and the above descriptions of the embodiments are only used to help understand the method and its core ideas of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.
Claims (9)
1. The integrated circuit photoetching structure is characterized by comprising a first conductor and a second conductor which are distributed along the horizontal direction and are mutually isolated, wherein the first conductor and the second conductor are both formed by photoetching of a preset layout;
the preset layout comprises a first shielding graph corresponding to the first conductor and a second shielding graph corresponding to the second conductor; the first shielding pattern comprises at least one shielding finger extending along a preset direction.
2. The integrated circuit photolithographic structure of claim 1 wherein the first mask pattern comprises a plurality of mask fingers, the mask fingers all having the same length value.
3. The integrated circuit photolithographic structure of claim 2 wherein the first masking pattern and the second masking pattern have a gap therebetween, and the width of the gap is the same at any position.
4. The integrated circuit photolithographic structure of claim 3 wherein the length of the shadow fingers is greater than the width of the gaps.
5. The integrated circuit photolithography structure of any of claims 1 through 4, wherein the second mask pattern annularly surrounds the first mask pattern, the first mask pattern comprises a mask block and at least two mask fingers extending in different directions, and the mask fingers and the mask block are in contact with each other.
6. The integrated circuit photolithographic structure of claim 5, wherein said first mask pattern comprises four of said mask fingers, said first mask pattern being cross-shaped.
7. The integrated circuit photolithographic structure of any of claims 1-4, wherein said first mask pattern comprises a mask block and at least two of said mask fingers extending in the same direction, said mask fingers contacting said mask block.
8. The integrated circuit photolithographic structure of claim 7 wherein said second masking pattern and said first masking pattern form an interdigitated pattern.
9. An integrated circuit comprising an integrated circuit lithographic structure according to any of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921169734.7U CN210073834U (en) | 2019-07-23 | 2019-07-23 | Integrated circuit photoetching structure and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921169734.7U CN210073834U (en) | 2019-07-23 | 2019-07-23 | Integrated circuit photoetching structure and integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210073834U true CN210073834U (en) | 2020-02-14 |
Family
ID=69429573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921169734.7U Active CN210073834U (en) | 2019-07-23 | 2019-07-23 | Integrated circuit photoetching structure and integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210073834U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110277372A (en) * | 2019-07-23 | 2019-09-24 | 南方电网科学研究院有限责任公司 | A kind of IC etching arbor, preparation method and integrated circuit |
-
2019
- 2019-07-23 CN CN201921169734.7U patent/CN210073834U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110277372A (en) * | 2019-07-23 | 2019-09-24 | 南方电网科学研究院有限责任公司 | A kind of IC etching arbor, preparation method and integrated circuit |
| CN110277372B (en) * | 2019-07-23 | 2024-05-31 | 南方电网科学研究院有限责任公司 | Integrated circuit photo-etching structure, preparation method and integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI490758B (en) | Display devices with touch screen | |
| CN210073834U (en) | Integrated circuit photoetching structure and integrated circuit | |
| WO2020001098A1 (en) | Touch panel and touch display device | |
| CN103730337A (en) | Mask for photolithography process and prepared pattern thereof | |
| CN103489839B (en) | Hard mask clearance wall structure and preparation method thereof | |
| US20120219701A1 (en) | Method for fabricating touch sensor structure | |
| CN209821833U (en) | Physical unclonable function circuit and integrated circuit | |
| WO2017117981A1 (en) | Touch-control substrate, manufacturing method thereof and touch-control device | |
| CN110263588B (en) | Physical unclonable function circuit, integrated circuit and preparation method | |
| CN103687282A (en) | Ultra-wide band electromagnetic band-gap structure | |
| CN110277372B (en) | Integrated circuit photo-etching structure, preparation method and integrated circuit | |
| CN204374608U (en) | A kind of mask plate | |
| CN103839769A (en) | Method for forming patterns | |
| CN106227381B (en) | Touch substrate, mask plate and method for manufacturing touch substrate | |
| US20200104012A1 (en) | Touch display panel, method of manufacturing touch display panel, and display apparatus | |
| KR100862870B1 (en) | A semiconductor device and method for manufacturing the same | |
| KR940010236A (en) | Glass mask for semiconductor device and manufacturing method thereof | |
| US20040229129A1 (en) | Reducing charging effects in photolithography reticle manufacturing | |
| CN103440906B (en) | Conducting film and contact panel | |
| CN107425269A (en) | Multifrequency Shared aperture broadband radiation body | |
| KR0122870Y1 (en) | Photomask | |
| KR100307542B1 (en) | Fence structure for wet etch | |
| WO2022267053A1 (en) | Metal mesh, thin film sensor and mask | |
| CN102830594A (en) | Exposed out-of-focus SEM (Scanning Electron Microscope) detection device and detection method thereof | |
| JPH0318024A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |