CN210072387U

CN210072387U - Digital signal processing device

Info

Publication number: CN210072387U
Application number: CN201921220004.5U
Authority: CN
Inventors: 龚建强
Original assignee: Hubei Aidixin Electronic Technology Co Ltd
Current assignee: Hubei Aidixin Electronic Technology Co Ltd
Priority date: 2019-07-29
Filing date: 2019-07-29
Publication date: 2020-02-14
Anticipated expiration: 2029-07-29

Abstract

The utility model relates to a digital signal processing technology field especially relates to a digital signal processing device, including CCD module, leading pre-filtering module, high-speed AD conversion module, programmable gate array module, two port storage module, external storage interface module, processor module, DA conversion module, display module, SDRAM storage module, Flash storage module, JTAC test module, clock circuit module, power module and voltage monitoring reset module, the output of CCD module and the input electric connection of leading pre-filtering module, the output of leading pre-filtering module and the input electric connection of high-speed AD conversion module. The utility model provides a because the influence of various external factors can lead to the image to take place the problem that distortion, quality descend by a wide margin to improve the whole quality of image in gathering the transmission course, furthest protects the quality of image, can not cause the emergence that the image vibrates, phenomenon such as fuzzy.

Description

Digital signal processing device

Technical Field

The utility model relates to a digital signal processing technology field especially relates to a digital signal processing device.

Background

Digital signal processing means that a converter is used to convert an analog state into a digital state, and analog and measurement are performed on a real world continuous signal, that is, a real visible or audible object is converted into a digital signal, such as sound, picture or video, which can be converted into a digital signal through digital signal processing. As a digital signal processing theory application technology, it is involved in many fields. Digital signal processing has played a tremendous role, especially in the fields of communications, graphics, instrumentation, PCs, hearing aids, and automotive electronics.

The image processing technology works by removing noise, enhancing, restoring and encoding the image. After a long period of development, in the process of processing image information, the analog image processing technology can cause image distortion and quality reduction due to the influence of various external factors, so that the problem of the reduction of the image transmission quality can be solved in a mode of transmitting an image signal by combining with a digital signal.

SUMMERY OF THE UTILITY MODEL

Technical problem to be solved

The utility model provides a not enough to prior art, the utility model provides a digital signal processing device has solved because the influence of various external factors can lead to the image to take place the problem that distortion, quality descend by a wide margin to improve the whole quality of image in gathering the transmission course, furthest protects the quality of image, can not cause the emergence that the image vibrates, phenomenon such as fuzzy.

(II) technical scheme

In order to realize the technical problem, the utility model provides a following technical scheme: a digital signal processing device comprises a CCD module, a pre-filtering module, a high-speed A/D conversion module, a programmable gate array module, a double-port storage module, an external storage interface module, a processor module, a D/A conversion module, a display module, an SDRAM storage module, a Flash storage module, a JTAC test module, a clock circuit module, a power supply module and a voltage monitoring reset module, wherein the output end of the CCD module is electrically connected with the input end of the pre-filtering module, the output end of the pre-filtering module is electrically connected with the input end of the high-speed A/D conversion module, the output end of the high-speed A/D conversion module is electrically connected with the input end of the programmable gate array module, the output end of the programmable gate array module is electrically connected with the input end of the double-port storage module, and the output end of the double-port storage module is electrically connected with the input end, the output end of the external storage interface module is electrically connected with the input end of the processor module, the output end of the processor module is electrically connected with the input end of the D/A conversion module, and the output end of the D/A conversion module is electrically connected with the input end of the display module.

Furthermore, the input end of the dual-port storage module is electrically connected with the output end of the external storage interface module, the input end of the external storage interface module is electrically connected with the output end of the processor module, the type of the dual-port storage module adopts IDT70V28 and is configured in CE2 space

Furthermore, the output end and the input end of the SDRAM storage module and the Flash storage module are electrically connected to the output end and the input end of the external storage interface module, respectively, the model of the Flash storage module adopts SST39VF040 and is configured in the CE1 space, and the model of the SDRAM storage module adopts HY57V653220 and is configured in the CE0 space.

Furthermore, the output end and the input end of the JTAC testing module are electrically connected with the output end and the input end of the processor module respectively, the model of the JTAC testing module adopts C6711, and the JTAC testing module is provided with TMS, TDI, TDO, TCK, EMU1 and EMU0 simulation pins.

Furthermore, the output end of the clock circuit module is electrically connected with the input end of the processor module, the output end of the power supply module is electrically connected with the input end of the voltage monitoring reset module, and the output end of the voltage monitoring reset module is electrically connected with the input end of the processor module.

Further, the model of the processor module employs TMS320C 6711B.

(III) advantageous effects

The utility model provides a digital signal processing device possesses following beneficial effect:

1. the utility model discloses a real-time image processing system who comprises high performance processor module 7 and programmable gate array module 4, image acquisition has been realized, real-time data handles and output, utilize JTAC test module 12 interface to carry out online debugging to the system, make the system have fine scalability and expansibility, adopt processor module 7 to strengthen the throughput of system, system's processing speed has been improved, the real-time requirement of work has been guaranteed, the digital signal conversion ability to the image has been improved, protect the quality of image to the maximum extent, can not cause the image to shake, the emergence of phenomenons such as blur.

2. The utility model discloses can avoid the appearance of image distortion phenomenon well, it can guarantee image quality to the at utmost, ensures the true reappearance of image, except can carrying out conventional linear operation work, can also carry out nonlinear processing work, consequently has incomparable flexibility, and the simultaneous processing procedure is simple relatively, and the technical staff only need pass through computer equipment, just can realize truning into the purpose of digital coding format with different information source pictures conveniently.

Drawings

Fig. 1 is a system block diagram of the structure of the present invention.

In the figure: 1. a CCD module; 2. a pre-filtering module; 3. a high-speed A/D conversion module; 4. a programmable gate array module; 5. a dual port storage module; 6. an external storage interface module; 7. a processor module; 8. a D/A conversion module; 9. a display module; 10. an SDRAM storage module; 11. a Flash storage module; 12. a JTAC test module; 13. a clock circuit module; 14. a power supply module; 15. and a voltage monitoring reset module.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, the present invention provides a technical solution: a digital signal processing device comprises a CCD module 1, a pre-filtering module 2, a high-speed A/D conversion module 3, a programmable gate array module 4, a dual-port storage module 5, an external storage interface module 6, a processor module 7, a D/A conversion module 8, a display module 9, an SDRAM storage module 10, a Flash storage module 11, a JTAC test module 12, a clock circuit module 13, a power supply module 14 and a voltage monitoring reset module 15, wherein the output end of the CCD module 1 is electrically connected with the input end of the pre-filtering module 2, an analog image signal output by the CCD module 1 is converted into a 10-bit digital image signal by the high-speed A/D conversion module 3 and is stored in the dual-port storage module under the control of the programmable gate array module 4 for processing by the processor module 7, the output end of the pre-filtering module 2 is electrically connected with the input end of the high-speed A/D conversion module 3, the output end of the high-speed A/D conversion module 3 is electrically connected with the input end of the programmable gate array module 4, the output end of the programmable gate array module 4 is electrically connected with the input end of the double-port storage module 5, the output end of the double-port storage module 5 is electrically connected with the input end of the external storage interface module 6, the processor module 7 accesses the external memory and must pass through the external storage interface module 6, the external storage interface module 6 not only has high data throughput rate, but also has strong interface capability and can be directly interfaced with all types of memories at present, the Flash storage module 11 is a memory which can be erased on site and can retain data after power failure and is used for solidifying programs and retaining the data which needs to be stored after power failure, the double-port storage module 5 is used for storing one frame of image data, the SDRAM storage module 10 has high operation speed and is used for storing real-time operation, the output of external storage interface module 6 and the input electric connection of processor module 7, the output of processor module 7 and the input electric connection of DA conversion module 8, the output of DA conversion module 8 and the input electric connection of display module 9, the utility model discloses the real-time image processing system who comprises high performance processor module 7 and programmable gate array module 4 has realized image acquisition, real-time data processing and output, utilizes JTAC test module 12 interface to carry out online debugging to the system, makes the system have fine scalability and expansibility, adopts processor module 7 to strengthen the throughput of system, has improved system processing speed, has guaranteed the real-time requirement of work, has improved the digital signal conversion ability to the image, and the quality of protection image to the utmost can not cause image vibration, Blurring and the like.

The input end of the dual-port storage module 5 is electrically connected with the output end of the external storage interface module 6, the input end of the external storage interface module 6 is electrically connected with the output end of the processor module 7, the model of the dual-port storage module 5 adopts IDT70V28 and is configured in CE2 space, the output ends and the input ends of the SDRAM storage module 10 and the Flash storage module 11 are respectively electrically connected with the output end and the input end of the external storage interface module 6, the model of the Flash storage module 11 adopts SST39VF040 and is configured in CE1 space, the model of the SDRAM storage module 10 adopts HY57V653220 and is configured in CE0 space, the output end and the input end of the JTAC test module 12 are respectively electrically connected with the output end and the input end of the processor module 7, the model of the JTAC test module 12 adopts C6711, the JTAC test module 12 has TMS, TDI, TDO, TCK, EMU1 and EMU0 simulation pins, the output end of the clock circuit module 13 is electrically connected with the input end of the, the 25MHz clock circuit module 13 generates 150MHz and 100MHz clock signals after ICS501 frequency multiplication, obtains CPU working clock and working clock needed by synchronous interface after output by tristate gate bus buffer 74LVTH125, 6 JTAG simulation pins, TMS, TDI, TDO, TCK, EMU1 and EMU0 of C6711 are connected to a 14-pin double-row plug and can be connected with simulator for system debugging and program downloading, the output end of the power module 14 is electrically connected with the input end of the processor module 7, the processor module 7 needs two voltages, namely CPU core voltage and peripheral I/O interface voltage, the processor module 7 needs two voltages of 3.3V and 1.8V, and the two power supplies are required to meet a certain power-up sequence, the system adopts a mode of powering up the two simultaneously, and adopts chip TPS54316 and TPS54314 to directly generate two voltages of 3.3V and 1.8V respectively according to the power consumption requirement of the system, the power supply circuit can provide 3A power supply current to the maximum extent, the voltage monitoring reset module 15 is realized by TPS3307-33 of TI company, the power supply circuit can monitor three independent voltages of 3.3V/5V/1.8V at the same time, and when one of the three monitored voltages is lower than the threshold value, an effective signal can be output to reset the processor module 7, when the values of the three voltages are higher than the threshold value, the signal is changed into high level, the output end of the power supply module 14 is electrically connected with the input end of the voltage monitoring reset module 15, the output end of the voltage monitoring reset module 15 is electrically connected with the input end of the processor module 7, the model of the processor module 7 adopts TMS320C6711B, the TMS320C6711B is a high-speed floating point DSP chip of TI company, the main frequency is 150MHz, the peak value operation capacity of 900MFLOPS can be achieved to the maximum extent, the TMS320C6711B comprises three parts of a CPU core, an on-chip and an, With the advanced VelociTITM architecture, 8 functional units per clock cycle can operate in parallel.

The working principle is as follows: the CCD module 1 collects the output analog image signal, transmits the analog image signal to the pre-filtering module 2 for filtering processing, converts the analog signal into a digital signal through the high-speed A/D conversion module 3, the digital image signal continuously inputs the data into the dual-port storage module 5 under the control of the programmable gate array module 4, when one frame of image is scanned, the programmable gate array module 4 provides an interrupt flag signal to trigger the processor module 7 to move the data, one frame of image in the dual-port storage module 5 is moved into the SDRAM storage module 10 through the QDMA in the processor module 7, the QDMA checks whether the image data is valid after the data is moved, if so, the processor module 7 is triggered to execute the image processing program, otherwise, the next interrupt is returned, and the processor module 7 finishes processing the frame of image before the next interrupt, the attitude angle information that will reachd is exported for computer PC RS232 mouth and is shown through multichannel buffering serial ports MCBSP, later gets into the interrupt wait state again, waits to interrupt and triggers QDMA once more and carries out data removal and move, the utility model discloses can avoid the appearance of image distortion phenomenon well, it can guarantee image quality to the at utmost, ensures the true reappearance of image, except can carrying out conventional linear operation work, can also carry out nonlinear processing work, consequently has incomparable flexibility, and the simultaneous processing procedure is simple relatively, and the technical staff only needs to pass through computer equipment, just can realize conveniently truning into the purpose of digital coding format with different information source images.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The utility model provides a digital signal processing device, including CCD module (1), pre-filtering module (2), high-speed AD conversion module (3), programmable gate array module (4), two port storage module (5), external storage interface module (6), processor module (7), DA conversion module (8), display module (9), SDRAM storage module (10), Flash storage module (11), JTAC test module (12), clock circuit module (13), power module (14) and voltage monitoring reset module (15), its characterized in that: the output end of the CCD module (1) is electrically connected with the input end of a pre-filtering module (2), the output end of the pre-filtering module (2) is electrically connected with the input end of a high-speed A/D conversion module (3), the output end of the high-speed A/D conversion module (3) is electrically connected with the input end of a programmable gate array module (4), the output end of the programmable gate array module (4) is electrically connected with the input end of a double-port storage module (5), the output end of the double-port storage module (5) is electrically connected with the input end of an external storage interface module (6), the output end of the external storage interface module (6) is electrically connected with the input end of a processor module (7), the output end of the processor module (7) is electrically connected with the input end of a D/A conversion module (8), and the output end of the D/A conversion module (8) is electrically connected with the input end of a display module (9) .

2. A digital signal processing apparatus according to claim 1, wherein: the input of two port storage module (5) and the output electric connection of external storage interface module (6), the input of external storage interface module (6) and the output electric connection of processor module (7), IDT70V28 is adopted to the model of two port storage module (5), and the configuration is in CE2 space.

3. A digital signal processing apparatus according to claim 1, wherein: the SDRAM storage module (10) and the Flash storage module (11) are electrically connected with the output end and the input end of the external storage interface module (6) respectively, the type of the Flash storage module (11) adopts SST39VF040 and is configured in CE1 space, and the type of the SDRAM storage module (10) adopts HY57V653220 and is configured in CE0 space.

4. A digital signal processing apparatus according to claim 1, wherein: the output end and the input end of the JTAC testing module (12) are electrically connected with the output end and the input end of the processor module (7) respectively, the model of the JTAC testing module (12) adopts C6711, and the JTAC testing module (12) is provided with TMS, TDI, TDO, TCK, EMU1 and EMU0 simulation pins.

5. A digital signal processing apparatus according to claim 1, wherein: the output end of the clock circuit module (13) is electrically connected with the input end of the processor module (7), the output end of the power supply module (14) is electrically connected with the input end of the voltage monitoring reset module (15), and the output end of the voltage monitoring reset module (15) is electrically connected with the input end of the processor module (7).

6. A digital signal processing apparatus according to claim 1, wherein: the model of the processor module (7) adopts TMS320C 6711B.