CN213661604U - Low-power consumption image receiving circuit based on WIFI - Google Patents

Abstract

The utility model relates to an image transmission field, the technical scheme who adopts is: a low-power-consumption image receiving circuit based on WIFI comprises a voltage conversion circuit, a signal processing circuit, a storage circuit, a video output circuit and an input power supply reverse connection prevention circuit, wherein the storage circuit and the video output circuit are connected with the signal processing circuit, and the output end of the voltage conversion circuit is connected with the power supply ends of the storage circuit, the signal processing circuit and the video output circuit respectively; the output end of the input power supply reverse connection prevention circuit is connected with the input end of the voltage conversion circuit. The utility model has simple and reliable circuit and small volume, on one hand, the integrated chip is utilized, and the peripheral circuit can be reduced; the safety of the circuit is improved by using an advanced power supply chip, and finally, the problem of digital-analog video signal conversion is solved by using a video converter. The utility model has the advantages of simple circuit, small volume, low power consumption, high integration degree and the like.

Description

Low-power consumption image receiving circuit based on WIFI

Technical Field

The utility model relates to an image transmission field, concretely relates to low-power consumption image receiving circuit based on WIFI.

Background

Image transmission is a process of performing information source and channel processing, and transmitting or storing image information in real time or in time, according to certain requirements. In the prior art, the image transmission mode by using WIFI and the like is relatively mature, and the image transmission circuit based on WIFI has the following defects in practical application: the transmission delay of the mode is relatively large, and the circuit is complex, large in size, high in power consumption and low in integration degree.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a low-power consumption image receiving circuit based on WIFI.

In order to realize the purpose of the utility model, the utility model adopts the technical proposal that: a low-power-consumption image receiving circuit based on WIFI comprises a voltage conversion circuit, a signal processing circuit, a storage circuit, a video output circuit and an input power supply reverse connection prevention circuit, wherein the storage circuit and the video output circuit are connected with the signal processing circuit, and the output end of the voltage conversion circuit is connected with the power supply ends of the storage circuit, the signal processing circuit and the video output circuit respectively; the output end of the input power supply reverse connection prevention circuit is connected with the input end of the voltage conversion circuit.

Preferably, the input power supply reverse connection prevention circuit comprises a resistor R1, a capacitor C1, a field effect transistor Q1, a resistor R424, a resistor R2 and a capacitor C2; one pin of the resistor R1 is respectively connected with one pin of the capacitor C1 and two pins of the field effect transistor Q1; one pin of the field effect transistor Q1 is connected with one pin of a resistor R2 and one pin of a capacitor C2; the three pins of the field effect transistor Q1 are connected with two pins of a resistor R2, two pins of a capacitor C2 and one pin of a resistor R424; two pins of the resistor R1, two pins of the capacitor C1 and two pins of the resistor R424 are all grounded.

Preferably, the voltage conversion circuit comprises a capacitor C228, a capacitor C13, a resistor R13, a capacitor C229, a resistor R420, a capacitor C15, a capacitor C16, a capacitor C17, a resistor R15, a resistor R19, a resistor R16, an inductor L2, an integrated power chip U2, an inductor L7, a resistor R17, a resistor R18, a resistor R26, a capacitor C18, a capacitor C19, a resistor R24, a resistor R23, a resistor R423, and a capacitor C20;

a seventh pin of the integrated power chip U2 is respectively connected with a pin of the capacitor C228, a pin of the capacitor C13, a pin of the resistor R13 and a pin of the resistor R420; the fourth pin of the integrated power chip U2 is respectively connected with two pins of a resistor R13 and one pin of a capacitor C229, and the second pin of the integrated power chip U2 is respectively connected with two pins of a resistor R420 and one pin of a capacitor C15;

a sixth pin of the integrated power chip U2 is connected with a pin of an inductor L2, two pins of the inductor L2 are connected with a pin of a capacitor C16, a pin of a capacitor C17 and a pin of a resistor R15, two pins of a resistor R15 are connected with a pin of a resistor R19, a pin of a resistor R16 and a pin of a resistor R24, and two pins of the resistor R16 are connected with an eighth pin of the integrated power chip U2;

two pins of the resistor R24 are connected with one pin of a resistor R23, and two pins of the resistor R23 are respectively connected with one pin of a resistor R423 and one pin of a capacitor C20; two pins of the resistor R423 are PWM debugging ends;

a first pin of the integrated power chip U2 is connected with a pin of a resistor R17, two pins of the resistor R17 are respectively connected with a pin of a resistor R26 and a pin of a resistor R18, two pins of the resistor R18 are respectively connected with a pin of an inductor L7, a pin of a capacitor C18 and a pin of a capacitor C19, and two pins of the inductor L7 are connected with a third pin of the integrated power chip U2;

the fifth pin of the integrated power chip U2, the two pins of the capacitor C228, the two pins of the capacitor C13, the two pins of the capacitor C229, the two pins of the capacitor C15, the two pins of the capacitor C16, the two pins of the capacitor C17, the two pins of the capacitor C18, the two pins of the capacitor C19, the two pins of the resistor R26 and the two pins of the capacitor C20 are all grounded.

Preferably, the signal processing circuit comprises an integrated chip U1, a capacitor C122, a capacitor C141, a capacitor C139, a capacitor C123, a resistor R165, and an inductor L5;

one pin of the capacitor C122 is connected with the U12 th pin of the integrated chip U1; one pin of the capacitor C141 is connected with the P15 th pin of the integrated chip U1; one pin of the capacitor C139 is connected with the P14 th pin of the integrated chip U1; the D16 th pin of the integrated chip U1 is respectively connected with a pin of the inductor L5 and a pin of the capacitor C123; two pins of the resistor R165 are connected with a B13 pin of the integrated chip U1; two pins of the capacitor C122, two pins of the capacitor C141, two pins of the capacitor C139, a second pin of the capacitor C123, and two pins of the inductor L5 are all grounded.

Preferably, the memory circuit comprises an integrated chip U16, a resistor R12, a resistor R22, a resistor R21, a resistor R406 and a resistor R132;

two pins of the resistor R12 are connected with a first pin of an integrated chip U16; one pin of the resistor R22 is connected with the third pin of the integrated chip U16; two pins of the resistor R21 are connected with one pin of the resistor R406; two pins of the resistor R406 are respectively connected with the seventh pin of the integrated chip U16 and one pin of the resistor R132; the fourth pin of the integrated chip U16 and the ninth pin of the integrated chip U16 are both grounded.

Preferably, the video output circuit comprises an integrated chip U17, a capacitor C238, a resistor R410, a resistor R409, a capacitor C219, a crystal oscillator X2, a capacitor C218, a resistor R411, a resistor R407, a resistor R408, a capacitor C220, a resistor R413, a resistor R412, an inductor LB22, a capacitor C216, a capacitor C217 and a capacitor C221;

one pin of the inductor LB22 is connected with one pin of the capacitor C221 and the fourteenth pin of the integrated chip U17 respectively, and two pins of the inductor LB22 are connected with one pin of the capacitor C216, one pin of the capacitor C217, one pin of the capacitor C220, the second twelve pin of the integrated chip U17 and the twentieth pin of the integrated chip U17 respectively;

one pin of the resistor R411, one pin of the resistor R407 and one pin of the resistor R408 are connected with the output end of the voltage conversion circuit; two pins of the resistor R411 are connected with a nineteenth pin of the integrated chip U17, two pins of the resistor R407 are connected with an eighteenth pin of the integrated chip U17, and two pins of the resistor R408 are connected with a seventeenth pin of the integrated chip U17;

one pin of the capacitor C221 is connected to the fourteenth pin of the ic U17, and one pin of the resistor R412 is connected to one pin of the resistor R413 and the twenty-first pin of the ic U17, respectively; a pin of the resistor R410 is respectively connected with a twenty-sixth pin of the integrated chip U17, a pin of the capacitor C218 and a first pin of the crystal oscillator X2; two pins of the resistor R410 are respectively connected with the twenty-fifth pin of the integrated chip U17 and one pin of the resistor R409; two pins of the resistor R409 are respectively connected with a third pin of the crystal oscillator X2 and a pin of the capacitor C219;

two pins of the capacitor C218, two pins of the capacitor C221, two pins of the resistor R413, two pins of the capacitor C219, two pins of the crystal oscillator X2, and a fourth pin of the crystal oscillator X2 are all grounded.

The beneficial effects of the utility model are concentrated and are embodied in: the utility model has simple and reliable circuit and small volume, on one hand, the integrated chip is utilized, and the peripheral circuit can be reduced; the safety of the circuit is improved by using an advanced power supply chip, and finally, the problem of digital-analog video signal conversion is solved by using a video converter. The utility model has the advantages of simple circuit, small volume, low power consumption, high integration degree and the like.

Drawings

FIG. 1 is a block diagram of the overall circuit of the present invention;

FIG. 2 is a circuit diagram of the power supply reverse connection prevention of the present invention;

FIG. 3 is a voltage conversion circuit diagram of the present invention;

fig. 4 is a circuit diagram of the signal processing circuit of the present invention;

fig. 5 is a circuit diagram of the memory of the present invention;

fig. 6 is a circuit diagram of the interface of the video output of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, a low-power-consumption image receiving circuit based on WIFI includes a voltage conversion circuit, a signal processing circuit, a storage circuit, a video output circuit and an input power supply reverse-connection prevention circuit, wherein the storage circuit and the video output circuit are both connected with the signal processing circuit, and an output end of the voltage conversion circuit is respectively connected with power supply ends of the storage circuit, the signal processing circuit and the video output circuit; the output end of the input power supply reverse connection prevention circuit is connected with the input end of the voltage conversion circuit; the input power supply reverse connection preventing circuit is used for protecting a rear-stage circuit from being damaged by input reverse voltage; the voltage conversion circuit is used for converting and filtering input power supply voltage; the signal processing circuit is used for digital signal processing; the storage circuit is used for storing system key information and effective information; the video output circuit is used for outputting video signals.

As shown in fig. 2, the input power supply reverse connection prevention circuit includes a resistor R1, a capacitor C1, a field effect transistor Q1, a resistor R424, a resistor R2, and a capacitor C2; one pin of the resistor R1 is respectively connected with one pin of the capacitor C1 and two pins of the field effect transistor Q1; one pin of the field effect transistor Q1 is connected with one pin of a resistor R2 and one pin of a capacitor C2; the three pins of the field effect transistor Q1 are connected with two pins of a resistor R2, two pins of a capacitor C2 and one pin of a resistor R424; two pins of the resistor R1, two pins of the capacitor C1 and two pins of the resistor R424 are all grounded; one pin of the resistor R1 is an external power input terminal, and one pin of the capacitor C2 is a power output terminal.

As shown in fig. 3, the voltage conversion circuit includes a capacitor C228, a capacitor C13, a resistor R13, a capacitor C229, a resistor R420, a capacitor C15, a capacitor C16, a capacitor C17, a resistor R15, a resistor R19, a resistor R16, an inductor L2, an integrated power chip U2, an inductor L7, a resistor R17, a resistor R18, a resistor R26, a capacitor C18, a capacitor C19, a resistor R24, a resistor R23, a resistor R423, and a capacitor C20;

a seventh pin of the integrated power chip U2 is respectively connected with a pin of the capacitor C228, a pin of the capacitor C13, a pin of the resistor R13 and a pin of the resistor R420; the fourth pin of the integrated power chip U2 is respectively connected with two pins of a resistor R13 and one pin of a capacitor C229, and the second pin of the integrated power chip U2 is respectively connected with two pins of a resistor R420 and one pin of a capacitor C15; in this embodiment, the common terminal of one pin of the capacitor C13 is a 3.3V output terminal, which supplies power to all 3.3V devices in the scheme;

a sixth pin of the integrated power chip U2 is connected with a pin of an inductor L2, two pins of the inductor L2 are connected with a pin of a capacitor C16, a pin of a capacitor C17 and a pin of a resistor R15, two pins of a resistor R15 are connected with a pin of a resistor R19, a pin of a resistor R16 and a pin of a resistor R24, and two pins of the resistor R16 are connected with an eighth pin of the integrated power chip U2; the common end of one pin of the capacitor C16 is used as a power supply input end and can be connected with one pin of the capacitor C2;

two pins of the resistor R24 are connected with one pin of a resistor R23, and two pins of the resistor R23 are respectively connected with one pin of a resistor R423 and one pin of a capacitor C20; two pins of the resistor R423 are PWM debugging ends;

a first pin of the integrated power chip U2 is connected with a pin of a resistor R17, two pins of the resistor R17 are respectively connected with a pin of a resistor R26 and a pin of a resistor R18, two pins of the resistor R18 are respectively connected with a pin of an inductor L7, a pin of a capacitor C18 and a pin of a capacitor C19, and two pins of the inductor L7 are connected with a third pin of the integrated power chip U2; the common end of one pin of the capacitor C19 is a 1.35V output end, and supplies power for all 1.35V devices in the scheme;

the fifth pin of the integrated power chip U2, the two pins of the capacitor C228, the two pins of the capacitor C13, the two pins of the capacitor C229, the two pins of the capacitor C15, the two pins of the capacitor C16, the two pins of the capacitor C17, the two pins of the capacitor C18, the two pins of the capacitor C19, the two pins of the resistor R26 and the two pins of the capacitor C20 are all grounded.

As shown in fig. 4, the signal processing circuit includes an integrated chip U1, a capacitor C122, a capacitor C141, a capacitor C139, a capacitor C123, a resistor R165, and an inductor L5;

one pin of the capacitor C122 is connected with the U12 th pin of the integrated chip U1; one pin of the capacitor C141 is connected with the P15 th pin of the integrated chip U1; one pin of the capacitor C139 is connected with the P14 th pin of the integrated chip U1; the D16 th pin of the integrated chip U1 is respectively connected with a pin of the inductor L5 and a pin of the capacitor C123; two pins of the resistor R165 are connected with a B13 pin of the integrated chip U1; two pins of the capacitor C122, two pins of the capacitor C141, two pins of the capacitor C139, a second pin of the capacitor C123, and two pins of the inductor L5 are all grounded.

As shown in fig. 5, the memory circuit includes an integrated chip U16, a resistor R12, a resistor R22, a resistor R21, a resistor R406, and a resistor R132;

two pins of the resistor R12 are connected with a first pin of an integrated chip U16; one pin of the resistor R22 is connected with the third pin of the integrated chip U16; two pins of the resistor R21 are connected with one pin of the resistor R406; two pins of the resistor R406 are respectively connected with the seventh pin of the integrated chip U16 and one pin of the resistor R132; the fourth pin of the integrated chip U16 and the ninth pin of the integrated chip U16 are both grounded.

As shown in fig. 6, the video output circuit includes an integrated chip U17, a capacitor C238, a resistor R410, a resistor R409, a capacitor C219, a crystal oscillator X2, a capacitor C218, a resistor R411, a resistor R407, a resistor R408, a capacitor C220, a resistor R413, a resistor R412, an inductor LB22, a capacitor C216, a capacitor C217, and a capacitor C221;

one pin of the inductor LB22 is connected with one pin of the capacitor C221 and the fourteenth pin of the integrated chip U17 respectively, and two pins of the inductor LB22 are connected with one pin of the capacitor C216, one pin of the capacitor C217, one pin of the capacitor C220, the second twelve pin of the integrated chip U17 and the twentieth pin of the integrated chip U17 respectively;

one pin of the resistor R411, one pin of the resistor R407 and one pin of the resistor R408 are connected with the output end of the voltage conversion circuit; two pins of the resistor R411 are connected with a nineteenth pin of the integrated chip U17, two pins of the resistor R407 are connected with an eighteenth pin of the integrated chip U17, and two pins of the resistor R408 are connected with a seventeenth pin of the integrated chip U17;

one pin of the capacitor C221 is connected to the fourteenth pin of the ic U17, and one pin of the resistor R412 is connected to one pin of the resistor R413 and the twenty-first pin of the ic U17, respectively; a pin of the resistor R410 is respectively connected with a twenty-sixth pin of the integrated chip U17, a pin of the capacitor C218 and a first pin of the crystal oscillator X2; two pins of the resistor R410 are respectively connected with the twenty-fifth pin of the integrated chip U17 and one pin of the resistor R409; two pins of the resistor R409 are respectively connected with a third pin of the crystal oscillator X2 and a pin of the capacitor C219;

two pins of the capacitor C218, two pins of the capacitor C221, two pins of the resistor R413, two pins of the capacitor C219, two pins of the crystal oscillator X2, and a fourth pin of the crystal oscillator X2 are all grounded.

It should be noted that, for simplicity of description, the above-mentioned embodiments of the method are described as a series of acts or combinations, but those skilled in the art should understand that the present application is not limited by the order of acts described, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and elements referred to are not necessarily required in this application.

Claims (6)

1. The utility model provides a low-power consumption image receiving circuit based on WIFI which characterized in that: the anti-reverse-connection control circuit comprises a voltage conversion circuit, a signal processing circuit, a storage circuit, a video output circuit and an input power supply anti-reverse-connection circuit, wherein the storage circuit and the video output circuit are connected with the signal processing circuit, and the output end of the voltage conversion circuit is respectively connected with the power supply ends of the storage circuit, the signal processing circuit and the video output circuit; the output end of the input power supply reverse connection prevention circuit is connected with the input end of the voltage conversion circuit.

2. The WIFI-based low-power-consumption image receiving circuit according to claim 1, wherein: the input power supply reverse connection prevention circuit comprises a resistor R1, a capacitor C1, a field effect transistor Q1, a resistor R424, a resistor R2 and a capacitor C2; one pin of the resistor R1 is respectively connected with one pin of the capacitor C1 and two pins of the field effect transistor Q1; one pin of the field effect transistor Q1 is connected with one pin of a resistor R2 and one pin of a capacitor C2; the three pins of the field effect transistor Q1 are connected with two pins of a resistor R2, two pins of a capacitor C2 and one pin of a resistor R424; two pins of the resistor R1, two pins of the capacitor C1 and two pins of the resistor R424 are all grounded.

3. The WIFI-based low-power-consumption image receiving circuit according to claim 1, wherein: the voltage conversion circuit comprises a capacitor C228, a capacitor C13, a resistor R13, a capacitor C229, a resistor R420, a capacitor C15, a capacitor C16, a capacitor C17, a resistor R15, a resistor R19, a resistor R16, an inductor L2, an integrated power chip U2, an inductor L7, a resistor R17, a resistor R18, a resistor R26, a capacitor C18, a capacitor C19, a resistor R24, a resistor R23, a resistor R423 and a capacitor C20;

a seventh pin of the integrated power chip U2 is respectively connected with a pin of the capacitor C228, a pin of the capacitor C13, a pin of the resistor R13 and a pin of the resistor R420; the fourth pin of the integrated power chip U2 is respectively connected with two pins of a resistor R13 and one pin of a capacitor C229, and the second pin of the integrated power chip U2 is respectively connected with two pins of a resistor R420 and one pin of a capacitor C15;

a sixth pin of the integrated power chip U2 is connected with a pin of an inductor L2, two pins of the inductor L2 are connected with a pin of a capacitor C16, a pin of a capacitor C17 and a pin of a resistor R15, two pins of a resistor R15 are connected with a pin of a resistor R19, a pin of a resistor R16 and a pin of a resistor R24, and two pins of the resistor R16 are connected with an eighth pin of the integrated power chip U2;

two pins of the resistor R24 are connected with one pin of a resistor R23, and two pins of the resistor R23 are respectively connected with one pin of a resistor R423 and one pin of a capacitor C20; two pins of the resistor R423 are PWM debugging ends;

a first pin of the integrated power chip U2 is connected with a pin of a resistor R17, two pins of the resistor R17 are respectively connected with a pin of a resistor R26 and a pin of a resistor R18, two pins of the resistor R18 are respectively connected with a pin of an inductor L7, a pin of a capacitor C18 and a pin of a capacitor C19, and two pins of the inductor L7 are connected with a third pin of the integrated power chip U2;

the fifth pin of the integrated power chip U2, the two pins of the capacitor C228, the two pins of the capacitor C13, the two pins of the capacitor C229, the two pins of the capacitor C15, the two pins of the capacitor C16, the two pins of the capacitor C17, the two pins of the capacitor C18, the two pins of the capacitor C19, the two pins of the resistor R26 and the two pins of the capacitor C20 are all grounded.

4. The WIFI-based low-power-consumption image receiving circuit according to claim 1, wherein: the signal processing circuit comprises an integrated chip U1, a capacitor C122, a capacitor C141, a capacitor C139, a capacitor C123, a resistor R165 and an inductor L5;

one pin of the capacitor C122 is connected with the U12 th pin of the integrated chip U1; one pin of the capacitor C141 is connected with the P15 th pin of the integrated chip U1; one pin of the capacitor C139 is connected with the P14 th pin of the integrated chip U1; the D16 th pin of the integrated chip U1 is respectively connected with a pin of the inductor L5 and a pin of the capacitor C123; two pins of the resistor R165 are connected with a B13 pin of the integrated chip U1; two pins of the capacitor C122, two pins of the capacitor C141, two pins of the capacitor C139, a second pin of the capacitor C123, and two pins of the inductor L5 are all grounded.

5. The WIFI-based low-power-consumption image receiving circuit according to claim 1, wherein: the memory circuit comprises an integrated chip U16, a resistor R12, a resistor R22, a resistor R21, a resistor R406 and a resistor R132;

two pins of the resistor R12 are connected with a first pin of an integrated chip U16; one pin of the resistor R22 is connected with the third pin of the integrated chip U16; two pins of the resistor R21 are connected with one pin of the resistor R406; two pins of the resistor R406 are respectively connected with the seventh pin of the integrated chip U16 and one pin of the resistor R132; the fourth pin of the integrated chip U16 and the ninth pin of the integrated chip U16 are both grounded.

6. The WIFI-based low-power-consumption image receiving circuit according to claim 1, wherein: the video output circuit comprises an integrated chip U17, a capacitor C238, a resistor R410, a resistor R409, a capacitor C219, a crystal oscillator X2, a capacitor C218, a resistor R411, a resistor R407, a resistor R408, a capacitor C220, a resistor R413, a resistor R412, an inductor LB22, a capacitor C216, a capacitor C217 and a capacitor C221;

one pin of the inductor LB22 is connected with one pin of the capacitor C221 and the fourteenth pin of the integrated chip U17 respectively, and two pins of the inductor LB22 are connected with one pin of the capacitor C216, one pin of the capacitor C217, one pin of the capacitor C220, the second twelve pin of the integrated chip U17 and the twentieth pin of the integrated chip U17 respectively;

one pin of the resistor R411, one pin of the resistor R407 and one pin of the resistor R408 are connected with the output end of the voltage conversion circuit; two pins of the resistor R411 are connected with a nineteenth pin of the integrated chip U17, two pins of the resistor R407 are connected with an eighteenth pin of the integrated chip U17, and two pins of the resistor R408 are connected with a seventeenth pin of the integrated chip U17;

one pin of the capacitor C221 is connected to the fourteenth pin of the ic U17, and one pin of the resistor R412 is connected to one pin of the resistor R413 and the twenty-first pin of the ic U17, respectively; a pin of the resistor R410 is respectively connected with a twenty-sixth pin of the integrated chip U17, a pin of the capacitor C218 and a first pin of the crystal oscillator X2; two pins of the resistor R410 are respectively connected with the twenty-fifth pin of the integrated chip U17 and one pin of the resistor R409; two pins of the resistor R409 are respectively connected with a third pin of the crystal oscillator X2 and a pin of the capacitor C219;

two pins of the capacitor C218, two pins of the capacitor C221, two pins of the resistor R413, two pins of the capacitor C219, two pins of the crystal oscillator X2, and a fourth pin of the crystal oscillator X2 are all grounded.

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