CN210052153U - Buffer for serving Internet of things - Google Patents

Abstract

A buffer serving for the Internet of things comprises components such as a buffer U903, a voltage V, a clock chip U702, a resistor R720, a resistor R721, a resistor R900, a resistor R901, a capacitor C950, a capacitor C951, a capacitor C952, a capacitor C953, a controller CON2 and the like. The SO pin of the buffer U903 is connected to the signal data output end, the WP pin of the buffer U903, one end of the resistor R901 and the No. 2 pin of the controller CON2 share a node, and one end of the resistor R901, which is far away from the WP pin of the buffer U903, is grounded. By setting multi-point control and selecting the M25P32 memory, the method simplifies circuit elements and the like, reduces the construction cost of the buffer in the circuit of the Internet of things, and realizes the control of the buffer in multiple directions.

Description

Buffer for serving Internet of things

Technical Field

The utility model relates to a thing networking communication field, in particular to buffer that serves thing networking.

Background

With the progress of internet technology, the internet of things has also been developed in a leap-type manner. The current internet of things is mature, and for the development of the internet of things, quick, low-cost and large-storage-capacity storage is important. In the development process of the internet of things at present, a plurality of different options are provided for the construction of the memory. However, most of the buffers have low storage efficiency and small storage data amount, and the memory circuit design is too complicated, which results in high cost and complicated lines.

SUMMERY OF THE UTILITY MODEL

The novel purpose of this use lies in improving buffer processing efficiency, reduces buffer construction cost. The utility model provides a buffer for serving thing networking, the purpose is in order to solve present thing networking storage. The cache circuit has low storage efficiency and high circuit construction cost.

The utility model adopts the following technical proposal:

a buffer for serving the Internet of things comprises a buffer U903, a voltage V, a clock chip U702, a resistor R720, a resistor R721, a resistor R900, a resistor R901, a capacitor C950, a capacitor C951, a capacitor C952, a capacitor C953 and a controller CON 2; an nCS pin of the buffer U903 is connected to a chip selection input end through a resistor R900; an SO pin of the buffer U903 is connected to a signal data output end; an nWP pin of the buffer U903, one end of a resistor R901 and a No. 2 pin of the controller CON2 share a node, and one end of the resistor R901, which is far away from a nWP pin of the buffer U903, is grounded; the GND pin of the buffer U903 is grounded, and the capacitor C950, the capacitor C951, the capacitor C952 and the capacitor C953 are connected between the GND pin of the buffer U903 and the ground in parallel; an SI pin of the buffer U903 is connected to a signal data input end; the SCK pin of the buffer U903, one end of the resistor R720 and one end of the resistor R721 are connected to a common node, one end of the resistor R720, which is far away from the SCK pin of the buffer U903, is connected to the SCL pin of the clock chip U702, and one end of the resistor R721, which is far away from the SCK pin of the buffer U903, is connected to the SDA pin of the clock chip U702; an nHOLD pin of the buffer U903 is connected to a termination signal end; a VCC pin of the buffer U903, a No. 1 pin of the controller CON2 and an output end of the voltage share a node; the VCC pin of the clock chip U702 is connected to a voltage input signal; the GND pin of the clock chip U702 is grounded.

Use the utility model discloses the time, when chip select input is high, deselect this device. When the chip selection signal of the device is pulled down and enabled, the device enters a normal working mode. The nHOLD pin of the buffer U903 is connected with a signal end, and the function of the signal end is to terminate the buffer and external communication. Two pins of the controller CON2 are connected to the VCC pin of the buffer U903 and the nWP pin of the buffer U903, the input pin and the power supply pin, respectively, and these two functions are selected according to the range of the supply voltage. The input voltage functions as a control input at this time if it is in the low voltage range (0-Vcc). The controller can implement control of the storage. The voltage can provide a stable voltage input, and a plurality of resistors are connected in parallel between the GND pin of the buffer U903 and the ground to avoid the passing of direct current when the direct ground is connected and to avoid the interference of alternating current.

Further, a standby power supply BT701 is included, a negative pole of the standby power supply BT701 is connected to a VBAT pin of the clock chip U702, and a positive pole of the standby power supply BT701 is connected to a GND pin of the clock chip U702.

When an accident happens to the server, the ground of the clock chip U702 is disconnected, and the standby power supply BT701 starts to work as a missing chip to provide stable working voltage.

Further, the model of the buffer U903 is M25P 32.

M25P32 is a 32Mbit (4M × 8) serial flash memory with an enhanced write protection architecture. The access uses the SPI bus protocol. 1-256 bytes can be programmed at one time. The enhanced fast program, erase mode may be adapted for situations where fast storage is required

Further, the model of the clock chip U702 is DS 3231.

DS3231 is a high precision I2C Real Time Clock (RTC) device with an integrated temperature compensated crystal oscillator (TCXO). The device includes a battery input that maintains accurate timing when the main power supply is turned off. The integrated crystal oscillator may improve the long term accuracy of the device. The registers of DS3231 can hold information such as seconds, minutes, hours, weeks, dates, months, years, and alarm settings. Less than 31 days of the month, the end of month date can be automatically adjusted, including leap year compensation. The clock operates in a 12 hour format with an AM or PM indication for 24 hours. DS3231 provides two programmable calendar alarm clocks and a programmable square wave output. The DS3231 and the single chip microcomputer transmit addresses and data through an I2C bidirectional serial bus.

Compared with the prior art, in the practical application of thing networking, the sexual valence relative altitude of whole circuit design. Meanwhile, the controller is arranged, so that the control of the buffer is more efficient. The number of components required by the circuit is less than that of components required by a conventional scheme, and the circuit cost required by building the Internet of things is reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a buffer of a service and internet of things provided by the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in detail below with reference to the accompanying drawings, and the exemplary embodiments and descriptions of the present invention are only used for explaining the present invention, and are not intended to limit the present invention.

Example 1

As shown in fig. 1, is a cache serving the internet of things,

a buffer for serving the Internet of things comprises a buffer U903, a voltage V, a clock chip U702, a resistor R720, a resistor R721, a resistor R900, a resistor R901, a capacitor C950, a capacitor C951, a capacitor C952, a capacitor C953 and a controller CON 2; an nCS pin of the buffer U903 is connected to a chip selection input end through a resistor R900; an SO pin of the buffer U903 is connected to a signal data output end; an nWP pin of the buffer U903, one end of a resistor R901 and a No. 2 pin of the controller CON2 share a node, and one end of the resistor R901, which is far away from a nWP pin of the buffer U903, is grounded; the GND pin of the buffer U903 is grounded, and the capacitor C950, the capacitor C951, the capacitor C952 and the capacitor C953 are connected between the GND pin of the buffer U903 and the ground in parallel; an SI pin of the buffer U903 is connected to a signal data input end; the SCK pin of the buffer U903, one end of the resistor R720 and one end of the resistor R721 are connected to a common node, one end of the resistor R720, which is far away from the SCK pin of the buffer U903, is connected to the SCL pin of the clock chip U702, and one end of the resistor R721, which is far away from the SCK pin of the buffer U903, is connected to the SDA pin of the clock chip U702; an nHOLD pin of the buffer U903 is connected to a termination signal end; a VCC pin of the buffer U903, a No. 1 pin of the controller CON2 and an output end of the voltage share a node; the VCC pin of the clock chip U702 is connected to a voltage input signal; the GND pin of the clock chip U702 is grounded.

Use the utility model discloses the time, when chip select input was high, deselected this device. When the chip selection signal of the device is pulled down and enabled, the device enters a normal working mode. The nHOLD pin of the buffer U903 is connected with a signal end, and the function of the signal end is to terminate the buffer and external communication. Two pins of the controller CON2 are connected to the VCC pin of the buffer U903 and the nWP pin of the buffer U903, the input pin and the power supply pin, respectively, and these two functions are selected according to the range of the supply voltage. The input voltage functions as a control input at this time if it is in the low voltage range (0-Vcc). The controller can implement control of the storage. The voltage can provide a stable voltage input, and a plurality of resistors are connected in parallel between the GND pin of the buffer U903 and the ground to avoid the passing of direct current when the direct ground is connected and to avoid the interference of alternating current.

Further, a standby power supply BT701 is included, a negative pole of the standby power supply BT701 is connected to a VBAT pin of the clock chip U702, and a positive pole of the standby power supply BT701 is connected to a GND pin of the clock chip U702.

When an accident happens to the server, the ground of the clock chip U702 is disconnected, and the standby power supply BT701 starts to work as a missing chip to provide stable working voltage.

In this embodiment, the selection value of the resistor R900 is 10K, the selection value of the resistor R901 is 4K, the selection addresses of the resistor R720 and the resistor R721 are both 10K, and the selection values of the capacitor C950, the capacitor C951, the capacitor C952 and the capacitor C953 are all 10 μ F. The operating voltage of the circuit is designed to be 3V.

Further, the model of the buffer U903 is M25P 32.

M25P32 is a 32Mbit (4M × 8) serial flash memory with an enhanced write protection architecture. The access uses the SPI bus protocol. 1-256 bytes can be programmed at one time. The enhanced fast program, erase mode may be suitable where fast storage is required.

Further, the model of the clock chip U702 is DS 3231.

DS3231 is a high precision I2C Real Time Clock (RTC) device with an integrated temperature compensated crystal oscillator (TCXO). The device includes a battery input that maintains accurate timing when the main power supply is turned off. The integrated crystal oscillator may improve the long term accuracy of the device. The registers of DS3231 can hold information such as seconds, minutes, hours, weeks, dates, months, years, and alarm settings. Less than 31 days of the month, the end of month date can be automatically adjusted, including leap year compensation. The clock operates in 24 hour or 12 hour format with AM/PM indication. DS3231 provides two programmable calendar alarm clocks and a programmable square wave output. The DS3231 and the single chip microcomputer transmit addresses and data through an I2C bidirectional serial bus.

The above-mentioned embodiments further describe the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and do not serve to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (4)

1. A cache serving an internet of things, comprising: the circuit comprises a buffer U903, a voltage V, a clock chip U702, a resistor R720, a resistor R721, a resistor R900, a resistor R901, a capacitor C950, a capacitor C951, a capacitor C952, a capacitor C953 and a controller CON 2; an nCS pin of the buffer U903 is connected to a chip selection input end through a resistor R900; an SO pin of the buffer U903 is connected to a signal data output end; an nWP pin of the buffer U903, one end of a resistor R901 and a No. 2 pin of the controller CON2 share a node, and one end of the resistor R901, which is far away from a nWP pin of the buffer U903, is grounded; the GND pin of the buffer U903 is grounded, and the capacitor C950, the capacitor C951, the capacitor C952 and the capacitor C953 are connected between the GND pin of the buffer U903 and the ground in parallel; an SI pin of the buffer U903 is connected to a signal data input end; the SCK pin of the buffer U903, one end of the resistor R720 and one end of the resistor R721 are connected to a common node, one end of the resistor R720, which is far away from the SCK pin of the buffer U903, is connected to the SCL pin of the clock chip U702, and one end of the resistor R721, which is far away from the SCK pin of the buffer U903, is connected to the SDA pin of the clock chip U702; an nHOLD pin of the buffer U903 is connected to a termination signal end; a VCC pin of the buffer U903, a No. 1 pin of the controller CON2 and an output end of the voltage share a node; the VCC pin of the clock chip U702 is connected to a voltage input signal; the GND pin of the clock chip U702 is grounded.

2. A cache for serving the internet of things as recited in claim 1, wherein: the standby power supply BT701 is further included, wherein the negative pole of the standby power supply BT701 is connected to the VBAT pin of the clock chip U702, and the positive pole of the standby power supply BT701 is connected to the GND pin of the clock chip U702.

3. A cache for serving the internet of things as recited in claim 1, wherein: the buffer U903 is M25P 32.

4. A cache for serving the internet of things as recited in claim 1, wherein: the model of the clock chip U702 is DS 3231.