CN210041789U - Biasing circuit, integrated clock circuit and integrated circuit chip - Google Patents
Biasing circuit, integrated clock circuit and integrated circuit chip Download PDFInfo
- Publication number
- CN210041789U CN210041789U CN201822197117.XU CN201822197117U CN210041789U CN 210041789 U CN210041789 U CN 210041789U CN 201822197117 U CN201822197117 U CN 201822197117U CN 210041789 U CN210041789 U CN 210041789U
- Authority
- CN
- China
- Prior art keywords
- voltage
- circuit
- resistor
- module
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The utility model provides a biasing circuit, include: the input voltage division module is used for dividing the voltage of the external power input to generate a first voltage signal; the amplifying module is used for amplifying the first voltage signal; the current mirror module is used for receiving an output signal of the first output end of the amplifying module and outputting a bias current through the first output end of the current mirror module; the output voltage division module is used for dividing the output signal of the second output end of the current mirror module to generate high comparison voltage and low comparison voltage; wherein the high comparison voltage, the low comparison voltage and the bias current are respectively proportional to the external power input. A second aspect of the present invention provides an integrated clock circuit. A third aspect of the present application provides an integrated circuit chip.
Description
Technical Field
The utility model relates to an integrated circuit technical field. And more particularly to a bias circuit, an integrated clock circuit, and an integrated circuit chip.
Background
Integrated clock circuits are widely used inside chips, which often require operation at different supply voltages; also, the disturbance of the power supply voltage may disturb the operation of the clock circuit. Therefore, the clock signal generated by the integrated clock circuit needs to be unaffected by the supply voltage.
To achieve this, there are two common methods:
the first method comprises the following steps: the external crystal oscillator circuit provides a reference oscillation signal, and the frequency division is carried out to obtain the desired clock signal frequency. The method needs to occupy IO port resources, and the larger area of the crystal oscillator increases the cost of the system and is not beneficial to integration;
the second method comprises the following steps: FIG. 1 shows a typical integrated clock oscillator circuit for this method, with a clock period of equation (1)
Wherein N is the internal counter current I of the oscillating circuitbMagnification or reduction.
Referring to equation (1), if the clock period T is not affected by the power supply voltage, the comparison voltage V is requiredH、VLAnd a bias current IbThe circuit is not influenced by the power supply voltage, and for achieving the purpose, a more complex current stabilizing source, a band gap circuit and a linear voltage regulator circuit are needed to provide bias current and comparison voltage which are not influenced by the power supply voltage for a clock circuit, as shown in a block diagram of fig. 2. This approach also increases the chip area, which also leads to increased power consumption and circuit complexity.
Therefore, there is a need for a bias circuit that can provide a bias to an oscillation circuit, an integrated clock circuit that is biased by the bias circuit and that can be more structurally simplified to facilitate integration while satisfying the condition that the frequency of a clock signal generated by the integrated clock circuit is not affected by a power supply, and an integrated circuit chip that includes the integrated clock circuit.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a frequency of the clock signal of clock circuit output does not receive mains voltage influence in addition.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
an aspect of the present application provides a bias circuit, including:
the input voltage division module is used for dividing the voltage of the external power input to generate a first voltage signal;
the amplifying module is used for amplifying the first voltage signal;
the current mirror module is used for receiving an output signal of the first output end of the amplifying module and outputting a bias current through the first output end of the current mirror module; and
the output voltage division module is used for dividing the output signal of the second output end of the current mirror module to generate high comparison voltage and low comparison voltage;
wherein the high comparison voltage, the low comparison voltage and the bias current are respectively proportional to the external power input.
Preferably, the amplifying module comprises an operational amplifier;
the current mirror module comprises a first PMOS tube and a second PMOS tube; and
the output voltage division module comprises a first resistor and a second resistor,
the inverting input end of the operational amplifier is used as the input end of the amplification module, the non-inverting input end of the operational amplifier is connected with the drain electrode of the first PMOS tube, the output end of the operational amplifier is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the external power supply input, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the external power supply input, the drain electrode of the second PMOS tube is used as the output end of the current mirror module, the first resistor and the second resistor are connected in series at the common end of the non-inverting input end of the operational amplifier and the drain electrode of the first PMOS tube, the other end of the second resistor is grounded, the voltage of the common end is used as a high comparison voltage, and the voltage.
Preferably, the input voltage division module includes a third resistor and a fourth resistor, one end of the third resistor is connected to the external power input, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is grounded, and a common end of the third resistor and the fourth resistor is connected to the inverting input end of the operational amplifier.
A second aspect of the present application provides an integrated clock circuit comprising an oscillation circuit and the above-mentioned bias circuit, the oscillation circuit being configured to generate a clock signal according to a high comparison voltage, a low comparison voltage and a bias current output by the bias circuit.
A third aspect of the application provides an integrated circuit chip comprising the integrated clock circuit described above.
The utility model has the advantages as follows:
technical scheme provide an integrated clock circuit, its clock signal frequency that satisfies integrated clock circuit production does not receive under the power influence's the condition, can the structure do benefit to the integration more simply to and by this integrated clock circuit's integrated circuit chip.
Drawings
The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings;
FIG. 1 is a circuit schematic of a typical integrated clock oscillator circuit of the prior art;
FIG. 2 is a block diagram of a typical integrated clock circuit of the prior art;
FIG. 3 is a block diagram of an integrated clock circuit according to an embodiment of the present application; and
FIG. 4 is a circuit schematic diagram illustrating in detail the biasing circuit of the integrated clock circuit according to an embodiment of the present application.
Detailed Description
In order to explain the present invention more clearly, the present invention will be further described with reference to the preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
In order to explain the present invention more clearly, the present invention will be further described with reference to the preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
It should be understood that the ordinal numbers first, second, etc. described in the specification are for clarity of description only and are not intended to limit the order of elements, parts, or components, etc., i.e., a description of a first element, part, or component and a second element, part, or component may also refer to a second element, part, or component and the first element, part, or component.
Fig. 3 shows a block diagram of integrated clock circuit 10 according to an embodiment of the present application.
As shown in fig. 3, integrated clock circuit 10 includes: an oscillation circuit 101 and a bias circuit 103. The bias circuit 103 generates a high comparison voltage V according to an external power inputHLow comparative voltage VLAnd a bias current IbWherein, in the oscillating circuit 101, the comparison voltage V is highHAnd a low comparative voltage VLUsed as a comparison voltage for generating an oscillating clock, bias current IbProviding an oscillator circuit with an AND (V)H-VL) The specific effect of the respective quantities of the reference current, which is proportional to the fixed ratio, can be seen in the schematic diagram of the oscillating circuit shown in fig. 1. Embodiments according to the present application are not limited to the oscillation circuit shown in fig. 1, and the oscillation circuit may be various RC oscillation circuits. However, it will be appreciated by those skilled in the art that the principles of other types of RC oscillator circuits are similar and all require the provision of a high comparison voltage V for comparisonHAnd a low comparative voltage VLAnd a bias current I for providing a reference currentb。
The oscillating circuit 101 is based on a high comparison voltage V input theretoHLow comparative voltage VLAnd a bias current IbGenerating a clock oscillation period as a clock output by the bias circuit 103 according to the embodiment of the present applicationHigh comparison voltage VHLow comparative voltage VLAnd a bias current IbThe clock oscillation period as the clock output is made independent of the external power supply input, and is made dependent only on the parameters of the components in the bias circuit 103 and the oscillation circuit 101, so that the clock frequency of the integrated clock circuit 10 is not affected by the external power supply.
The principle of the bias circuit 103 and the integrated clock circuit 10 including the bias circuit 103 according to the embodiment of the present application is further described below with reference to fig. 4, wherein fig. 4 is a circuit schematic diagram illustrating the bias circuit 103 of the integrated clock circuit according to the embodiment of the present application in detail.
The bias circuit 103 according to an embodiment of the present application includes an input voltage division module 103-1, an amplification module 103-2, a current mirror module 103-3, and an output voltage division module 103-4. Wherein, the input voltage division module 103-1 is arranged between the external power input and the amplification module 103-1, and divides the voltage signal input by the external power, and the divided voltage V isinAs an output signal of the input voltage module 103-1, a voltage signal VinAn input amplification module 103-2, the amplification module 103-2 is used for inputting a voltage signal VinAmplifying; the amplified signal is input to the input terminal of the current mirror module 103-3; the current mirror module 103-3 includes two output terminals, an output terminal C and an output terminal A, the output terminal C is used as a current output terminal, and the output current is used as a bias current IbThe output end A is used as a voltage output end and is connected with the output voltage division module 103-4; the output voltage division module 103-4 divides the output signal of the output end A of the current mirror module 103-3, the divided voltage is used as the output of the module, and a high comparison voltage V is generatedHAnd a low comparative voltage VL. High comparison voltage V generated by the above structureHLow comparative voltage VLAnd a bias current IbRespectively, proportional to the external power input.
The circuit principle of the bias circuit 103 and the integrated clock circuit 10 provided with the bias circuit 103 is further described below in terms of the specific internal constitution and connection relationship of the respective blocks of the circuit.
The bias circuit 103 has three outputs: the output end A is an oscillating circuit101 providing a high comparison voltage VHThe output terminal B provides a low comparative voltage V for the oscillating circuit 101LThe output terminal C provides a bias current I for the oscillating circuit 101b。
The oscillation circuit 101 has three input terminals, which are input terminals D, respectively, connected to the output a of the bias circuit 103; an input terminal E connected to an output B of the bias circuit 103; an input terminal F connected to an output terminal C of the bias circuit 103; the output G of the oscillator circuit 101 generates the desired output clock output signal.
The specific design of the bias circuit 103 provided in this embodiment is shown in fig. 4:
as shown in fig. 4, the amplifying module 103-2 includes an operational amplifier OP 1; the current mirror module 103-3 comprises a PMOS transistor M1 and a PMOS transistor M2; the output voltage division module 103-4 comprises a resistor R1 and a resistor R2. The non-inverting input end of the operational amplifier OP1 is connected with the drain of the PMOS tube M1, the output end of the operational amplifier OP1 is connected with the gate of the PMOS tube M1, the drain of the PMOS tube M1 is simultaneously used as the output end A, the source of the PMOS tube M1 is connected with the external power supply input, the gate of the PMOS tube M2 is connected with the gate of the PMOS tube M1, the source of the PMOS tube is connected with the external power supply input, and the drain of the PMOS tube is used as the output end C of the bias circuit 103 to provide the bias current I for the oscillation circuit 101bThe output end A is connected with one end of a resistor R1 in the resistors R1 and R2 which are connected in series, and one end of the resistor R2 which is not connected with the resistor R1 is grounded.
In the present embodiment, an input voltage dividing module 103-1 may be further included, in the input voltage dividing module 103-1, an external power input connected to one end of the resistor R3 is divided by the resistors R3 and R4 connected in series, that is, a voltage across the resistor R4 is connected as a divided input to the inverting input terminal of the operational amplifier OP 1. It will be appreciated by those skilled in the art that this is a design requirement to create a suitable voltage differential between the pins of PMOS transistor M1 and to properly set the high comparative voltage VH. And those skilled in the art will understand that the designer can select the resistors R3 and R4 of the voltage divider circuit as desired.
The oscillating circuit may be a classic clock oscillating circuit example as shown in fig. 1, or other clock oscillating circuits designed with the same principle, not to mention a few examples here.
The working principle of the integrated clock circuit provided by the embodiment that the clock frequency is not affected by the power supply voltage is as follows:
as shown in FIG. 4, let V be the voltage input by the external power sourceDDThe voltage obtained by dividing the voltage by the resistors R3 and R4 is VinThe following were used:
equation (2)
The voltage Vin is fed into a negative feedback system composed of an OP1, a PMOS tube M1, a resistor R1 and a resistor R2, if the inverting input end of the operational amplifier OP1 is taken as the input end of the negative feedback system, the drain electrode of the PMOS tube M1 is taken as the output end of the negative feedback system, the open-loop gain of the operational amplifier OP1 is set as A1, the transconductance of the PMOS tube M1 is gm1, and the equivalent resistor is R1, the open-loop gain of the negative feedback system is A1openComprises the following steps:
equation (3) Aopen＝A1·gm·[r1||(R1+R2)]。
And because the output end A of the negative feedback system is directly short-circuited with the non-inverting input end of the operational amplifier OP1, the feedback gain is 1 according to the virtual short principle. The closed loop gain a of the systemcloseComprises the following steps:
equation (4)
Because A is1·gm·[r1||(R1+R2)]>>1, so closed loop gain AcloseCan be approximately considered as:
equation (5) Aclose＝1。
Therefore, the high comparison voltage V of the node AHIs equal to voltage Vin. Since R1 and R2 are divided, the voltage V at node BLComprises the following steps:
equation (6)
Current I flowing through PMOS transistor M1D1Equal to the current through R1 and R2,
equation (7)
If the ratio of the width-length ratio of the PMOS transistor M2 to the width-length ratio of the PMOS transistor M1 is
The current flowing through the PMOS transistor M2 is the bias current I of the oscillating circuit 101bComprises the following steps:
equation (8)
According to the clock oscillation period shown in equation (1), equations (2), (6), (8) and VH＝VinSubstituting equation (1) results in a clock period of:
equation (9)
As shown by equation (9), the clock period of the clock circuit is only related to the resistance value of the resistor R1 in the bias circuit 103 and the capacitance value of the capacitor C (not shown) in the oscillator circuit 101, which can be the charging capacitor of the oscillator circuit 101 and the width and length values of the PMOS transistor M1 and the PMOS transistor M2 according to the principle of the RC oscillator circuit, and is related to the voltage V inputted from the external power sourceDDIs irrelevant.
From the foregoing, embodiments of the present invention can see that the present invention provides an integrated clock circuit whose output clock frequency is not affected by the input of the external power source. When the function is realized, a simpler circuit design is used, and a complex band gap circuit, a linear voltage regulator and a current stabilizing source are replaced. Thereby reducing cost and saving power consumption.
Furthermore, embodiments of the present application may also include implementing as an integrated circuit chip including the integrated clock circuit 10 of the present application, and it will be understood by those skilled in the art that the integrated circuit chip may be any integrated circuit chip that needs to be integrated with the integrated clock circuit 10 and packaged separately, and by setting the clock as the integrated clock circuit 10, chip area may be saved, integration may be facilitated, and furthermore, other circuits in the integrated circuit chip may be provided with a stable clock frequency that is not affected by the external power input of the clock.
Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it is obvious for those skilled in the art to make other variations or changes based on the above descriptions, and all the embodiments cannot be exhausted here, and all the obvious variations or changes that belong to the technical solutions of the present invention are still in the protection scope of the present invention.
Claims (5)
1. A bias circuit, comprising:
the input voltage division module is used for dividing the voltage of the external power input to generate a first voltage signal;
the amplifying module is used for amplifying the first voltage signal;
the current mirror module is used for receiving an output signal of a first output end of the amplifying module and outputting a bias current through the first output end of the current mirror module; and
the output voltage division module is used for dividing the output signal of the second output end of the current mirror module to generate a high comparison voltage and a low comparison voltage;
wherein the high comparison voltage, the low comparison voltage, and the bias current are each proportional to the external power input.
2. The bias circuit of claim 1,
the amplification module comprises an operational amplifier;
the current mirror module comprises a first PMOS tube and a second PMOS tube; and
the output voltage division module comprises a first resistor and a second resistor,
wherein, the inverting input end of the operational amplifier is used as the input end of the amplifying module, the non-inverting input end of the operational amplifier is connected with the drain electrode of the first PMOS tube, the output end of the operational amplifier is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the external power input, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the external power input, the drain electrode of the second PMOS is used as the output end of the current mirror module, the first resistor and the second resistor are connected in series at the common end of the non-inverting input end of the operational amplifier and the drain electrode of the first PMOS tube, the other end of the second resistor is grounded, the voltage of the common end is used as the high comparison voltage, and the voltage of the connection point of the first resistor and the second resistor is used as the low comparison voltage.
3. The bias circuit according to claim 2, wherein the input voltage dividing module includes a third resistor and a fourth resistor, one end of the third resistor is connected to the external power input, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is grounded, and a common end of the third resistor and the fourth resistor is connected to the inverting input terminal of the operational amplifier.
4. An integrated clock circuit comprising an oscillating circuit and a biasing circuit according to any of claims 1-3,
the oscillation circuit is used for generating clock signals according to the high comparison voltage, the low comparison voltage and the bias current output by the bias circuit.
5. An integrated circuit chip comprising an integrated clock circuit as claimed in claim 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822197117.XU CN210041789U (en) | 2018-12-26 | 2018-12-26 | Biasing circuit, integrated clock circuit and integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822197117.XU CN210041789U (en) | 2018-12-26 | 2018-12-26 | Biasing circuit, integrated clock circuit and integrated circuit chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210041789U true CN210041789U (en) | 2020-02-07 |
Family
ID=69343166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822197117.XU Active CN210041789U (en) | 2018-12-26 | 2018-12-26 | Biasing circuit, integrated clock circuit and integrated circuit chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210041789U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111371447A (en) * | 2018-12-26 | 2020-07-03 | 华润半导体（深圳）有限公司 | Biasing circuit, integrated clock circuit and integrated circuit chip |
-
2018
- 2018-12-26 CN CN201822197117.XU patent/CN210041789U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111371447A (en) * | 2018-12-26 | 2020-07-03 | 华润半导体（深圳）有限公司 | Biasing circuit, integrated clock circuit and integrated circuit chip |
| CN111371447B (en) * | 2018-12-26 | 2024-08-06 | 华润微集成电路(无锡)有限公司 | Bias circuit, integrated clock circuit and integrated circuit chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202995523U (en) | Linear dropout regulator (LDO) with ultra-low power consumption and without output filtering capacitor | |
| US7400183B1 (en) | Voltage controlled oscillator delay cell and method | |
| CN105406824B (en) | Common mode feedback circuit, corresponding signal processing circuit and method | |
| US7570040B2 (en) | Accurate voltage reference circuit and method therefor | |
| CN106444949A (en) | Low-noise quick-start low-dropout linear regulator | |
| EP1111493A1 (en) | Low drop voltage regulators with low quiescent current | |
| CN110837268A (en) | Two-stage low dropout linear regulator with low noise and high power supply rejection ratio | |
| KR20050072547A (en) | Current reference circuit with voltage-current converter having auto-tuning function | |
| JPH02262714A (en) | Duty control circuit device | |
| CN103472882A (en) | Low dropout regulator of integrated slew rate enhancement circuit | |
| CN210041789U (en) | Biasing circuit, integrated clock circuit and integrated circuit chip | |
| CN110928350A (en) | A power supply with wide input voltage | |
| CN110572151B (en) | Phase-locked loop circuit | |
| CN111371447B (en) | Bias circuit, integrated clock circuit and integrated circuit chip | |
| Frederiksen et al. | A new current-differencing single-supply operational amplifier | |
| US7265609B2 (en) | Transconductor circuits | |
| US7928810B2 (en) | Oscillator arrangement and method for operating an oscillating crystal | |
| CN110632970B (en) | Fast transient response LDO and circuit thereof | |
| CN113126685B (en) | Noise filter circuit and low dropout regulator | |
| JPH0247883B2 (en) | ||
| CN211827062U (en) | High-precision high-power-supply-rejection-ratio depletion type voltage reference circuit | |
| CN112346506A (en) | LDO circuit without off-chip capacitor | |
| CN112859984A (en) | Linear voltage regulator circuit with high power supply rejection ratio and fast transient state | |
| TW202046045A (en) | Reference voltage generation circuit | |
| CN217846967U (en) | LDO circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210510 Address after: No.180-6, Linghu Avenue, Taihu International Science and Technology Park, Xinwu District, Wuxi City, Jiangsu Province, 214135 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: 518040 8a, block a, Tianxiang building, Tian'an Digital City, Futian District, Shenzhen City, Guangdong Province Patentee before: CHINA RESOURCES SEMICONDUCTOR (SHENZHEN) Co.,Ltd. |
|
| TR01 | Transfer of patent right |