CN209994360U - Capacitive touch key detection circuit - Google Patents
Capacitive touch key detection circuit Download PDFInfo
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- CN209994360U CN209994360U CN201920939467.0U CN201920939467U CN209994360U CN 209994360 U CN209994360 U CN 209994360U CN 201920939467 U CN201920939467 U CN 201920939467U CN 209994360 U CN209994360 U CN 209994360U
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Abstract
The utility model relates to a capacitance touch key detection circuit, which comprises a clock generation circuit, a phase inverter, a first comparator, a second comparator, a digital processing circuit and a first control switch, a second control switch, a third control switch, wherein the clock generation circuit is connected with the phase inverter, the control ends of the first control switch and the third control switch are connected with the clock generation circuit, the control end of the second control switch is connected with the output end of the phase inverter, the output end of the first comparator is connected with the positive phase input end of the second comparator, the output end of the second comparator is connected with the digital processing circuit, the first and second reference voltages are connected to the non-inverting input terminal of the first comparator through the first and second control switches, an inductive capacitor is connected to the inverting input end of the first comparator, a feedback capacitor and a third control switch are connected in parallel between the inverting input end of the first comparator and the output end of the first comparator, and a third reference voltage is connected to the inverting input end of the second comparator. The detection circuit has the advantages of wide capacitance detection range, strong anti-interference capability and easy realization.
Description
Technical Field
The utility model belongs to the technical field of the touch button detects, especially, relate to a capacitanc touch button detection circuitry.
Background
The capacitive touch key is a novel technology at present, and compared with the traditional mechanical key, the capacitive touch key has the characteristics of safety, no mechanical wear, long service life, water and pollution resistance, easiness in cleaning, fashion and the like.
Principle of capacitive touch keys: an induced capacitance exists between any two conductive objects, and an induced capacitance C0 is formed between the touch key (a pad on the PCB) and the ground. When a finger of a human body approaches the touch key, the induction capacitor Ch formed between the human body and the ground is connected in series with the induction capacitor Ct formed between the finger and the touch key, and then is connected in parallel with the induction capacitor C0 formed between the pad and the ground, so that the total induction capacitor value is increased. That is, when the finger does not contact the touch key, the capacitance value of the touch key is C0; when the finger touches the touch key, the capacitance value of the touch key rises to C0+ (Ch + Ct)/Ch × Ct, because the human body sensing capacitance Ch is much larger than the touch key capacitance Ct, the capacitance of the touch key is equal to C0+ Ct. Fig. 1 is a schematic diagram of detection of capacitance of a touch key, and a capacitive touch key detection circuit outputs a high level after detecting that a capacitance value of the touch key increases by a certain extent, indicating that the touch key has been touched by a finger. Because the increased amplitude of the capacitance value is smaller, the judgment and detection precision of the existing capacitive touch key detection circuit is lower, the problems of high false triggering probability, poor anti-electromagnetic interference capability and the like exist, and the detection range of the circuit for the increased amplitude of the capacitance value is narrow, so that the detection sensitivity of the touch key is lower.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a simple structure, easily realize, detect the capacitanc touch button detection circuitry that the precision is high and the interference killing feature is strong.
In order to achieve the above object, the present invention adopts the technical solution that, a capacitive touch key detection circuit comprises a clock generation circuit, a phase inverter, a first comparator, a second comparator, a digital processing circuit and first to third control switches, wherein an output terminal of the clock generation circuit is connected to an input terminal of the phase inverter, control terminals of the first control switch and the third control switch are connected to an output terminal of the clock generation circuit, a control terminal of the second control switch is connected to an output terminal of the phase inverter, an output terminal of the first comparator is connected to a positive input terminal of the second comparator, an output terminal of the second comparator is connected to an input terminal of the digital processing circuit, an output terminal of the digital processing circuit is led out as an output terminal of the detection circuit, a clock signal port of the digital processing circuit is connected to an output terminal of the clock generation circuit, a first reference voltage is connected to the positive input terminal of the first comparator through the first control switch, a second reference voltage is connected to a positive phase input end of the first comparator through a second control switch, an inverse phase input end of the first comparator is led out to serve as a connection end of the touch key, an induction capacitor between the touch key and the ground is connected to the inverse phase input end of the first comparator, a feedback capacitor and a third control switch are connected in parallel between the inverse phase input end of the first comparator and an output end of the first comparator, and a third reference voltage is connected to the inverse phase input end of the second comparator; when the digital processing circuit detects that the output end of the second comparator is at a high level in two continuous clock cycles, the digital processing circuit outputs the high level to indicate that the touch key is touched by a finger.
As an improvement of the utility model, the clock generation circuit includes oscillating circuit and D trigger frequency division circuit, and the input of D trigger frequency division circuit is connected to oscillating circuit's output, and D trigger frequency division circuit's output is as clock generation circuit's output, and frequency division circuit output duty cycle is 50% square wave signal.
As an improvement of the present invention, when the clock generating circuit outputs a high level, the first and third control switches are kept in an on state, and the second control switch is kept in an off state; when the clock generation circuit outputs a low level, the first and third control switches are kept in an off state, and the second control switch is kept in an on state.
As an improvement of the utility model, the voltage value of first to third reference voltage rises in proper order, and first reference voltage's voltage value is less than second reference voltage's voltage value promptly, and second reference voltage's voltage value is less than third reference voltage's voltage value.
As an improvement of the present invention, the digital processing circuit includes a detection module and a counting module, the input end of the detection module is connected to the output end of the second comparator, the output end of the detection module is connected to the input end of the counting module, the output end of the counting module is led out as the output end of the digital processing circuit, the clock control ends of the detection module and the counting module are both connected to the output end of the clock generation circuit, the detection module detects the level of the input signal when the clock signal is at the high level, and outputs the high level when the input signal is detected to be at the high level, and keeps the next detection period; when the detection module outputs a high level, the counting module starts to count the clock signal, and when the count reaches 2, the counting module outputs the high level and keeps the high level until the detection module outputs a low level.
As an improvement of the utility model, the value range of feedback electric capacity is 1pF ~ 100pF for the electric capacity detection range of circuit can reach 1pF minimum.
As an improvement of the utility model, the voltage value of third reference voltage sets up between the output voltage value of first comparator when capacitanc touch button is not touched and the output voltage value of first comparator when capacitanc touch button is touched by the finger.
As an improvement of the present invention, the first to third control switches are implemented by using a single PMOS transistor or NMOS transistor, and the gate of the PMOS transistor or NMOS transistor is used as the control terminal of the first to third control switches.
As an improvement of the present invention, the first to third control switches are implemented by a CMOS transmission gate formed by connecting an NMOS transistor and a PMOS transistor in parallel.
Compared with the prior art, the utility model provides a capacitive touch key detection circuit overall structure design benefit, simple structure is reasonable stable, easily realizes and the cost of manufacture is low, through using the clock to produce the on off state that the circuit combines the phase inverter to come periodic control first to third control switch, thereby makes detection circuit work in circuit self-correction stage and electric capacity detection stage in turn, effectively improves the performance parameter stability of circuit, and strengthens the anti-electromagnetic interference ability of circuit; in addition, the voltage values of the first to third reference voltages are sequentially increased, the third reference voltage value is set between the output voltage value of the first comparator when the capacitive touch key is not touched and the output voltage value of the first comparator when the capacitive touch key is touched by a finger, and the feedback capacitor is set between 1pF and 100pF, so that the capacitance increase value detection range of the circuit can be effectively improved while the false triggering can be effectively prevented, and the minimum capacitance increase value detection range of the circuit can reach 1 pF.
Drawings
Fig. 1 is a schematic block diagram of capacitance detection of a capacitive touch key in the prior art.
Fig. 2 is a structural diagram of a capacitive touch key detection circuit according to a preferred embodiment of the present invention.
Fig. 3 is a block diagram of a clock generating circuit in the capacitive touch key detection circuit according to the preferred embodiment of the present invention.
Fig. 4 is a block diagram of a data processing circuit in the capacitive touch key detection circuit according to the preferred embodiment of the present invention.
Fig. 5 is a simulation result diagram of the capacitive touch key detection circuit according to the preferred embodiment of the present invention under the condition that the touch key is not triggered.
Fig. 6 is a simulation result diagram of the capacitive touch key detection circuit according to the preferred embodiment of the present invention under the condition that the touch key is triggered by a finger.
Detailed Description
For the purposes of promoting an understanding and appreciation of the invention, the invention will be further described and illustrated in connection with the accompanying drawings.
As shown in fig. 2, a capacitive touch key detection circuit according to a preferred embodiment of the present invention includes a CLOCK generating circuit CLOCK, an inverter, a first comparator COMP _ a, a second comparator COMP _ B, a digital processing circuit, and first to third control switches, wherein the first and second comparators COMP _ B are all implemented by a common comparator, an output terminal of the CLOCK generating circuit CLOCK is connected to an input terminal of the inverter, control terminals of the first control switch SW1 and the third control switch SW3 are connected to an output terminal of the CLOCK generating circuit CLOCK, a control terminal of the second control switch SW2 is connected to an output terminal of the inverter, an output terminal OUTA of the first comparator COMP _ a is connected to a positive input terminal of the second comparator COMP _ B, an output terminal OUTB of the second comparator COMP _ B is connected to an input terminal of the digital processing circuit, and an output terminal of the digital processing circuit is led out as an output terminal of the detection circuit, a CLOCK signal port of the digital processing circuit is connected with an output end of a CLOCK generating circuit CLOCK, a first reference voltage VA is connected to a non-inverting input end INP of a first comparator COMP _ A through a first control switch SW1, a second reference voltage VB is connected to the non-inverting input end INP of the first comparator COMP _ A through a second control switch SW2, an inverting input end INN of the first comparator COMP _ A is led out to be used as an access end of a touch key, a sensing capacitor C0 between the touch key and the ground is connected to the inverting input end INN of the first comparator COMP _ A, when the touch key is touched by a finger, a touch capacitor Ct between the touch key and the finger is connected to the inverting input end INN of the first comparator COMP _ A, a feedback capacitor Cff and a third control switch SW3 are connected in parallel between the inverting input end INN of the first comparator COMP _ A and an output end OUTA of the first comparator COMP _ A, a third reference voltage VC is connected to the inverting input end of the second comparator COMP _ B; when the digital processing circuit detects that the output terminal OUTB of the second comparator COMP _ B is at a high level in two consecutive clock cycles, the digital processing circuit outputs a high level, which indicates that the touch key has been touched by a finger.
Specifically, as shown in fig. 3, the CLOCK generating circuit CLOCK includes an oscillator circuit OSC and a D flip-flop frequency dividing circuit, an output terminal of the oscillator circuit OSC is connected to an input terminal of the D flip-flop frequency dividing circuit, and an output terminal of the D flip-flop frequency dividing circuit is used as an output terminal of the CLOCK generating circuit CLOCK. The oscillator circuit OSC can generate a high-pulse square wave signal as a vibration source of the CLOCK generating circuit CLOCK, and then outputs a square wave signal with a certain duty ratio through the D flip-flop frequency dividing circuit. The D flip-flop frequency divider circuit can output a square wave signal having a duty ratio of 50%, and thus, has high and low level signals having the same width in one CLOCK cycle of the CLOCK generation circuit CLOCK. When the CLOCK generation circuit CLOCK output CLK is at a high level, the inverter output CLKB is at a low level, at this time, the first control switch SW1 and the third control switch SW3 are kept at an on state, and the second control switch SW2 is kept at an off state; when the CLOCK generation circuit CLOCK output CLK is low and the inverter output CLKB is high, the first control switch SW1 and the third control switch SW3 maintain an off state and the second control switch SW2 maintains an on state.
Further, the first to third control switches may be implemented by using a single PMOS transistor or NMOS transistor, where a gate of the PMOS transistor or NMOS transistor is used as a control end of the first to third control switches, and a source and a drain of the PMOS transistor or NMOS transistor are used as two ends of the first to third control switches. The first to third control switches can also be realized by adopting a CMOS transmission gate formed by connecting an NMOS tube and a PMOS tube in parallel, the input end and the output end of the CMOS transmission gate are used as the two ends of the first to third control switches, and the C end of the CMOS transmission gate is used as the control end of the first to third control switches, so that the complementary electrical characteristics of the NMOS tube and the PMOS tube are fully utilized, an input signal with a low value of the on-state resistance can be obtained no matter the control switch transmits a high level or a low level, and the signal can be effectively transmitted to the output end under various input levels.
As shown IN fig. 4, the digital processing circuit includes a detection module and a counting module, an input terminal IN of the detection module is connected to an output terminal OUTB of the second comparator COMP _ B, an output terminal of the detection module is connected to an input terminal of the counting module, an output terminal OUT of the counting module is led OUT as an output terminal OUT of the digital processing circuit, and CLOCK control terminals CLK of the detection module and the counting module are both connected to an output terminal of the CLOCK generation circuit CLOCK. The detection module starts the level of an input signal of the detection input end IN when a clock signal input by the clock control end CLK is high level, and outputs a high level by the output end of the detection module when the input signal is detected to be high level and keeps the next detection period; and when the detection module outputs a high level to the input end of the counting module, the counting module starts to count the clock signal of the clock control end to be a high level, and when the count is 2, the output end of the counting module outputs a high level and keeps the high level until the detection module outputs a low level (when the detection module inputs a low level, the detection module outputs a low level).
Further, in order to enable the detection circuit to be in a better detection state and to extend the capacitance detection range of the detection circuit, the voltage values of the first to third reference voltages in the circuit are set to be sequentially increased, that is, the voltage value of the first reference voltage VA is smaller than the voltage value of the second reference voltage VB, and the voltage value of the second reference voltage VB is smaller than the voltage value of the third reference voltage VC.
In addition, in order to improve the anti-interference capability of the detection circuit, the voltage value of the third reference voltage VC is set between the output voltage value of the first comparator COMP _ a when the capacitive touch key is not touched and the output voltage value of the first comparator COMP _ a when the capacitive touch key is touched by a finger. Preferably, an average value of the output voltage value of the first comparator COMP _ a when the capacitive touch key is not touched and the output voltage value of the first comparator COMP _ a when the capacitive touch key is touched by a finger is selected as the voltage value of the third reference voltage VC.
Furthermore, in order to widen the capacitance detection range of the detection circuit, the value range of the feedback capacitance Cf is selected to be 1pF to 100pF, so that the capacitance detection range of the circuit can reach 1pF at minimum.
The working principle of the detection circuit of the preferred embodiment is as follows:
in one cycle of the CLOCK generation circuit CLOCK, the detection circuit goes through two stages, namely a circuit self-calibration stage and a capacitance detection stage, wherein,
(1) a circuit self-correction stage: when the CLOCK generation circuit CLOCK output CLK is high, the first control switch SW1 and the third control switch SW3 are kept in an on state, and the second control switch SW2 is kept in an off state; at this time, the voltage of the non-inverting input terminal INP of the first comparator COMP _ a is equal to the voltage of the first reference voltage VA, the output terminal OUTA of the first comparator COMP _ a and the inverting input terminal thereof are shorted together, so that the first comparator COMP _ a operates in the following operating state, and then:
VINN=VOUTA=VINP=VA
at this time, the voltage difference applied across the feedback capacitor Cf is 0V.
The input voltages of the non-inverting input terminal and the inverting input terminal of the second comparator COMP _ B are a first reference voltage VA and a third reference voltage VC, respectively, and since the first reference voltage VA is smaller than the third reference voltage VC, the output terminal OUTB of the second comparator COMP _ B outputs a low level signal, and the digital processing circuit outputs a low level after detecting the low level signal.
(2) And a capacitance detection stage: when the CLOCK generation circuit CLOCK output CLK is low, the first control switch SW1 and the third control switch SW3 are kept in an off state, and the second control switch SW2 is kept in an on state; at this time, the voltage of the non-inverting input terminal INP of the first comparator COMP _ a is equal to the voltage value of the second reference voltage VB, and according to the theory of virtual short circuit between the two input terminals of the general comparator, the voltage of the inverting input terminal INN of the first comparator COMP _ a is adjusted by the feedback loop to be equal to the voltage of the non-inverting input terminal of the first comparator COMP _ a. Namely:
VINN= VINP= VB
therefore, when the capacitive touch key is not touched by a finger, the capacitance value of the input end of the touch key is the sensing capacitor C0 between the touch key and the ground, and the amount of charge required for the voltage value of the sensing capacitor C0 to rise from the voltage value of the first reference voltage VA in the circuit self-calibration phase to the voltage value of the second reference voltage VB in the capacitance detection phase is as follows:
Q=（VB-VA）*C0
as can be seen from the circuit structure, the required charge amount is provided by the feedback capacitor Cf, and therefore, the voltage difference between the two ends of the feedback capacitor Cf is changed from 0V to:
Vf=Q/Cf=（VB-VA）*C0/Cf
at this time, the output voltage OUTA of the first comparator COMP _ a is:
VOUTA=VINN+Vf=VB+（VB-VA）*C0/Cf
when a finger touches the capacitive touch key, the capacitance value at the input end of the touch key is the sum of the inductive capacitance C0 between the touch key and the ground and the touch capacitance between the touch key and the finger, and the amount of electric charge required for the voltage value at the input end of the touch key to be increased from the voltage value of the first reference voltage VA in the circuit self-correction phase to the voltage value of the second reference voltage VB in the capacitance detection phase is as follows:
Q’=（VB-VA）*(C0+Ct)
as can be seen from the circuit structure, the required charge amount is provided by the feedback capacitor Cf, and therefore, the voltage difference between the two ends of the feedback capacitor Cf is changed from 0V to:
Vf’=Q’/Cf=（VB-VA）*(C0+Ct)/Cf
at this time, the output voltage OUTA of the first comparator COMP _ a is:
VOUTA’=VINN+Vf=VB+（VB-VA）*(C0+Ct)/Cf
from VOUTA<VC<VOUTAIt can be known that the voltage value of the third reference voltage VC ranges from
VB+（VB-VA）*C0/Cf<VC<VB+（VB-VA）*(C0+Ct)/Cf
In summary, when the touch button is not triggered by a finger, the voltage of the output terminal OUTA of the first comparator COMP _ a is always less than the voltage of the third reference voltage VC, so that the voltage of the output terminal OUTB of the second comparator COMP _ B is always at a low level, so that the output terminal of the digital processing circuit outputs a low level, and a corresponding simulation result is shown in fig. 5.
When the touch key is triggered by a finger, the voltage of the output terminal OUTA of the first comparator COMP _ a is greater than the voltage value of the third reference voltage VC at each capacitance detection stage, so that the voltage value of the output terminal OUTB of the second comparator COMP _ B is a high-level signal at each capacitance detection stage, and after the detection processing of the digital processing circuit, the digital processing circuit outputs a high level after two consecutive capacitance detection stages, and the corresponding simulation result is as shown in fig. 6.
The utility model provides a capacitanc touch button detection circuitry's simple structure is reliable, easily realize, detection performance parameter to capacitanc touch button is reliable and stable, the interference killing feature of circuit is strong, can effectively prevent the spurious triggering and the electromagnetic interference of capacitanc touch button, and set up to rising in proper order through first to third reference voltage who uses in the circuit, and set up third reference voltage VC when capacitanc touch button is not touched between the output voltage value of first comparator COMP _ A and capacitanc touch button when being pointed the touch output voltage value of first comparator COMP _ A, further combine feedback electric capacity Cf's reasonable value range 1pF ~ 100pF, make the electric capacity detection range minimum of circuit can reach 1pF, the electric capacity detection range of electric capacity has been improved greatly.
The technical means disclosed by the scheme of the present invention is not limited to the technical means disclosed by the above embodiments, but also includes the technical scheme formed by the arbitrary combination of the above technical features. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also considered as the protection scope of the present invention.
Claims (9)
1. Capacitive touch key detection circuitry, its characterized in that: the output end of the clock generating circuit is connected with the input end of the inverter, the control ends of the first control switch and the third control switch are connected with the output end of the clock generating circuit, the control end of the second control switch is connected with the output end of the inverter, the output end of the first comparator is connected with the positive phase input end of the second comparator, the output end of the second comparator is connected with the input end of the digital processing circuit, the output end of the digital processing circuit is led out to be used as the output end of the detection circuit, a clock signal port of the digital processing circuit is connected with the output end of the clock generating circuit, the positive phase input end of the first comparator is connected with a first reference voltage through the first control switch, the positive phase input end of the first comparator is connected with a second reference voltage through the second control switch, leading out an inverting input end of a first comparator as an access end of a touch key, accessing an induction capacitor between the touch key and the ground at the inverting input end of the first comparator, accessing a feedback capacitor and a third control switch in parallel between the inverting input end of the first comparator and an output end of the first comparator, and accessing a third reference voltage at the inverting input end of a second comparator; when the digital processing circuit detects that the output end of the second comparator is at a high level in two continuous clock cycles, the digital processing circuit outputs the high level to indicate that the touch key is touched by a finger.
2. The capacitive touch key detection circuit of claim 1, wherein the clock generation circuit comprises an oscillation circuit and a D-flip-flop frequency divider circuit, an output terminal of the oscillation circuit is connected to an input terminal of the D-flip-flop frequency divider circuit, an output terminal of the D-flip-flop frequency divider circuit serves as an output terminal of the clock generation circuit, and the D-flip-flop frequency divider circuit outputs a square wave signal having a duty cycle of 50%.
3. The capacitive touch key detection circuit of claim 2, wherein when the clock generation circuit outputs a high level, the first and third control switches remain on, and the second control switch remains off; when the clock generation circuit outputs a low level, the first and third control switches are kept in an off state, and the second control switch is kept in an on state.
4. The capacitive touch key detection circuit of claim 3, wherein the voltage values of the first to third reference voltages increase in sequence, i.e., the voltage value of the first reference voltage is less than the voltage value of the second reference voltage, which is less than the voltage value of the third reference voltage.
5. The capacitive touch key detection circuit according to claim 4, wherein the digital processing circuit comprises a detection module and a counting module, an input terminal of the detection module is connected to an output terminal of the second comparator, an output terminal of the detection module is connected to an input terminal of the counting module, an output terminal of the counting module is led out as an output terminal of the digital processing circuit, clock control terminals of the detection module and the counting module are both connected to an output terminal of the clock generation circuit, the detection module detects a level of the input signal when the clock signal is at a high level, and outputs the high level when the input signal is detected to be at the high level, and keeps the level at a next detection period; when the detection module outputs a high level, the counting module starts to count the clock signal, and when the count reaches 2, the counting module outputs the high level and keeps the high level until the detection module outputs a low level.
6. The capacitive touch key detect circuit of claim 5, wherein the feedback capacitance has a value in the range of 1pF to 100pF, such that the capacitance detection range of the circuit can be as small as 1 pF.
7. The capacitive touch key detection circuit of claim 6 wherein the third reference voltage has a voltage value set between the output voltage value of the first comparator when the capacitive touch key is not touched and the output voltage value of the first comparator when the capacitive touch key is touched by a finger.
8. The capacitive touch key detection circuit according to any one of claims 1-7, wherein the first to third control switches are implemented by using a single PMOS transistor or NMOS transistor, and the gate of the PMOS transistor or NMOS transistor is used as the control terminal of the first to third control switches.
9. The capacitive touch key detection circuit according to any one of claims 1-7, wherein the first to third control switches are implemented using CMOS transmission gates formed by connecting an NMOS transistor and a PMOS transistor in parallel.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176922A (en) * | 2019-06-21 | 2019-08-27 | 苏州锴威特半导体有限公司 | Capacitance type touch key detection circuit |
| CN111965431A (en) * | 2020-10-23 | 2020-11-20 | 杭州晶华微电子有限公司 | Semiconductor device with a plurality of semiconductor chips |
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2019
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110176922A (en) * | 2019-06-21 | 2019-08-27 | 苏州锴威特半导体有限公司 | Capacitance type touch key detection circuit |
| CN110176922B (en) * | 2019-06-21 | 2024-02-20 | 苏州锴威特半导体股份有限公司 | Capacitive touch key detection circuit |
| CN111965431A (en) * | 2020-10-23 | 2020-11-20 | 杭州晶华微电子有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN111965431B (en) * | 2020-10-23 | 2020-12-25 | 杭州晶华微电子有限公司 | Semiconductor device with a plurality of semiconductor chips |
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