CN209979794U

CN209979794U - Multichannel short circuit detection circuit based on FPGA

Info

Publication number: CN209979794U
Application number: CN201920501793.3U
Authority: CN
Inventors: 霍风祥; 李涛; 李鹏飞; 葛亚山
Original assignee: Beijing Jinghanyu Electronic Engineering Technology Co Ltd
Current assignee: Beijing Jinghanyu Electronic Engineering Technology Co Ltd
Priority date: 2019-04-15
Filing date: 2019-04-15
Publication date: 2020-01-21
Anticipated expiration: 2029-04-15

Abstract

The application relates to a multichannel short circuit detection circuitry based on FPGA includes: the system comprises an FPGA main control chip, an FPGA configuration chip, a crystal oscillator chip, a short circuit condition diagnosis indicating circuit, a diode protection circuit and a detection interface circuit. The FPGA main control chip sends a detection electric signal to each signal output pin in sequence, simultaneously detects a feedback electric signal of the signal input pin corresponding to the signal output pin, if no short circuit occurs in an external detected signal accessed by the pin of the detection interface circuit, the feedback electric signal is the same as the level of the detection electric signal, and if the short circuit occurs in the external detected signal accessed by the pin of the detection interface circuit, the feedback electric signal is different from the level of the detection electric signal. If the FPGA main control chip detects that the feedback electric signal is different from the detection electric signal level, the FPGA main control chip controls the signal output pin to continuously output the electric signal, and keeps the light emitting diode corresponding to the signal output pin normally bright, so that whether a short circuit occurs in an external detected signal is judged.

Description

Multichannel short circuit detection circuit based on FPGA

Technical Field

The application relates to the technical field of circuit detection, in particular to a multichannel short circuit detection circuit based on an FPGA.

Background

In the prior art, whether the short circuit condition exists between a plurality of channels is detected, generally, whether the short circuit condition exists between two pins is detected in sequence by using a universal meter, if 2 channels are detected, whether the short circuit condition exists can be judged by using the universal meter to test once, but 3 times of detection is needed when 3 channels are detected, 6 times of detection is needed when 4 channels are detected, 2016 times of detection is needed if 64 channels are detected, therefore, when a plurality of channels are detected, if the previous universal meter is used for testing, the test times are increased along with the increase of the channel numbers, the test times are rapidly increased, the test efficiency is rapidly reduced, and the workload is large. It is also possible to use integrated digital test equipment for testing, but special test programs need to be developed, which are costly and not portable.

SUMMERY OF THE UTILITY MODEL

In order to overcome the problems in the related art at least to a certain extent, the application provides a multi-channel short circuit detection circuit based on an FPGA.

The scheme of the application is as follows:

a multichannel short circuit detection circuit based on FPGA includes:

the system comprises an FPGA main control chip, an FPGA configuration chip, a crystal oscillator chip, a short circuit condition diagnosis indication circuit, a diode protection circuit and a detection interface circuit; the FPGA main control chip comprises: the device comprises a program configuration pin, a clock configuration pin, a plurality of signal output pins and a plurality of signal input pins, wherein each signal output pin corresponds to each signal input pin one to one;

the FPGA configuration chip is electrically connected with a program configuration pin of the FPGA main control chip and is used for loading a program to the FPGA main control chip when the FPGA main control chip is powered on every time;

the crystal oscillator chip is electrically connected with a clock configuration pin of the FPGA main control chip and is used for providing clock frequency for the FPGA main control chip;

the FPGA main control chip is used for generating a detection electric signal according to a program provided by the FPGA configuration chip and the clock frequency provided by the crystal oscillator chip;

the detection interface circuit comprises a plurality of pins, and each pin is used for accessing one path of detected signals in a plurality of paths of external detected signals;

the diode protection circuit includes: a plurality of Schottky diodes; anodes of the Schottky diodes are connected with the signal output pins of the FPGA main control chip one by one; the cathodes of the Schottky diodes are connected with the pins of the detection interface circuit one by one, and the cathodes of the Schottky diodes are connected with the signal input pins of the FPGA main control chip one by one;

the short circuit condition diagnostic indication circuit includes: a plurality of light emitting diodes and a plurality of first pull-down resistors; the anodes of the light emitting diodes are connected with the pins of the detection interface circuit one by one, and the anodes of the light emitting diodes are connected with the signal input pins of the FPGA main control chip one by one; cathodes of the plurality of light emitting diodes are connected with one end of the plurality of first pull-down resistors one by one; the other end of the first pull-down resistors is grounded.

Preferably, in an implementation manner of the present application, the method further includes:

JTAG interface, is used for debugging and downloading the procedure;

one end of the JTAG interface is connected with the FPGA configuration chip, and the other end of the JTAG interface is connected with a program configuration pin of the FPGA main control chip.

the FPGA configuration mode selection circuit is used for determining the working configuration mode of the FPGA main control chip;

the FPGA main control chip further comprises: a mode configuration pin;

the FPGA configuration mode selection circuit is connected with a mode configuration pin of the FPGA main control chip and is used for configuring the FPGA main control chip into a master-slave mode.

the FPGA pull-up resistor control circuit is used for controlling the signal output pin and the signal input pin of the FPGA main control chip to be pulled up;

the FPGA main control chip further comprises: pulling up the configuration pins;

the FPGA pull-up resistance control circuit is connected with a pull-up configuration pin of the FPGA main control chip and is used for controlling the pull-up of a signal output pin and a signal input pin of the FPGA main control chip in the configuration process of the FPGA main control chip.

Preferably, in an implementation manner of the present application, the method further includes: the reset circuit is used for reloading a configuration program for the FPGA main control chip;

the FPGA main control chip further comprises: resetting the configuration pin;

the reset circuit is provided with a reset circuit switch and a first contact and a second contact which are in contact with the reset circuit switch, and the reset circuit switch is used for controlling the connection or disconnection of the reset circuit;

the first contact is grounded;

the second contact is connected with a reset configuration pin of the FPGA main control chip; the second contact is also connected with the FPGA configuration chip.

Preferably, in an implementation manner of the present application, the method further includes: the key circuit is used for starting or closing a test program of the FPGA main control chip;

the key circuit includes:

the circuit comprises a first branch circuit, a second branch circuit and a third branch circuit, wherein the first branch circuit, the second branch circuit and the third branch circuit are mutually connected in parallel;

the FPGA main control chip further comprises: a first key configuration pin and a second key configuration pin;

the first branch circuit is provided with a first branch circuit switch, a third contact and a fourth contact, the third contact and the fourth contact are in contact with the first branch circuit switch, the first branch circuit switch is used for controlling connection or disconnection of the first branch circuit, the third contact is grounded, and the fourth contact is connected with a first key configuration pin of the FPGA main control chip; when the first branch is communicated, the FPGA main control chip starts a test program;

a second branch switch, a fifth contact and a sixth contact which are in contact with the second branch switch are arranged on the second branch, the second branch switch is used for controlling the connection or disconnection of the second branch, the fifth contact is grounded, and the sixth contact is connected with a second key configuration pin of the FPGA main control chip; when the second branch is communicated, the FPGA main control chip closes the test program;

and a third branch switch, a seventh contact and an eighth contact which are in contact with the third branch switch are arranged on the third branch, and the third branch switch is used for controlling the connection or disconnection of the third branch.

Preferably, in an implementation manner of the present application, the method further includes: the power supply module is used for supplying power to the FPGA main control chip and the FPGA configuration chip;

the power supply module comprises a hardware interface, a self-locking key and a plurality of voltage stabilizing chips;

the FPGA main control chip comprises: a first power supply pin, a second power supply pin and a third power supply pin;

the FPGA configuration chip comprises: a first power supply pin and a second power supply pin;

the power module is introduced with a power supply through the hardware interface and is respectively connected with a first voltage stabilizing chip, a second voltage stabilizing chip, a third voltage stabilizing chip and a fourth voltage stabilizing chip through the self-locking key;

the first voltage stabilizing chip is connected with a first power supply pin and a second power supply pin of the FPGA configuration chip; the first power supply pin is also connected with the FPGA main control chip;

the second voltage stabilizing chip is connected with a first power supply pin of the FPGA main control chip;

the third voltage stabilizing chip is connected with a second power supply pin of the FPGA main control chip;

and the fourth voltage stabilizing chip is connected with a third power supply pin of the FPGA main control chip.

Preferably, in an implementation manner of the present application, the method further includes: the power supply indicating circuit is used for indicating a power supply switch;

the power supply indicating circuit comprises a first indicating lamp;

one end of the first indicator light is connected into the power supply module, and the other end of the first indicator light is grounded.

Preferably, in an implementation manner of the present application, the method further includes: the operation state and result display circuit is used for reflecting the operation state and the detection result of the detection circuit;

the operating status and result display circuit includes:

the fourth branch, the fifth branch and the sixth branch are mutually connected in parallel;

a second indicator light is arranged on the fourth branch, one end of the second indicator light is connected with a third power supply pin of the FPGA main control chip through a sixteenth resistor, and the other end of the second indicator light is grounded;

a third indicator light is arranged on the fifth branch, one end of the third indicator light is connected with a third power supply pin of the FPGA main control chip through a seventeenth resistor, and the other end of the third indicator light is grounded;

and a fourth indicator light is arranged on the sixth branch, one end of the fourth indicator light is connected with a third power supply pin of the FPGA main control chip through an eighteenth resistor, and the other end of the fourth indicator light is grounded.

Preferably, in an implementation manner of the present application, the method further includes: a plurality of second pull-down resistors;

the first ends of the second pull-down resistors are connected with the signal input pins of the FPGA main control chip one by one, and the second ends of the second pull-down resistors are grounded.

The technical scheme provided by the application can comprise the following beneficial effects:

multichannel short circuit detection circuitry based on FPGA in this application includes: the system comprises an FPGA main control chip, an FPGA configuration chip, a crystal oscillator chip, a short circuit condition diagnosis indication circuit, a diode protection circuit and a detection interface circuit; when the FPGA main control chip is used, the FPGA main control chips with the corresponding pin number can be selected according to the channel number of the external tested signals, and if the channel number of the external tested signals is 64, the FPGA main control chips with the signal input pin number and the signal output pin number larger than or equal to 64 are selected. The FPGA configuration chip is used for loading a program to the FPGA main control chip when the FPGA main control chip is powered on every time, the crystal oscillator chip is used for providing clock frequency to the FPGA main control chip, the FPGA main control chip generates detection electric signals according to the program provided by the FPGA configuration chip and the clock frequency provided by the crystal oscillator chip, the detection electric signals are sequentially sent to each signal output pin, and meanwhile, feedback electric signals of the signal input pins corresponding to the signal output pins are detected. Because the positive pole of schottky diode is connected with the signal output pin of FPGA main control chip, the negative pole is connected with the pin that detects interface circuit, and the negative pole of schottky diode is connected with the signal input pin of FPGA main control chip, it exports the schottky diode to detect the signal of telecommunication through the signal output pin, feed back corresponding signal input pin behind the pin that detects interface circuit, if the external surveyed signal that detects interface circuit's pin access does not have the short circuit and takes place, then this feedback signal of telecommunication is the same with the signal level of detection signal of telecommunication, if the external surveyed signal that detects interface circuit's pin access takes place the short circuit, then this feedback signal of telecommunication is inequality with the signal level of detection signal of telecommunication. The light emitting diodes of the short circuit condition diagnosis indicating circuit can be sequentially lightened when current passes through, and if the FPGA main control chip detects that the feedback electric signal is different from the detection electric signal level, the signal output pin is controlled to continuously output the electric signal, so that the light emitting diodes corresponding to the signal output pin are kept normally lightened, and the external detected signal accessed by the pin of the corresponding detection interface circuit is indicated to be short-circuited.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic circuit diagram of an FPGA-based multi-channel short circuit detection circuit according to an embodiment of the present application;

fig. 2 is a circuit structure diagram of an FPGA main control chip according to an embodiment of the present application;

fig. 3 is a circuit diagram of an FPGA configuration chip according to an embodiment of the present application;

fig. 4 is a circuit structure diagram of a crystal oscillator chip according to an embodiment of the present application;

fig. 5 is a circuit diagram of a part of an FPGA main control chip, a short-circuit condition diagnosis indication circuit, a diode protection circuit, and a detection interface circuit according to an embodiment of the present application;

fig. 6 is a circuit connection diagram and a current flow diagram of a part of the FPGA main control chip, the short-circuit condition diagnosis indication circuit, the diode protection circuit and the detection interface circuit according to an embodiment of the present application;

FIG. 7 is a circuit schematic of an FPGA-based multi-channel short detection circuit according to another embodiment of the present application;

FIG. 8 is a circuit diagram of a JTAG interface provided by another embodiment of the present application;

fig. 9 is a circuit configuration diagram of an FPGA configuration mode selection circuit according to another embodiment of the present application;

FIG. 10 is a circuit block diagram of an FPGA pull-up resistance control circuit according to another embodiment of the present application;

fig. 11 is a circuit configuration diagram of a reset circuit according to another embodiment of the present application;

fig. 12 is a circuit configuration diagram of a key circuit according to another embodiment of the present application;

fig. 13 is a circuit configuration diagram of a power module according to another embodiment of the present application;

FIG. 14 is a circuit block diagram of a power indicator circuit according to another embodiment of the present application;

fig. 15 is a circuit configuration diagram of an operating status and result display circuit according to another embodiment of the present application.

Reference numerals: an FPGA main control chip-1; an FPGA configuration chip-2; a crystal oscillator chip-3; short circuit condition diagnostic indicator circuit-4; diode protection circuit-5; detection interface circuit-6; JTAG interface-7; FPGA configuration mode selection circuit-8; FPGA pull-up resistance control circuit-9; a reset circuit-10; a key circuit-11; a power supply module-12; power indication circuit-13; the operation state and result display circuit-14.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

Fig. 1 is a schematic circuit diagram of a multi-channel short-circuit detection circuit based on an FPGA according to an embodiment of the present application, and referring to fig. 1, the multi-channel short-circuit detection circuit based on the FPGA includes:

the system comprises an FPGA main control chip 1, an FPGA configuration chip 2, a crystal oscillator chip 3, a short circuit condition diagnosis indicating circuit 4, a diode protection circuit 5 and a detection interface circuit 6; the FPGA main control chip 1 includes: the device comprises a program configuration pin, a clock configuration pin, a plurality of signal output pins and a plurality of signal input pins, wherein each signal output pin corresponds to each signal input pin one to one;

the FPGA configuration chip 2 is electrically connected with a program configuration pin of the FPGA main control chip 1 and is used for loading a program to the FPGA main control chip 1 when being powered on every time;

the crystal oscillator chip 3 is electrically connected with a clock configuration pin of the FPGA main control chip 1 and is used for providing clock frequency for the FPGA main control chip 1;

the FPGA main control chip 1 is used for generating a detection electric signal according to a program provided by the FPGA configuration chip 2 and the clock frequency provided by the crystal oscillator chip 3;

the detection interface circuit 6 comprises a plurality of pins, and each pin is used for accessing one tested signal in a plurality of external tested signals;

the diode protection circuit 5 includes: a plurality of Schottky diodes; anodes of the Schottky diodes are connected with the signal output pins of the FPGA main control chip 1 one by one; the cathodes of the plurality of Schottky diodes are connected with the plurality of pins of the detection interface circuit 6 one by one, and the cathodes of the plurality of Schottky diodes are connected with the plurality of signal input pins of the FPGA main control chip 1 one by one;

the short circuit condition diagnosis indication circuit 4 includes: a plurality of light emitting diodes and a plurality of first pull-down resistors; anodes of the light emitting diodes are connected with the pins of the detection interface circuit 6 one by one, and the anodes of the light emitting diodes are connected with the signal input pins of the FPGA main control chip 1 one by one; cathodes of the plurality of light emitting diodes are connected with one end of the plurality of first pull-down resistors one by one; the other ends of the first pull-down resistors are grounded.

Taking a 64-channel short circuit detection circuit as an example, the FPGA main control chip 1 has 64 signal output pins and 64 signal input pins. The circuit structure diagram of the FPGA main control chip 1 refers to fig. 2. The 64-channel short detection circuit can detect an external signal under test that is no larger than 64 channels.

Referring to fig. 3, a circuit structure diagram of the FPGA configuration chip 2 shows that the specific connection relationship between the FPGA configuration chip 2 and the FPGA main control chip 1 is as follows:

the PIN83 of the FPGA main control chip 1 is connected with the PIN13 of the FPGA configuration chip 2;

the PIN92 of the FPGA main control chip 1 is connected with the PIN40 of the FPGA configuration chip 2;

PIN103 of FPGA main control chip 1 is connected with PIN15 of FPGA configuration chip 2;

the PIN104 of the FPGA main control chip 1 is connected with the PIN43 of the FPGA configuration chip 2;

PIN207 of FPGA main control chip 1 is connected with PIN10 of FPGA configuration chip 2;

the PIN159 of the FPGA main control chip 1 is connected with the R67, and the R67 is connected with the PIN7 of the FPGA configuration chip 2;

the PIN160 of the FPGA main control chip 1 is connected with the R66, and the R66 is connected with the PIN5 of the FPGA configuration chip 2;

PIN208 of the FPGA main control chip 1 is connected with R103, and R103 is connected with PIN31 of the FPGA configuration chip 2.

Referring to fig. 4, a circuit structure diagram of the crystal oscillator chip 3 shows that the specific connection relationship between the crystal oscillator chip 3 and the FPGA main control chip 1 is as follows:

and a PIN79 PIN of the FPGA main control chip 1 is connected with a clock output PIN of the crystal oscillator chip 3.

Referring to fig. 5, partial circuit connection diagrams of the FPGA main control chip 1, the short circuit condition diagnosis indication circuit 4, the diode protection circuit 5 and the detection interface circuit 6 are shown, in the diagrams, D1-D64 are schottky diodes of the diode protection circuit 5, and led _ min is a light emitting diode of the detection interface circuit 6. The current flow is shown in figure 6.

Multichannel short circuit detection circuitry based on FPGA in this application includes: the system comprises an FPGA main control chip 1, an FPGA configuration chip 2, a crystal oscillator chip 3, a short circuit condition diagnosis indicating circuit 4, a diode protection circuit 5 and a detection interface circuit 6; when the FPGA main control chip is used, the FPGA main control chip 1 with the corresponding number of pins can be selected according to the number of the channels of the external signals to be tested, and if the number of the channels of the external signals to be tested is 64, the FPGA main control chip 1 with the number of the signal input pins and the number of the signal output pins more than or equal to 64 is selected. The FPGA configuration chip 2 is used for loading programs to the FPGA main control chip 1 when the FPGA main control chip is powered on every time, the crystal oscillator chip 3 is used for providing clock frequency for the FPGA main control chip 1, the FPGA main control chip 1 generates detection electric signals according to the programs provided by the FPGA configuration chip 2 and the clock frequency provided by the crystal oscillator chip 3, sends a detection electric signal to each signal output pin in sequence, and detects feedback electric signals of the signal input pins corresponding to the signal output pins at the same time. Because the positive pole of schottky diode is connected with the signal output pin of FPGA main control chip 1, the negative pole is connected with the pin that detects interface circuit 6, and the negative pole of schottky diode is connected with the signal input pin of FPGA main control chip 1, it exports the schottky diode to detect the signal of telecommunication through the signal output pin, feed back corresponding signal input pin behind the pin that detects interface circuit 6, if the external surveyed signal that the pin that detects interface circuit 6 inserts does not have the short circuit and takes place, then this feedback signal of telecommunication is the same with the signal level of detection telecommunication, if the external surveyed signal that the pin that detects interface circuit 6 inserts takes place the short circuit, then this feedback signal of telecommunication is inequality with the signal level of detection telecommunication. The light emitting diodes of the short circuit condition diagnosis indicating circuit 4 are sequentially lighted when current passes through, and if the FPGA main control chip 1 detects that the feedback electric signal is different from the detection electric signal level, the signal output pin is controlled to continuously output the electric signal, so that the light emitting diode corresponding to the signal output pin is kept normally lighted, and the external detected signal accessed by the pin of the corresponding detection interface circuit 6 is indicated to be short-circuited.

The circuit of the FPGA-based multi-channel short detection circuit in some embodiments, with reference to fig. 7, further includes:

a JTAG interface 7 for debugging and downloading a program;

one end of the JTAG interface 7 is connected with the FPGA configuration chip 2, and the other end of the JTAG interface 7 is connected with a program configuration pin of the FPGA main control chip 1.

Referring to fig. 8, the circuit structure diagram of the JTAG interface 7 shows that the specific connection relationship between the JTAG interface 7 and the FPGA main control chip 1 and the FPGA configuration chip 2 is as follows:

PIN158 of FPGA main control chip 1 connects PIN11 of JTAG interface 7;

the PIN3 of the FPGA configuration chip 2 is connected with the PIN10 of the JTAG interface 7;

the PIN5 of the FPGA configuration chip 2 is connected with the PIN13 of the JTAG interface 7;

the PIN7 of the FPGA configuration chip 2 is connected to the PIN12 of the JTAG interface 7.

The PIN158 is a program configuration PIN of the FPGA main control chip 1.

the FPGA configuration mode selection circuit 8 is used for determining the working configuration mode of the FPGA main control chip 1;

the FPGA master control chip 1 further includes: a mode configuration pin;

the FPGA configuration mode selection circuit 8 is connected with a mode configuration pin of the FPGA main control chip 1 and is used for configuring the FPGA main control chip 1 into a master-slave mode.

Referring to fig. 9, the

PINs

54, 55 and 56 of the FPGA main control chip 1 are connected to the R92 resistor to ground, so as to determine that the working mode of the FPGA main control chip 1 is the master-slave mode. The

PINs

54, 55 and 56 are mode configuration PINs of the FPGA main control chip 1.

FPGAs have multiple configuration modes: the parallel main mode is a mode of adding one FPGA and one EPROM; the master-slave mode can support a PROM to program a plurality of FPGAs; the serial mode can adopt a serial PROM to program the FPGA; the peripheral mode may use the FPGA as a peripheral to the microprocessor, which is programmed by the microprocessor.

the FPGA pull-up resistor control circuit 9 is used for controlling the signal output pin and the signal input pin of the FPGA main control chip 1 to be pulled up;

the FPGA master control chip 1 further includes: pulling up the configuration pins;

the FPGA pull-up resistance control circuit 9 is connected with a pull-up configuration pin of the FPGA main control chip 1 and is used for controlling the pull-up of a signal output pin and a signal input pin of the FPGA main control chip 1 in the configuration process of the FPGA main control chip 1.

Circuit structure diagram of FPGA pull-up resistance control circuit 9 referring to figure 10,

PIN1 of the FPGA pull-up resistor control circuit 9 is connected with R90;

the PIN2 is connected with the PIN207 of the FPGA main control chip 1;

PIN3 is connected to R91, and R91 is connected to ground.

The PIN207 of the FPGA main control chip 1 is a pull-up configuration PIN of the FPGA main control chip 1.

The circuit of the FPGA-based multi-channel short detection circuit in some embodiments, with reference to fig. 7, further includes: the reset circuit 10 is used for reloading the configuration program for the FPGA main control chip 1;

the FPGA master control chip 1 further includes: resetting the configuration pin;

the reset circuit 10 is provided with a reset circuit 10 switch and a first contact and a second contact which are contacted with the reset circuit 10 switch, and the reset circuit 10 switch is used for controlling the connection or disconnection of the reset circuit 10;

the first contact is grounded;

the second contact is connected with a reset configuration pin of the FPGA main control chip 1; the second contact is also connected with the FPGA configuration chip 2.

Circuit configuration of the reset circuit 10 referring to fig. 11:

the PIN1 and the R89 of the reset circuit 10 are connected, and the other end of the R89 is grounded;

PIN2 and R88 of reset circuit 10 are connected;

and PIN2 of reset circuit 10 is connected with PIN207 of FPGA main control chip 1, and is also connected with PIN10 of FPGA configuration chip 2.

The PIN207 of the FPGA main control chip 1 is a reset configuration PIN of the FPGA main control chip 1.

And the reset circuit 10 reloads the configuration program for the FPGA main control chip 1 when the switch of the reset circuit 10 is pressed.

The circuit of the FPGA-based multi-channel short detection circuit in some embodiments, with reference to fig. 7, further includes: the key circuit 11 is used for starting or closing a test program of the FPGA main control chip 1;

the key circuit 11 includes:

the first branch circuit, the second branch circuit and the third branch circuit are mutually connected in parallel;

the FPGA master control chip 1 further includes: a first key configuration pin and a second key configuration pin;

the first branch circuit is provided with a first branch circuit switch, a third contact and a fourth contact which are in contact with the first branch circuit switch, the first branch circuit switch is used for controlling the connection or disconnection of the first branch circuit, the third contact is grounded, and the fourth contact is connected with a first key configuration pin of the FPGA main control chip 1; when the first branch is communicated, the FPGA main control chip 1 starts a test program;

a second branch switch, a fifth contact and a sixth contact which are in contact with the second branch switch are arranged on the second branch, the second branch switch is used for controlling the connection or disconnection of the second branch, the fifth contact is grounded, and the sixth contact is connected with a second key configuration pin of the FPGA main control chip 1; when the second branch is communicated, the FPGA main control chip 1 closes the test program;

and a third branch circuit switch, a seventh contact and an eighth contact which are in contact with the third branch circuit switch are arranged on the third branch circuit, and the third branch circuit switch is used for controlling the connection or disconnection of the third branch circuit.

Circuit configuration of the key circuit 11 referring to fig. 12:

the SW _ START of the key circuit 11 is connected with the PIN149 of the FPGA main control chip 1;

the SW _ RST of the key circuit 11 is connected with the PIN150 of the FPGA main control chip 1;

the SW _ RFU of the key circuit 11 holds the key, temporarily suspended, and is not used.

The PIN149 of the FPGA main control chip 1 is a first key configuration PIN of the FPGA main control chip 1, and the PIN150 of the FPGA main control chip 1 is a second key configuration PIN of the FPGA main control chip 1.

The circuit of the FPGA-based multi-channel short detection circuit in some embodiments, with reference to fig. 7, further includes: the power supply module 12 is used for supplying power to the FPGA main control chip 1 and the FPGA configuration chip 2;

the power module 12 comprises a hardware interface, a self-locking key and a plurality of voltage stabilizing chips;

the FPGA main control chip 1 includes: a first power supply pin, a second power supply pin and a third power supply pin;

the FPGA configuration chip 2 includes: a first power supply pin and a second power supply pin;

the power module 12 introduces a power supply through a hardware interface and is respectively connected with a first voltage stabilizing chip, a second voltage stabilizing chip, a third voltage stabilizing chip and a fourth voltage stabilizing chip through a self-locking key;

the first voltage stabilizing chip is connected with a first power supply pin and a second power supply pin of the FPGA configuration chip 2; the first power supply pin of the FPGA main control chip 1 is also connected;

the second voltage stabilizing chip is connected with a first power supply pin of the FPGA main control chip 1;

the third voltage stabilizing chip is connected with a second power supply pin of the FPGA main control chip 1;

and the fourth voltage stabilizing chip is connected with a third power supply pin of the FPGA main control chip 1.

Circuit structure of power module 12 referring to fig. 13:

the power module 12 introduces a 5V power supply through the hardware interface of DC-2.1. Is connected to ASM117-3.3, ASM117-2.5, ASM117-1.8 and ASM117-1.2 through a self-locking key.

ASM117-3.3 is the first voltage stabilization chip, and ASM117-3.3 is connected with VCCO and VCCINT pins of FPGA configuration chip 2 through short cap 72; the ASM117-3.3 is also connected with a VCCIO4_7 pin of the FPGA main control chip 1 through a short cap 3.3.

The ASM117-2.5 is a second voltage stabilizing chip, the ASM117-2.5 is connected with R71 through a short-circuit cap 69, and R71 is connected with R72 and is grounded; the ASM117-2.5 is also connected with a VCCIO4_7 pin of the FPGA main control chip 1 through a short cap 2.5.

ASM117-1.8 is the third voltage stabilization chip, and ASM117-1.8 is connected with a short circuit cap VCC1.8_ TEST through a short circuit cap 70; the other end of the short cap VCC1.8_ TEST is connected with VCCIO _0_3 pin of FPGA.

The ASM117_1.2 is the fourth voltage stabilizing chip, and the ASM117_1.2 is connected to the VCCINT pin of the FPGA main control chip 1 through the shorting cap 71.

The first power supply pin of the FPGA main control chip 1 is a VCCIO4_7 pin of the FPGA main control chip 1, the first power supply pin of the FPGA main control chip 1 is a VCCIO _0_3 pin of the FPGA main control chip 1, and the third power supply pin of the FPGA main control chip 1 is a VCCINT pin of the FPGA main control chip 1.

The first power supply pin of the FPGA configuration chip 2 is the VCCO pin of the FPGA configuration chip 2, and the second power supply pin of the FPGA configuration chip 2 is the VCCINT pin of the FPGA configuration chip 2.

The jump cap is used as a lead, and voltage is conveniently measured during development.

The actual production of the finished product can be ignored.

The circuit of the FPGA-based multi-channel short detection circuit in some embodiments, with reference to fig. 7, further includes: a power supply indicating circuit 13 for indicating a power supply switch;

the power supply indicating circuit 13 includes a first indicator light;

one end of the first indicator light is connected to the power module 12, and the other end is grounded.

The circuit configuration of the power supply instruction circuit 13 is shown in fig. 14.

The circuit of the FPGA-based multi-channel short detection circuit in some embodiments, with reference to fig. 7, further includes: an operation state and result display circuit 14 for reflecting the operation state and the detection result of the detection circuit;

the operating state and result display circuit 14 includes:

a second indicator light is arranged on the fourth branch, one end of the second indicator light is connected with a third power supply pin of the FPGA main control chip 1 through a sixteenth resistor, and the other end of the second indicator light is grounded;

a third indicator light is arranged on the fifth branch, one end of the third indicator light is connected with a third power supply pin of the FPGA main control chip 1 through a seventeenth resistor, and the other end of the third indicator light is grounded;

and a fourth indicator light is arranged on the sixth branch, one end of the fourth indicator light is connected with a third power supply pin of the FPGA main control chip 1 through an eighteenth resistor, and the other end of the fourth indicator light is grounded.

Circuit configuration diagram of the operation state and result display circuit 14 referring to fig. 15:

the circuit comprises three LED lamps, the third indicator light zhishideng is used for indicating that a program runs, the second indicator light FAIL is used for indicating that a test result has a short circuit, and the first indicator light PASS is used for indicating that the test result is normal and is controlled by the FPGA main control chip 1 without the short circuit.

When a program in the FPGA main control chip 1 runs, the FPGA main control chip 1 controls the third indicator light zhishideng to be normally on; when the FPGA main control chip 1 detects that a short circuit occurs, controlling a second indicator light FAIL to be normally on; when the FPGA main control chip 1 does not detect that a short circuit occurs, the first indicator light PASS is controlled to be normally on.

Preferably, the circuit of the FPGA-based multi-channel short circuit detection circuit in some embodiments further includes: a plurality of second pull-down resistors;

the first ends of the second pull-down resistors are connected with the signal input pins of the FPGA main control chip 1 one by one, and the second ends of the second pull-down resistors are grounded.

The signal input pin of the FPGA main control chip 1 is pulled down and grounded through a pull-down resistor, so that the better work of the circuit can be ensured.

Based on the circuit of the multi-channel short-circuit detection circuit based on the FPGA in the above embodiments, the present embodiment provides a preferred circuit of the multi-channel short-circuit detection circuit based on the FPGA.

A circuit of a multi-channel short circuit detection circuit based on an FPGA comprises an FPGA main control chip 1, an FPGA configuration chip 2, a crystal oscillator chip 3, a short circuit condition diagnosis indication circuit 4, a diode protection circuit 5, a detection interface circuit 6, a JTAG interface 7, an FPGA configuration mode selection circuit 8, an FPGA pull-up resistor control circuit 9, a reset circuit 10, a key circuit 11, a power module 12, a power indication circuit 13 and an operation state and result display circuit 14.

The functions of the circuits have already been described above and are not described in detail here.

It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.

It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims

1. A multichannel short circuit detection circuit based on FPGA is characterized by comprising:

2. The detection circuit of claim 1, further comprising:

JTAG interface, is used for debugging and downloading the procedure;

3. The detection circuit of claim 1, further comprising:

the FPGA main control chip further comprises: a mode configuration pin;

4. The detection circuit of claim 3, further comprising:

5. The detection circuit of claim 1, further comprising: the reset circuit is used for reloading a configuration program for the FPGA main control chip;

the FPGA main control chip further comprises: resetting the configuration pin;

the first contact is grounded;

6. The detection circuit of claim 1, further comprising: the key circuit is used for starting or closing a test program of the FPGA main control chip;

the key circuit includes:

7. The detection circuit of claim 1, further comprising: the power supply module is used for supplying power to the FPGA main control chip and the FPGA configuration chip;

8. The detection circuit of claim 7, further comprising: the power supply indicating circuit is used for indicating a power supply switch;

the power supply indicating circuit comprises a first indicating lamp;

9. The detection circuit of claim 1, further comprising: the operation state and result display circuit is used for reflecting the operation state and the detection result of the detection circuit;

the operating status and result display circuit includes:

10. The detection circuit of claim 1, further comprising: a plurality of second pull-down resistors;