CN209979709U - PXIE framework-based power card - Google Patents
PXIE framework-based power card Download PDFInfo
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- CN209979709U CN209979709U CN201920481012.9U CN201920481012U CN209979709U CN 209979709 U CN209979709 U CN 209979709U CN 201920481012 U CN201920481012 U CN 201920481012U CN 209979709 U CN209979709 U CN 209979709U
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Abstract
The utility model discloses a power card based on PXIE framework, including analog-to-digital converter unit, a plurality of DPS chip unit, back panel connector unit, controller unit, DUT connector unit, the controller unit with analog-to-digital converter unit electric connection, analog-to-digital converter unit converts analog signal into digital signal transmission extremely the controller unit, every DPS chip unit respectively with controller unit electric connection, every the output of DPS chip unit connect in parallel and with analog-to-digital converter unit's input electric connection. The utility model discloses a power card based on PXIE framework, it has excessive pressure, overflows, the clamp protect function, can use power supply in the chip test, characteristics such as the dynamic electric current of test chip.
Description
Technical Field
The utility model belongs to the power card field, concretely relates to power card based on PXIE (PXI EXPRESS) framework.
Background
In a chip development test system, a power supply part is a test item which is of great interest in reliability tests, and in the reliability tests of the power supply part, power supply tolerance, weak points of a chip power supply and the like are generally of great interest. In order to improve the reliability of the system, it is often necessary to perform a reliability test on the electronic product, so as to verify whether the product has reliability and stability under extreme working conditions. Therefore, in the research and development test stage in the industry, the reliability of the system is usually required to be tested, specifically, the single board can be biased, and the sensitivity of the system to power supply fluctuation and the reliability of the system in the power supply aspect are verified by reducing the power supply voltage of the chip.
The test scheme has the following disadvantages:
1. the reliability test cannot be carried out on the chip power supply independently;
2. the overall reliability of the system to the power supply cannot be guaranteed.
SUMMERY OF THE UTILITY MODEL
The utility model discloses to prior art's situation, overcome above-mentioned defect, provide a power card based on PXIE framework.
The utility model discloses a main aim at provides a power card based on PXIE framework, it has multichannel power channel, and every power of the same kind can independently program, can merge a passageway by the multichannel and provide functions such as heavy current.
Another object of the utility model is to provide a power card based on PXIE framework, it has excessive pressure, overflows, the clamp protect function, can be in chip test mains operated, can also test chip dynamic current simultaneously.
In order to reach above purpose, the utility model provides a power card based on PXIE framework, including analog to digital converter unit, a plurality of DPS unit, power card and backplate electric connection are used for testing the chip performance, include:
backplane connector unit, controller unit, analog-to-digital converter unit, a plurality of DPS chip units, DUT connector unit, wherein:
the controller unit is electrically connected with the analog-to-digital converter unit, the analog-to-digital converter unit converts an analog signal into a digital signal and transmits the digital signal to the controller unit, each DPS chip unit is electrically connected with the controller unit, and the output end of each DPS chip unit is connected in parallel and is electrically connected with the input end of the analog-to-digital converter;
one end of each DPS chip unit is electrically connected with the corresponding end of the DUT connector unit, and one end of the DUT connector unit, which is far away from the DPS chip unit, is electrically connected with one end of the test chip;
one end of the backplane connector unit is electrically connected with one end of the controller unit, and one end of the backplane connector unit, which is far away from the controller unit, is electrically connected with one end of the backplane.
As a further preferable aspect of the above technical solution, the backplane connector unit includes an XJ3 region connector and an XJ4 region connector, the XJ3 region connector and the XJ4 region connector being electrically connected, wherein:
the pins A, B, E, F, A, B, C, D, E, F of the XJ area connector are respectively electrically connected with capacitors C606, C612, C607, C613, C608, C609, C610, C611, C617, C618, C619, C620, C621, C622, C623, C624, C625, C626, C149, the capacitors C606, C612, C607, C613, C608, C609, C610, C611, C617, C618, C619, C620, C621, C622, C623, C624, C625, C626, C149 are far away from the pins A, B, E, F, A, B, C, D, E, F, E, F, and F pins of the XJ area connector are respectively electrically connected with the parallel pins A, B, A, B, E, F, A, B, F, and A, the B4 pin of the XJ3 area connector is connected with a power supply through a pull-up resistor R423, the B4 pin is used for an open-drain output, and the pull-up resistor R423 provides a current channel for the open-drain output;
the pins C4, D4 and E4 of the XJ4 area connector are connected to one end of a fuse in parallel, capacitors C614-C616 are connected to one end of the fuse far away from the pins C4, D4 and E4 in parallel, the capacitors C614-C616 are connected to the ground far away from the parallel end of the fuse, the fuse provides overcurrent protection for the backboard, the pins A1-E1 of the XJ4 area connector are respectively connected with a power supply through pull-up resistors R401, R402, R404, R405 and R403, the pins A1-E1 are used for open-drain output, the pull-up resistors R401-R405 provide current channels for the open-drain output, the pin E6 of the XJ4 area connector is electrically connected with a terminating resistor R407, and the terminating resistor R407 is used for reducing signal reflection.
As a further preferable technical solution of the above technical solution, the analog-to-digital converter unit is an AD7608BSTZ chip of analog device.
As a further preferable technical solution of the above technical solution, the pins 49-63 of the AD7608BSTZ chip are electrically connected with the pins of each DPS chip unit, analog signals output by each DPS chip unit enter the AD7608BSTZ chip through the pins 49-63, respectively, and the AD7608BSTZ chip converts the analog signals into digital signals and transmits the digital signals to the controller unit through the pins 24 and 25 of the AD7608BSTZ chip.
As a further preferable mode of the above mode, each of the DPS chip units has a register therein, and the controller unit accesses the register by signal transmission from the register to inquire about the operating state of the DPS chip unit.
As a further preferable technical solution of the above technical solution, the controller unit is a Xilinx Artix7 series FPGA chip and a peripheral circuit thereof.
Drawings
Fig. 1 is a schematic structural diagram of a PXIE-architecture-based power card according to a first preferred embodiment of the present invention.
Fig. 2 is a circuit diagram of an XJ3 area connector of a PXIE-based power card according to a first preferred embodiment of the present invention.
Fig. 3 is a circuit diagram of an XJ4 area connector of a PXIE-based power card according to a first preferred embodiment of the present invention.
Fig. 4 is a circuit diagram of an analog-to-digital converter unit of a PXIE-based power card according to a first preferred embodiment of the present invention.
The reference numerals include: 1. a backplane connector unit; 2. a controller unit; 3. an analog-to-digital converter unit; 4. a DUT connector unit; 5. a DPS chip unit 1; 6. a DPS chip unit 2; 7. a DPS chip unit 3; 8. a DPS chip unit 4; 9. a DPS chip unit 5; 10. a DPS chip unit 6; 11. a DPS chip unit 7; 12. DPS chip unit 8.
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents and other technical solutions without departing from the spirit and scope of the invention.
In this preferred embodiment of the present invention, it should be noted by those skilled in the art that the present invention relates to a back plate, which comprises: PXI EXPRESS chassis and its components, XJ3 area connector, XJ4 area connector, and PCI EXPRESS serial interface are all prior art.
It should be noted that the controller unit 2 is electrically connected to the analog-to-digital converter unit 3, the analog-to-digital converter unit 3 converts an analog signal into a digital signal and transmits the digital signal to the controller unit 2, the DPS chip units 5 to 12 are electrically connected to the controller unit 2, and output ends of the DPS chip units 5 to 12 are connected in parallel and electrically connected to an input end of the analog-to-digital converter unit 3;
one end of each of the DPS chip units 5-12 is electrically connected to one end of the DUT connection unit 4, and the other end of the DUT connection unit 4 is electrically connected to one end of the test chip (not shown);
one end of the backplane connector unit 1 is electrically connected to the controller unit 2, and the other end of the backplane connector unit 1 is electrically connected to the backplane (not shown).
Further, the backplane connector unit 1 comprises an XJ3 area connector and its peripheral circuits, and an XJ4 area connector and its peripheral circuits, the XJ3 area connector and the XJ4 area connector being electrically connected, wherein:
the pins A, B, E, F, A, B, C, D, E, F of the XJ area connector are respectively electrically connected with capacitors C606, C612, C607, C613, C608, C609, C610, C611, C617, C618, C619, C620, C621, C622, C623, C624, C625, C626, C149, the capacitors C606, C612, C607, C613, C608, C609, C610, C611, C617, C618, C619, C620, C621, C622, C623, C624, C625, C626, C149 are far away from the pins A, B, E, F, A, B, C, D, E, F, E, F, and F pins of the XJ area connector are respectively electrically connected with the parallel pins A, B, A, B, E, F, A, B, F, and A, the B4 pin of the XJ3 area connector is connected with a power supply through a pull-up resistor R423, the B4 pin is used for an open-drain output, and the pull-up resistor R423 provides a current channel for the open-drain output;
the pins C4, D4 and E4 of the XJ4 area connector are connected with one end of a fuse F3 in parallel, capacitors C614-C616 are connected with one end of a fuse F3 far away from the pins C4, D4 and E4 in parallel, the parallel ends of the capacitors C614-C616 far away from the fuse F3 are grounded, the fuse F3 provides overcurrent protection for the backboard, the pins A1-E1 of the XJ4 area connector are respectively connected with a power supply through pull-up resistors R401, R402, R404, R405 and R403, the pins A1-E1 are used for open-drain output, the pull-up resistors R401-R405 provide current channels for the open-drain output, the pin E6 of the XJ4 area connector is electrically connected with a resistor R407, and the resistor R407 is used for reducing signal reflection.
Further, the capacitors C606, C612, C607, C613, C608, C609, C610, C611, C617, C618, C619, C620, C621, C622, C623, C624, C625, C626, C55 and C149 are used for cutting off dc level.
Specifically, the Analog-to-digital converter unit 3 is an AD7608BSTZ chip of Analog Device.
Preferably, the AD7608BSTZ chip is internally provided with 18bit, bipolar and 8-channel synchronous sampling, has an oversampling function, and has a signal-to-noise ratio of 90dB at 200 KSPS.
More specifically, the 49-63 pins of the AD7608BSTZ chip are electrically connected to the pins of each DPS chip unit, the analog signal output by each DPS chip unit enters the AD7608BSTZ chip through the 49-63 pins, and the AD7608BSTZ chip converts the analog signal into a digital signal and transmits the digital signal to the controller unit 2 through the 24 and 25 pins of the AD7608BSTZ chip.
Preferably, the DPS chip units 5-12 have the following features:
1. a programming Device Power Supply (DPS);
FV, MI, MV, FNMV function;
3.5 internal current ranges (on-chip RSENSE);
4.±5μA、±25μA、±250μA、±2.5mA、±25mA；
5.2 outer high current ranges (outer RSENSE);
extpore 1: ± 1.2A (maximum);
extpore 2: 500mA (max);
8. integrating the programmable level;
9. all 16-bit DACs: the drive DAC, the comparator DAC, the clamp DAC, the offset DAC, the OSD DAC and the DGS DAC are arranged;
10. programmable kelvin clamping and alarm.
Preferably, the DPS chip units 5-12 have a register (not shown) inside, which the controller unit 2 accesses by signal transmission of the register to inquire about the operating state of the DPS chip units 5-12.
Preferably, the SYS _ FORCE of the DPS chip units 5-12 are identically connected and the SYS _ SENSE of the DPS chip units 5-12 are identically connected.
Preferably, the controller unit 1 is a Xilinx Artix7 series FPGA chip and its peripheral circuits.
It should be mentioned that the utility model discloses a PXI EXPRESS machine case and subassembly that the patent application relates to, the regional connector of XJ3, the regional connector of XJ4, technical characteristics such as PCI EXPRESS serial interface should be regarded as prior art, PXIEXPRESS machine case can provide the power with power card electrical connection, the concrete structure of these technical characteristics, theory of operation and the control mode that may involve, spatial arrangement mode adopt the conventional selection in this field can, should not regard as the invention point of the utility model patent to be located, the utility model discloses a do not further specifically expand the detailing.
It will be apparent to those skilled in the art that modifications and variations can be made in the above-described embodiments, or some features of the invention may be substituted or omitted, and any modification, substitution, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A PXIE framework-based power card comprises an analog-to-digital converter unit and a plurality of DPS chip units, wherein the power card is electrically connected with a backboard and used for testing the performance of a chip, and the PXIE framework-based power card is characterized by comprising:
backplane connector unit, controller unit, DUT connector unit, wherein:
the controller unit is electrically connected with the analog-to-digital converter unit, the analog-to-digital converter unit converts an analog signal into a digital signal and transmits the digital signal to the controller unit, each DPS chip unit is electrically connected with the controller unit, and the output end of each DPS chip unit is connected in parallel and is electrically connected with the input end of the analog-to-digital converter unit;
one end of each DPS chip unit is electrically connected with the corresponding end of the DUT connector unit, and one end of the DUT connector unit, which is far away from the DPS chip unit, is electrically connected with one end of the test chip;
one end of the backplane connector unit is electrically connected with one end of the controller unit, and one end of the backplane connector unit, which is far away from the controller unit, is electrically connected with one end of the backplane.
2. The PXIE-based power card of claim 1, wherein the backplane connector unit comprises an XJ3 area connector and an XJ4 area connector, the XJ3 area connector and the XJ4 area connector being electrically connected, wherein:
the pins A, B, E, F, A, B, C, D, E, F of the XJ area connector are respectively electrically connected with capacitors C606, C612, C607, C613, C608, C609, C610, C611, C617, C618, C619, C620, C621, C622, C623, C624, C625, C626, C149, the capacitors C606, C612, C607, C613, C608, C609, C610, C611, C617, C618, C619, C620, C621, C622, C623, C624, C625, C626, C149 are far away from the pins A, B, E, F, A, B, C, D, E, F, E, F, and F pins of the XJ area connector are respectively electrically connected with the parallel pins A, B, A, B, E, F, A, B, F, and A, the B4 pin of the XJ3 area connector is connected with a power supply through a pull-up resistor R423, the B4 pin is used for an open-drain output, and the pull-up resistor R423 provides a current channel for the open-drain output;
the pins C4, D4 and E4 of the XJ4 area connector are connected to one end of a fuse in parallel, capacitors C614-C616 are connected to one end of the fuse far away from the pins C4, D4 and E4 in parallel, the capacitors C614-C616 are connected to the ground far away from the parallel end of the fuse, the fuse provides overcurrent protection for the backboard, the pins A1-E1 of the XJ4 area connector are respectively connected with a power supply through pull-up resistors R401, R402, R404, R405 and R403, the pins A1-E1 are used for open-drain output, the pull-up resistors R401-R405 provide current channels for the open-drain output, the pin E6 of the XJ4 area connector is electrically connected with a terminating resistor R407, and the terminating resistor R407 is used for reducing signal reflection.
3. The PXIE-architecture-based power card according to claim 1, wherein the Analog-to-digital converter unit is an AD7608BSTZ chip of Analog Device.
4. The power card based on the PXIE architecture as claimed in claim 3, wherein pins 49-63 of the AD7608BSTZ chip are electrically connected to pins of each DPS chip unit, analog signals output from each DPS chip unit enter the AD7608BSTZ chip through the pins 49-63, respectively, and the AD7608BSTZ chip converts the analog signals into digital signals and transmits the digital signals to the controller unit through pins 24 and 25 of the AD7608BSTZ chip.
5. The PXIE-based power card of claim 1, wherein each DPS chip unit has a register therein, and wherein the controller unit accesses the register via signal transmission from the register to query the operating state of the DPS chip unit.
6. The power card based on the PXIE architecture as claimed in claim 1, wherein the controller unit is a Xilinx Artix7 series FPGA chip and its peripheral circuits.
7. A backplane comprising a PXIE based power card according to any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920481012.9U CN209979709U (en) | 2019-04-10 | 2019-04-10 | PXIE framework-based power card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920481012.9U CN209979709U (en) | 2019-04-10 | 2019-04-10 | PXIE framework-based power card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209979709U true CN209979709U (en) | 2020-01-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920481012.9U Active CN209979709U (en) | 2019-04-10 | 2019-04-10 | PXIE framework-based power card |
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|---|---|
| CN (1) | CN209979709U (en) |
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- 2019-04-10 CN CN201920481012.9U patent/CN209979709U/en active Active
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| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210115 Address after: Room 513, 4th floor, building 2, 1158 Zhangdong Road, Pudong New Area Free Trade Zone, Shanghai, 200120 Patentee after: SHANGHAI POWERVALUE ELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 314000 a16-15 / F, 16 / F, building a, innovation building, 705 Asia Pacific Road, Nanhu District, Jiaxing City, Zhejiang Province Patentee before: JIAXING PENGWU ELECTRONIC TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right |