CN209887354U - Ceramic tray for grinding semiconductor epitaxial wafer - Google Patents
Ceramic tray for grinding semiconductor epitaxial wafer Download PDFInfo
- Publication number
- CN209887354U CN209887354U CN201920382249.1U CN201920382249U CN209887354U CN 209887354 U CN209887354 U CN 209887354U CN 201920382249 U CN201920382249 U CN 201920382249U CN 209887354 U CN209887354 U CN 209887354U
- Authority
- CN
- China
- Prior art keywords
- tray
- base
- fastening device
- epitaxial wafer
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The utility model discloses a ceramic tray for semiconductor epitaxial wafer grinds mainly includes base and tray, and the base top is connected with the tray bottom, and the base diameter is greater than the tray diameter to the base top still is provided with the fastening device of at least a pair of structure complete conformity, and the distance between fastening device top to the base bottom is greater than the tray top extremely distance between the base bottom, and a pair of fastening device set up the both sides at the tray diameter respectively to fastening device is provided with the clearance to the tray edge, the utility model discloses simple structure, it is convenient safe in utilization, can effectively improve epitaxial wafer substrate attenuate grinding process's the rate of certified products, can also deal with the attenuate grinding of the semiconductor of different diameters simultaneously to ensure grinding more reliable and stable.
Description
Technical Field
The utility model relates to a grind technical field, specifically be a ceramic tray for semiconductor epitaxial wafer grinds.
Background
In most semiconductor crystal growth processes, heteroepitaxy is mainly adopted, a certain lattice constant mismatch exists between a growth substrate and a semiconductor crystal material, so that a buffer layer is preset in epitaxial growth to adjust the stress among the materials, and in the growth process, the growth substrate warps due to the fact that the lattice constant of part of the semiconductor material is smaller than that of the growth substrate, and a material crystal accumulation layer can be formed on the edge of the growth substrate. In the subsequent semiconductor device process, since the growth substrate is thick, it is generally necessary to flip the epitaxial wafer, on which the semiconductor crystal layer is epitaxially grown, on the tray by wax bonding, and to thin the substrate. However, in the above epitaxial process, the thickness of the crystal accumulation layer at the edge of the substrate is thicker than the height of the device, so that the surface of the epitaxial wafer on which the semiconductor crystal material layer grows is uneven, and thus, the wafer is broken during the grinding process, which causes a reduction in the yield, and also directly affects the production cost, and the epitaxial wafer cannot cope with semiconductors of different diameters.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a ceramic tray for semiconductor epitaxial wafer grinds to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme: a ceramic tray for grinding semiconductor epitaxial wafers comprises a base and a tray, wherein the top of the base is connected with the bottom of the tray, the diameter of the base is larger than that of the tray, at least one pair of fastening mechanisms with completely consistent structures are further arranged on the top of the base, the distance between the top of each fastening mechanism and the bottom of the base is larger than that between the top of the tray and the bottom of the base, the fastening mechanisms are arranged on two sides of the diameter of the tray respectively, and gaps are arranged between the fastening mechanisms and the edges of the tray.
Preferably, fastening device includes bracing piece, adjusting screw and pressure head, the bracing piece sets up perpendicularly the base top, be provided with the bolt hole on the bracing piece, adjusting screw one end runs through the bolt hole with the pressure head is connected.
Preferably, a protective layer is arranged on one side, close to the tray, of the pressure head, and protruding points are uniformly arranged on the protective layer.
Preferably, the distance between the top of the pressure head and the bottom of the base is smaller than the distance between the top of the tray and the bottom of the base.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model discloses simple structure, it is convenient safe in utilization, can effectively improve epitaxial wafer substrate attenuate grinding process's the rate of certified products, the attenuate of the semiconductor of different diameters can also be dealt with simultaneously grinds to ensure grinding more reliable and stable.
Drawings
FIG. 1 is a schematic structural view of the present invention;
fig. 2 is a schematic top view of the structure of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: a ceramic tray for grinding semiconductor epitaxial wafers comprises a base 1 and a tray 2, wherein the top of the base 1 is connected with the bottom of the tray 2, the diameter of the base 1 is larger than that of the tray 2, and at least one pair of fastening mechanisms 3 with completely consistent structures are arranged on the top of the base 1; the distance between the top of the fastening mechanism 3 and the bottom of the base 1 is greater than the distance between the top of the tray 2 and the bottom of the base 1, a pair of the fastening mechanisms 3 are respectively arranged on two sides of the diameter of the tray 2, and a gap is arranged between the fastening mechanisms 3 and the edge of the tray 2; through this structural arrangement, can ensure to carry out attenuate grinding to the semiconductor of different diameters and handle, the security is high simultaneously.
In the utility model, the fastening mechanism 3 comprises a support rod 4, an adjusting screw rod 5 and a pressure head 6, the support rod 4 is vertically arranged at the top of the base 1, the support rod 4 is provided with a bolt hole, and one end of the adjusting screw rod 5 penetrates through the bolt hole and is connected with the pressure head 6; the design structure is adopted to ensure simpler and more convenient operation and improve the working efficiency.
In the utility model, a protective layer is arranged on one side of the pressure head 6 close to the tray 2, and convex points are uniformly arranged on the protective layer; the design structure is adopted to ensure that the surface of the semiconductor is not scratched when the semiconductor is fixed, and ensure more stability and reliability when the semiconductor is used.
In addition, in the utility model, the distance between the top of the pressure head 6 and the bottom of the base 1 is less than the distance between the top of the tray 2 and the bottom of the base 1; in order to secure the semiconductor wafer without affecting the polishing during the fixing, and to fix the semiconductor wafer, the height difference between the top of the head and the top of the tray should be controlled to be in the range of 10 mm to 20 mm.
The working principle is as follows:
at first at tray top coating one deck bond line, then with the semiconductor back-off in the tray, the periphery that makes the semiconductor crystal layer of epitaxial wafer is located the tray makes the pressure head can be fixed semiconductor and tray through adjusting fastening device in its periphery, what need explain, the utility model discloses in, tray top be the planar structure setting.
To sum up, the utility model discloses structural design is novel, and it is convenient safe in utilization, can effectively improve epitaxial wafer substrate attenuate grinding process's the rate of certified products, can also deal with the attenuate grinding of the semiconductor of different diameters simultaneously to ensure grinding more reliable and stable.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, article, or apparatus.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Exemplary embodiments according to the present application will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art, in the drawings, it is possible to enlarge the thicknesses of layers and regions for clarity, and the same devices are denoted by the same reference numerals, and thus the description thereof will be omitted.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (4)
1. A ceramic tray for semiconductor epitaxial wafer grinding comprises a base (1) and a tray (2), and is characterized in that: the base (1) top with tray (2) bottom is connected, just base (1) diameter is greater than tray (2) diameter, and base (1) top still is provided with at least a pair of fastening device (3) that the structure is identical completely, fastening device (3) top extremely the distance between base (1) bottom is greater than tray (2) top extremely the distance between base (1) bottom, and a pair of fastening device (3) set up respectively the both sides of tray (2) diameter, and fastening device (3) extremely tray (2) edge is provided with the clearance.
2. The ceramic tray for grinding the semiconductor epitaxial wafer as claimed in claim 1, wherein: fastening device (3) include bracing piece (4), adjusting screw (5) and pressure head (6), bracing piece (4) set up perpendicularly base (1) top, be provided with the bolt hole on bracing piece (4), adjusting screw (5) one end runs through the bolt hole with pressure head (6) are connected.
3. The ceramic tray for grinding the semiconductor epitaxial wafer as claimed in claim 2, wherein: the pressure head (6) is close to one side of the tray (2) and is provided with a protective layer, and the protective layer is evenly provided with convex points.
4. The ceramic tray for grinding the semiconductor epitaxial wafer as claimed in claim 2 or 3, wherein: the distance between the top of the pressure head (6) and the bottom of the base (1) is smaller than the distance between the top of the tray (2) and the bottom of the base (1).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201920382249.1U CN209887354U (en) | 2019-03-25 | 2019-03-25 | Ceramic tray for grinding semiconductor epitaxial wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201920382249.1U CN209887354U (en) | 2019-03-25 | 2019-03-25 | Ceramic tray for grinding semiconductor epitaxial wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
CN209887354U true CN209887354U (en) | 2020-01-03 |
Family
ID=68997996
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201920382249.1U Expired - Fee Related CN209887354U (en) | 2019-03-25 | 2019-03-25 | Ceramic tray for grinding semiconductor epitaxial wafer |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN209887354U (en) |
-
2019
- 2019-03-25 CN CN201920382249.1U patent/CN209887354U/en not_active Expired - Fee Related
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Powell et al. | Bulk growth of large area SiC crystals | |
KR101638888B1 (en) | Method for processing semiconductor wafer | |
US20150194319A1 (en) | Flat sic semiconductor substrate | |
WO2016129172A1 (en) | Indium phosphorus substrate, indium phosphorus substrate inspection method, and indium phosphorus substrate manufacturing method | |
WO2017047508A1 (en) | METHOD FOR PRODUCING SiC COMPOSITE SUBSTRATE | |
JP2009182126A (en) | Method of machining compound semiconductor substrate and compound semiconductor substrate | |
CN110071038A (en) | A kind of method that semiconductive thin film flatness improves | |
CN209887354U (en) | Ceramic tray for grinding semiconductor epitaxial wafer | |
CN102079113B (en) | Equipment and method for solving squaring quality problem of silicon ingot | |
CN104555907A (en) | Bonding method and bonding structure | |
CN109623553A (en) | A kind of chamfering grinding wheel, chamfer grinding device and grinding method | |
US7892072B2 (en) | Method for directional grinding on backside of a semiconductor wafer | |
CN112018025A (en) | Preparation method of III-V group compound semiconductor heterojunction structure | |
JP6327519B2 (en) | Method for processing silicon carbide single crystal substrate and silicon carbide single crystal substrate with jig | |
JPH02208931A (en) | Polishing process for compound semiconductor substrate | |
US20160163801A1 (en) | Group iii nitride substrates and their fabrication method | |
WO2016090223A1 (en) | Group iii nitride substrates and their fabrication method | |
US20140045411A1 (en) | Methods of and apparatus for producing wafers | |
US20130149941A1 (en) | Method Of Machining Semiconductor Substrate And Apparatus For Machining Semiconductor Substrate | |
US20200347513A1 (en) | Epitaxial wafer processing method | |
CN104538508B (en) | The angularity control method of GaN epitaxy silicon substrate material | |
JP6032087B2 (en) | Method for producing group 13 nitride crystal substrate | |
CN204772054U (en) | A anchor clamps for polishing carborundum single crystal gulde edge | |
KR20140148198A (en) | Laminating apparatus of wafer film and the method using the same | |
CN206116361U (en) | A ceramic tray for semiconductor epitaxial wafer grinds |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200103 |
|
CF01 | Termination of patent right due to non-payment of annual fee |