CN209878871U

CN209878871U - Drive overcurrent detection circuit

Info

Publication number: CN209878871U
Application number: CN201920454121.1U
Authority: CN
Inventors: 关硕; 张旭; 陈光胜
Original assignee: Shanghai Eastsoft Microelectronics Co Ltd
Current assignee: Shanghai Eastsoft Microelectronics Co Ltd
Priority date: 2019-04-04
Filing date: 2019-04-04
Publication date: 2019-12-31
Anticipated expiration: 2029-04-04

Abstract

A drive overcurrent detection circuit comprising: the driving transistor, the MOS pipe of the same type with the driving transistor, operation amplifier circuit, first current mirror circuit and reference current source, wherein: the first input end of the operational amplifier circuit is coupled with the drain electrode of the driving tube, the second input end of the operational amplifier circuit is coupled with the drain electrode of the MOS tube, and the output end of the operational amplifier circuit is coupled with the current input end of the first current mirror circuit; the driving tube inputs a control signal to the grid; the grid of the MOS tube inputs a control signal; the current output end of the first current mirror circuit is coupled with the output end of the reference current source and the judgment result output end of the driving overcurrent detection circuit; and when the output current of the current output end of the first current mirror is larger than the output current of the reference current source, judging that the driving tube is overcurrent. The scheme can accurately judge whether the driving pipe overflows or not.

Description

Drive overcurrent detection circuit

Technical Field

The utility model relates to a circuit field especially relates to a drive detection circuitry that overflows.

Background

When driving devices such as the driving tube and the like work, because the resistance of the driving tube is small, the current flowing on the driving tube is determined by the load coupled with the driving tube. When the load is small, even when the load is short-circuited, the current flowing through the driving tube is large, and the driving tube is in an overcurrent condition. When the drive tube is subjected to an overcurrent condition, the drive tube or load can be severely damaged. Therefore, the output current of the driving tube needs to be limited to avoid the above situation.

In the prior art, in order to determine whether the overcurrent condition of the driving tube occurs, one scheme is to connect a resistor in series between the driving tube and the ground. Because the current flowing through the driving tube flows through the resistor, whether the driving tube has overcurrent or not can be judged through the voltage drop of the resistor. However, the smaller the output impedance of the driving tube is, the better, otherwise, most of the power is consumed in the driving tube itself rather than the load, and the driving purpose is not achieved. After the resistor is connected in series between the driving tube and the ground, the equivalent output impedance of the driving tube is increased, and the performance of the driving tube is influenced. The other scheme for judging whether the driving tube is overcurrent is to directly measure the voltage drop on the driving tube so as to judge whether the driving tube is overcurrent. However, due to temperature, process, and other deviations, the voltage drop across the drive tube and the current flowing through the drive tube may not exactly correspond to the solution.

The existing scheme for avoiding the overcurrent of the driving tube can not accurately judge whether the driving tube is in overcurrent or not under the condition of not influencing the driving performance.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a solve be current avoid the driving tube to overflow in the scheme, can't judge accurately whether the technical problem that the driving tube overflows.

In order to solve the above technical problem, an embodiment of the utility model provides a drive detection circuitry that overflows, include: the MOS transistor of the same type as the driving transistor, an operational amplifier circuit, a first current mirror circuit and a reference current source, wherein: the first input end of the operational amplifier circuit is coupled with the drain electrode of the driving tube, the second input end of the operational amplifier circuit is coupled with the drain electrode of the MOS tube, and the output end of the operational amplifier circuit is coupled with the current input end of the first current mirror circuit; the grid electrode of the driving tube inputs a control signal; the grid of the MOS tube inputs a control signal; when the driving tube and the MOS tube are both PMOS tubes, the source electrode of the driving tube and the source electrode of the MOS tube are both inputted with power supply voltage; when the driving tube and the MOS tube are both NMOS tubes, the source electrode of the driving tube and the source electrode of the MOS tube are both coupled with the ground; the output current of the operational amplification circuit and the current flowing through the driving tube are related to the first current mirror circuit, and the current output end is coupled with the output end of the reference current source and the judgment result output end of the driving overcurrent detection circuit; and when the output current of the current output end of the first current mirror is larger than the output current of the reference current source, judging that the driving tube is overcurrent.

Optionally, the driving tube is a PMOS tube, and the MOS tube is a first PMOS tube.

Optionally, the first current mirror circuit includes: second NMOS pipe and third NMOS pipe, wherein: the grid electrode of the second NMOS tube is coupled with the drain electrode, the drain electrode is the current input end of the first current mirror circuit, and the source electrode is coupled with the ground; and the drain electrode of the third NMOS tube is the current output end of the first current mirror circuit, the grid electrode of the third NMOS tube is coupled with the grid electrode of the second NMOS tube, and the source electrode of the third NMOS tube is coupled with the ground.

Optionally, the width-to-length ratio of the second NMOS transistor is N times of the width-to-length ratio of the third NMOS transistor, where N is greater than 1.

Optionally, the operational amplifier circuit includes: first NMOS pipe and error amplification circuit, wherein: the first input end of the error amplifying circuit is the first input end of the operational amplifying circuit, the second input end of the error amplifying circuit is the second input end of the operational amplifying circuit, and the output end of the error amplifying circuit is coupled with the grid electrode of the first NMOS tube; and the drain electrode of the first NMOS tube is coupled with the second input end of the error amplifying circuit, and the source electrode of the first NMOS tube is the output end of the operational amplifying circuit.

Optionally, the driving overcurrent detection circuit further includes: a first bias current source, wherein: a current output end of the first bias current source is coupled with a bias current input end of the error amplification circuit; the error amplifying circuit further comprises a first current mirror bias; the first current mirror is biased, the current input end is a bias current input end of the error amplification circuit, the current output end is an output end of the error amplification circuit, and the first current mirror is suitable for mirroring the first bias current output by the first bias current source to the output end of the error amplification circuit and outputting the mirrored first bias current.

Optionally, the error amplifying circuit includes: second PMOS pipe, third PMOS pipe, fourth NMOS pipe, fifth NMOS pipe and sixth NMOS pipe, wherein: the grid electrode of the second PMOS tube is coupled with the drain electrode of the second NMOS tube, the source electrode of the second PMOS tube is coupled with the drain electrode of the driving tube, and the drain electrode of the second PMOS tube is coupled with the drain electrode of the fourth NMOS tube; the source electrode of the third PMOS tube is coupled with the drain electrode of the first PMOS tube, the grid electrode of the third PMOS tube is coupled with the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is coupled with the drain electrode of the fifth NMOS tube; the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the fifth NMOS tube, and the source electrode of the fourth NMOS tube is coupled with the ground; the source electrode of the fifth NMOS tube is coupled with the ground, and the drain electrode of the fifth NMOS tube is the output end of the error amplifying circuit and the current output end biased by the first current mirror; the drain of the sixth NMOS transistor is a current input end biased by the first current mirror, the grid of the sixth NMOS transistor is coupled with the grid of the fourth NMOS transistor, the grid of the fifth NMOS transistor and the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is coupled with the ground.

Optionally, the driving overcurrent detection circuit further includes: and a current output end of the second bias current source is coupled with the current input end of the first current mirror circuit.

Optionally, the driving tube is an NMOS tube, and the MOS tube is a seventh NMOS tube.

Optionally, the first current mirror circuit includes: fifth PMOS pipe and sixth PMOS pipe, wherein: the grid electrode and the drain electrode of the fifth PMOS tube are coupled, the drain electrode is the current input end of the first current mirror circuit, and the source electrode inputs the power supply voltage; and the drain of the sixth PMOSS tube is the current output end of the first current mirror circuit, the grid of the sixth PMOSS tube is coupled with the grid of the fifth PMOS tube, and the source of the sixth PMOSS tube inputs the power supply voltage.

Optionally, the width-to-length ratio of the fifth PMOS transistor is N times of the width-to-length ratio of the sixth PMOS transistor, where N is greater than 1.

Optionally, the operational amplifier circuit includes: fourth PMOS pipe and error amplification circuit, wherein: the operational amplifier circuit includes: fourth PMOS pipe and error amplification circuit, wherein: and the drain electrode of the fourth PMOS tube is coupled with the second input end of the error amplifying circuit, and the source electrode of the fourth PMOS tube is the output end of the operational amplifying circuit.

Optionally, the driving overcurrent detection circuit further includes: a third bias current source, wherein: a current output end of the third bias current source is coupled with a bias current input end of the error amplification circuit; the error amplifying circuit further comprises a second current mirror bias; and the second current mirror is biased, the current input end is a bias current input end of the error amplification circuit, and the current output end is an output end of the error amplification circuit, and is suitable for mirroring the third bias current output by the third bias current source to the output end of the error amplification circuit and outputting the mirrored third bias current.

Optionally, the error amplifying circuit includes: eighth NMOS pipe, ninth NMOS pipe, seventh PMOS pipe, eighth PMOS pipe and ninth PMOS pipe, wherein: the grid electrode of the eighth NMOS tube is coupled with the drain electrode, the source electrode of the eighth NMOS tube is coupled with the drain electrode of the driving tube, and the drain electrode of the eighth NMOS tube is coupled with the drain electrode of the seventh PMOS tube; the source of the ninth NMOS tube is coupled with the drain of the seventh NMOS tube, the gate of the ninth NMOS tube is coupled with the gate of the eighth NMOS tube, and the drain of the ninth NMOS tube is coupled with the drain of the eighth PMOS tube; the grid electrode of the seventh PMOS tube is coupled with the grid electrode of the eighth PMOS tube, and the source electrode of the seventh PMOS tube inputs the power supply voltage; the source electrode of the eighth PMOS tube inputs the power supply voltage, and the drain electrode of the eighth PMOS tube is the output end of the error amplifying circuit and the current output end biased by the second current mirror; the drain of the ninth PMOS transistor is a current input end biased by the second current mirror, the gate of the ninth PMOS transistor is coupled to the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor and the drain of the ninth PMOS transistor, and the source of the ninth PMOS transistor inputs the power voltage.

Optionally, the driving overcurrent detection circuit further includes: and a current output end of the fourth bias current source is coupled with the current input end of the first current mirror circuit.

Optionally, the driving overcurrent detection circuit further includes: a second current mirror circuit; the current input end of the second current mirror circuit is coupled with the current output end of the first current mirror circuit, and the current output end of the second current mirror circuit is coupled with the output end of the reference current source.

Optionally, the second current mirror circuit includes: tenth NMOS pipe and eleventh NMOS pipe, wherein: a grid electrode of the tenth NMOS tube is coupled with a drain electrode, the drain electrode is a current input end of the second current mirror circuit, the grid electrode is coupled with a grid electrode of the eleventh NMOS tube, and a source electrode is coupled with the ground; and the drain electrode of the eleventh NMOS tube is the current output end of the second current mirror circuit, and the source electrode of the eleventh NMOS tube is coupled with the ground.

Optionally, the driving overcurrent detection circuit further includes: and the input end of the trigger is coupled with the current output end of the first current mirror circuit, and the output end of the trigger is coupled with the judgment result output end of the driving overcurrent detection circuit.

Optionally, the trigger comprises a schmitt trigger.

Optionally, the width-to-length ratio of the driving tube is M times of the width-to-length ratio of the MOS tube, where M is greater than 1.

Optionally, the reference current source is a current source with adjustable output current.

Compared with the prior art, the utility model discloses technical scheme has following beneficial effect:

the driving tube and the MOS tube are correspondingly arranged, and the current on the MOS tube is determined according to the current flowing through the driving tube, the width-length ratio of the driving tube and the width-length ratio of the MOS tube, so that the input current of the current input end of the first current mirror circuit is determined. The output current at the current output terminal of the first current mirror circuit is related to the input current at the current input terminal. And when the output current of the current output end of the first current mirror is larger than the output current of the reference current source, judging that the driving tube is overcurrent. When judging whether the driving tube is overcurrent or not, the judgment is carried out according to the width-length ratio of the driving tube, the width-length ratio of the MOS tube, the output current of the reference current source and the current input-output ratio of the first current mirror circuit, and the voltage drop on the driving tube is not required to be measured, so that the number of times of electrical conversion can be reduced, and whether the driving tube is overcurrent or not can be accurately judged.

Further, a Schmitt trigger is arranged between the current output end of the first current mirror circuit and the judgment result output end of the driving overcurrent detection circuit, so that the influence of burrs of the current on the driving tube on the judgment result can be avoided.

Drawings

Fig. 1 is a circuit structure diagram of a driving overcurrent detecting circuit according to an embodiment of the present invention;

fig. 2 is a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention;

fig. 3 is a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention;

fig. 4 is a circuit structure diagram of a driving overcurrent detecting circuit according to an embodiment of the present invention;

fig. 5 is a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention;

fig. 6 is a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention;

fig. 7 is a circuit diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention.

Detailed Description

Therefore, the existing driving overcurrent detection schemes cannot accurately judge whether the driving tube is in overcurrent or not.

The embodiment of the utility model provides an in, when judging the driving tube and overflowing, judge according to the wide length ratio of driving tube and the wide length ratio of MOS pipe, the output current of reference current source and the current input output ratio of first current mirror circuit, need not to measure the pressure drop on the driving tube, consequently can reduce different class size electrical conversion number of times, can judge accurately whether the driving tube overflows.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

The embodiment of the utility model provides a drive detection circuitry that overflows, include: the driving transistor, the MOS pipe of the same type with the driving transistor, operation amplifier circuit, first current mirror circuit and reference current source, wherein:

the first input end of the operational amplification circuit is coupled with the drain electrode of the driving tube, the second input end of the operational amplification circuit is coupled with the drain electrode of the MOS tube, and the output end of the operational amplification circuit is coupled with the current input end of the first current mirror circuit;

the grid of the driving tube and the grid of the MOS tube are input with control signals; when the driving tube and the MOS tube are both PMOS tubes, the source electrode of the driving tube and the source electrode of the MOS tube are both inputted with power supply voltage; when the driving tube and the MOS tube are both NMOS tubes, the source electrode of the driving tube and the source electrode of the MOS tube are both grounded;

the current input end of the first current mirror circuit is coupled with the output end of the operational amplification circuit, and the current output end of the first current mirror circuit is coupled with the output end of the reference current source and the judgment result output end of the driving overcurrent detection circuit;

and the input end of the reference current source inputs power supply voltage, and the output end of the reference current source is coupled with the current output end of the first current mirror circuit.

In specific implementation, the width-to-length ratio of the driving tube is larger than that of the MOS tube. In the embodiment of the present invention, the width-to-length ratio of the driving tube is M times of the width-to-length ratio of the MOS tube, and M > 1.

In specific application, the width-to-length ratio of the driving tube can exceed that of the MOS tube by several orders of magnitude, that is, the width-to-length ratio of the driving tube can be far greater than that of the MOS tube. In other words, the width-to-length ratio of the driving tube may be tens of times or even more than the width-to-length ratio of the MOS tube. In an embodiment of the present invention, the width-to-length ratio of the driving transistor is 5000 times the width-to-length ratio of the MOS transistor.

In specific implementation, the driving tube and the MOS tube may be the same type of device, and the driving tube and the MOS tube may be placed at adjacent positions of the same chip, thereby ensuring that the deviations of the process, the temperature, and the power supply voltage have the same influence on the MOS tube and the driving tube.

In a specific implementation, a trigger may be further disposed between the current output terminal of the first current mirror circuit and the determination result output terminal of the driving overcurrent detection circuit, an input terminal of the trigger is coupled to the current output terminal of the first current mirror circuit, and an output terminal of the trigger is coupled to the determination result output terminal of the driving overcurrent detection circuit. Because the trigger of the trigger needs a certain threshold and delay, the Schmitt trigger can avoid the influence of the burr of the current on the driving tube on the judgment result.

In an embodiment of the present invention, the trigger may be a schmitt trigger.

The driving overcurrent detection circuit when the driving transistor is a PMOS transistor will be described in detail below.

Referring to fig. 1, an embodiment of the present invention provides a drive overcurrent detection circuit, in which the driving transistor is a PMOS transistor MPD, and the MOS transistor is a first PMOS transistor MP 1.

In fig. 1, the operational amplifier circuit includes an error amplifier circuit a1 and a first NMOS transistor MN1, wherein:

a first input terminal "-" of the error amplifying circuit a1 is a first input terminal of the operational amplifying circuit, and is coupled to the drain of the driving tube MPD; the second input end "+" of the error amplifying circuit A1 is the second input end of the operational amplifying circuit, and is coupled to the drain of the first PMOS transistor MP 1; the output end of the error amplifying circuit a1 is coupled to the gate of the first NMOS transistor MN1, and coupled to the gate of the first NMOS transistor MN 1;

a first NMOS transistor MN1, having a gate coupled to the output terminal of the error amplifier circuit a 1; the drain is coupled to the second input terminal "+" of the error amplifier circuit A1, and the source is the output terminal of the operational amplifier circuit.

The first NMOS transistor MN1 and the error amplifier a1 form a negative feedback loop.

The source of the driving transistor MPD receives a power voltage VCC, the gate receives a control signal, and the drain is coupled to the first input terminal "-" of the error amplifying circuit a 1. In a specific application, the drain of the driving tube MPD is the output OUT of the driving tube, and may be connected to a driving load.

The source of the first PMOS transistor MP1 receives the power voltage VCC, the gate receives the control signal, and the drain is coupled to the second input terminal "+" of the error amplifier A1.

And a first current mirror circuit, wherein a current input end is coupled with an input end of a feedback circuit in the operational amplification circuit, and a current output end is coupled with an output end of the reference current source 11.

A reference current source 11, one end of which inputs the power voltage VCC, and an output end of which is coupled to the current output end of the first current mirror circuit.

In the embodiment of the present invention, the reference current source 11 is suitable for outputting a constant current I_R。

In a specific implementation, the driving transistor MPD and the first PMOS transistor MP1 are disposed adjacent to each other on the same chip, so that the influence of process, temperature, and power voltage deviations on the first PMOS transistor MP1 and the driving transistor MPD can be ensured to be the same.

In a specific implementation, the width-to-length ratio of the driving tube MPD is different from that of the first PMOS tube MP1, and the width-to-length ratio of the driving tube MPD is greater than that of the first PMOS tube MP 1. In the embodiment of the present invention, the width-to-length ratio of the driving tube MPD is M times of the width-to-length ratio of the first PMOS tube MP1, where M > 1.

In a specific application, the width-to-length ratio of the driving transistor MPD may exceed that of the first PMOS transistor MP1 by several orders of magnitude. In other words, the width-to-length ratio of the driving transistor MPD may be tens of times or more than the width-to-length ratio of the first PMOS transistor MP 1. In an embodiment of the present invention, the width-to-length ratio of the driving tube MPD is 5000 times the width-to-length ratio of the first PMOS transistor MP 1.

In an implementation, the gate of the driving transistor MPD may be coupled to the gate of the first PMOS transistor MP1, and the control signal is input to the gate of the driving transistor MPD and the gate of the first PMOS transistor MP 1. The control signal can control the drive tube MPD to be turned off or on, and the first PMOS tube MP1 to be turned off or on.

Since the driving tube MPD and the first PMOS tube MP1 are PMOS tubes of the same type, when the driving tube MPD is turned off by the control signal, the first PMOS tube MP1 is also turned off; on the contrary, when the driving transistor MPD is turned on by the control signal, the first PMOS transistor MP1 is also turned on.

In the embodiment of the present invention, the control signal may be VG. When the control signal VG is a low level signal, the driving transistor MPD and the first PMOS transistor MP1 are both in a conducting state under the action of the control signal VG.

In a specific implementation, the first current mirror circuit may include a second NMOS transistor MN2 and a third NMOS transistor MN 3.

The gate of the second NMOS transistor MN2 is coupled to the drain of the second NMOS transistor MN2, that is, the gate of the second NMOS transistor MN2 is coupled to the drain thereof; the drain of the second NMOS transistor MN2 is the current input terminal of the first current mirror circuit, and is coupled to the source of the first NMOS transistor MN 1; the source of the second NMOS transistor MN2 is coupled to ground.

The drain of the third NMOS transistor MN3 is the current output terminal of the first current mirror circuit, and is coupled to the output terminal of the reference current source 11 and the input terminal of the determination result output terminal OC of the driving overcurrent detection circuit; the gate of the third NMOS transistor MN3 is coupled to the gate of the second NMOS transistor MN 2; the source of the third NMOS transistor MN3 is coupled to ground.

In the embodiment of the present invention, the width-to-length ratio of the second NMOS transistor MN2 is N times the width-to-length ratio of the third NMOS transistor MN3, where N > 1.

In a specific implementation, the output current of the reference current source 11 may be set in advance. The setting of the output current of the reference current source 11 may be associated with three of: critical current value I of MPD overcurrent of driving tube_maxThe ratio M of the width-to-length ratio of the MPD of the driving tube to the width-to-length ratio of the MP1 of the first PMOS tube, and the ratio N of the width-to-length ratio of the MN2 of the second NMOS tube to the width-to-length ratio of the MN3 of the third NMOS tube.

In the embodiment of the present invention, the output current of the reference current source 11 is set as: i is_max/(M.times.N). When the output current of the current output end of the first current mirror circuit is greater than the output current of the reference current source 11, the overcurrent condition of the driving tube MPD can be judged; and otherwise, judging that the MPD of the driving tube has no overcurrent condition.

The working principle of the driving overcurrent detection circuit provided in the above embodiment of the present invention is explained below.

It can be known from the above embodiments of the present invention that the driving tube MPD and the first PMOS tube MP1 are PMOS tubes of the same type, and the production processes of the driving tube MPD and the first PMOS tube MP1 are the same, so that the deviation of the power voltage and the temperature has the same effect on the driving tube MPD and the first PMOS tube MP 1. When the gate of the driving transistor MPD and the gate of the first PMOS transistor MP1 both input the control signal VG, the driving transistor MPD and the first PMOS transistor MP1 are both turned on. Through the width-to-length ratio of the driving tube MPD and the width-to-length ratio of the first PMOS tube MP1, the ratio between the resistance value of the driving tube MPD and the resistance value of the first PMOS tube MP1 can be determined.

In the embodiment of the present invention, the width-to-length ratio of the driving tube MPD is M times of the width-to-length ratio of the first PMOS transistor MP1, and therefore, the resistance R of the driving tube MPD_MPDAnd the resistance value R of the first PMOS transistor MP1_MP1The ratio between is 1/M, that is: r_MPD/R_MP1＝1/M。

When the current flowing through the MPD of the driving tube is I_LFrom ohm's law, the output voltage of the driving tube MPD is:

V_OUT＝VCC-I_L×R_MPD； (1)

therefore, the voltage at the first input terminal of the error amplifying circuit A1 is VCC-I_L×R_MPD。

At this time, the input voltage of the second input terminal of the error amplifier circuit a1 is:

V₁＝V_OUT＝VCC-I_L×R_MPD＝VCC-I₁×R_MP1； (2)

wherein, I₁The output current of the drain of the first PMOS transistor MP 1.

From the above equation (1) and the above equation (2), it can be known that: i is_L×R_MPD＝I₁×R_MP1。

Due to R_MPD/R_MP11/M, so that: i is₁/I_L＝1/M。

I₁The current is input to the current input terminal of the first current mirror circuit, that is: the drain of the second NMOS transistor MN2 has a current of I₁. According to the mirror image relationship between the second NMOS transistor MN2 and the third NMOS transistor MN3, since the width-to-length ratio of the second NMOS transistor MN2 is N times the width-to-length ratio of the third NMOS transistor MN3, the current of the drain of the third NMOS transistor MN3 is I₁/N。

When the overcurrent detection circuit is driven without the flip-flop 12, if the current of the drain of the third NMOS transistor MN3 is greater than the output current I of the reference current source 11_RI.e. when I₁/N＞I_RAnd then, the output result of the judgment result output end OC of the driving over-current detection circuit is a logic high level. At this time, the MPD of the driving tube is judged to have an overcurrent condition.

On the contrary, if the current of the drain of the third NMOS transistor MN3 is smaller than the output current of the reference current source 11, the output result of the determination result output terminal OC of the driving overcurrent detection circuit is a logic low level, and at this time, it is determined that the driving transistor MPD has no overcurrent condition.

In a specific implementation, since the output impedance of the current source is high, if the current output by the reference current source 11 is larger than the current output by the drain of the third NMOS transistor MN3, the current flows from the reference current source 11 to the ground in the loop formed by the reference current source 11 and the third NMOS transistor MN 3. After the current passes through the current mirror impedance, the drain of the third NMOS transistor MN3 is raised to the power supply voltage VCC. At this time, the output terminal OC outputs a logic low level.

On the contrary, if the current outputted by the reference current source 11 is smaller than the current outputted by the drain of the third NMOS transistor MN3, the drain of the third NMOS transistor MN3 is pulled down to ground. At this time, the output terminal OC outputs a logic high level.

In a specific implementation, a current flowing through the driving tube MPD may have a glitch, which causes an error in a determination result output by the determination result output terminal OC of the final current detection circuit. Therefore, for avoiding the influence of the burr of the electric current on the drive tube MPD to the judgement result, in the embodiment of the present invention, the trigger 12 can also be set between the current output end of the first current mirror circuit and the judgement result output end OC. Since the trigger 12 needs a certain threshold and delay for triggering, the influence of the glitch of the current on the drive tube MPD on the determination result can be effectively avoided.

In an embodiment of the present invention, the trigger 12 may be a schmitt trigger.

In the embodiment of the present invention, when the flip-flop 12 is provided between the current output end of the first current mirror circuit and the determination result output end OC, the level of the output signal of the flip-flop 12 is opposite to the level of the determination result output end OC output signal. When the level of the output signal of the output terminal OC is a logic low level, the level of the output signal of the flip-flop 12 is a logic high level; when the level of the output signal of the output terminal OC is a logic high level, the level of the output signal of the flip-flop 12 is a logic low level.

Therefore, when the trigger 12 is added, when the level of the output signal of the judgment result output end OC is a logic high level, the condition that the drive tube MPD has overcurrent is judged; and when the level of the output signal of the judgment result output end OC is a logic low level, judging that the MPD of the driving tube has no overcurrent.

In a specific implementation, the reference current source 11 is a current source with an adjustable output current, that is, the output current of the reference current source 11 is adjustable in magnitude. Since the output current of the reference current source 11 is related to M, N, the value of M, N can be more flexible when the output current of the reference current source 11 is adjustable.

In a specific implementation, the error amplifying circuit a1 may further include a bias current input terminal, and the driving overcurrent detecting circuit may further include a first bias current source 13 (as shown in fig. 2), where:

a first bias current source 13, a current output terminal of which is coupled to a bias current input terminal of the error amplifying circuit a1, and an input terminal of which is inputted with the power supply voltage VCC.

The error amplifying circuit a1 may further include a first current mirror bias, a current input terminal of the first current mirror bias is a bias current input terminal of the error amplifying circuit a1, that is, the current input terminal of the first current mirror bias is coupled to a current output terminal of the first bias current source 13; the current output terminal of the first current mirror bias is the output terminal of the error amplifying circuit a 1. The first current mirror bias may mirror the first bias current output from the first bias current source 13 to the output terminal of the error amplification circuit a1 and output it.

Referring to fig. 2, a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention is shown.

In fig. 2, the error amplification circuit a1 includes: a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6, wherein:

the gate and the drain of the second PMOS transistor MP2 are coupled, the source of the second PMOS transistor MP2 is coupled to the drain of the driving transistor MPD, and the drain of the second PMOS transistor MP2 is coupled to the drain of the fourth NMOS transistor MN 4; the source of the second PMOS transistor MP2 is the first input terminal of the error amplifying circuit a 1;

a source electrode of the third PMOS transistor MP3 is coupled to a drain electrode of the first PMOS transistor MP1, a gate electrode of the third PMOS transistor MP3 is coupled to a gate electrode of the second PMOS transistor MP2, and a drain electrode of the third PMOS transistor MP3 is coupled to a drain electrode of the fifth NMOS transistor MN 5; the source of the third PMOS transistor MP3 is the second input terminal of the error amplifying circuit a 1;

the gate of the fourth NMOS transistor MN4 is coupled to the gate of the fifth NMOS transistor MN5, and the source of the fourth NMOS transistor MN4 is coupled to ground;

the gate of the fifth NMOS transistor MN5 is coupled to the gate of the fourth NMOS transistor MN4, and the drain of the fifth NMOS transistor MN5 is the output terminal of the error amplifier circuit a1 and the current output terminal biased by the first current mirror; the source of the fifth NMOS transistor MN5 is coupled to ground;

the drain of the sixth NMOS transistor MN6 is a current input terminal biased by the first current mirror, the gate of the sixth NMOS transistor MN6 is coupled to the drain of the sixth NMOS transistor MN6, the gate of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5, and the source of the sixth NMOS transistor MN6 is coupled to ground.

In a specific implementation, the output current of the first bias current source 13 is I_B. In the embodiment of the present invention, the output current I of the first bias current source 13_BOn the μ a scale.

After the first bias current source 13 is provided, the sixth NMOS transistor MN6 may mirror the output current of the first bias current source 13 to the drain of the fifth NMOS transistor MN 5. At this time, I_B+I_L＝(I_B+I₁) Xm, so that the current flowing through the second NMOS transistor MN2 is:

I₁＝[I_L-(M-1)×I_B]＝I_L/M-(M-1)/M×I_B(3)。

in the formula (3), (M-1)/MXI_BAnd is generally negligible.

For example, when the current flowing through the driving tube MPD is set to 500mA, M is 1000, I_B1 muA, then I₁There is an error of 0.2%, i.e. I_LThe error of (2) is 0.2%.

In order to reduce the error, in the embodiment of the present invention, a second bias current source 14 (as shown in fig. 3) may be further provided, and the output current of the current output end of the second bias current source 14 is also I_B. A current output terminal of the second bias current source 14 is coupled to a current input terminal of the first current mirror circuit, and the other terminal of the second bias current source 14 inputs the power supply voltage VCC.

Referring to fig. 3, a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention is shown. After the second bias current source 14 is set, the current flowing through the second NMOS transistor MN2 is:

I₁+I_B＝I_L/M-(M-1/M)×I_B+I_B＝I_L/M+I_B/M。

continuing with the above example, at this time, I_LThe error introduced is only 0.0002%, which is negligible.

The driving overcurrent detection circuit when the driving transistor is an NMOS transistor will be described in detail below.

Referring to fig. 4, an embodiment of the present invention provides another driving overcurrent detection circuit. The driving tube is an NMOS tube MND, and the MOS tube is a seventh NMOS tube MN 7. The gate of the driving transistor MND and the gate of the seventh NMOS transistor MN7 both input the control signal VG. When the control signal VG is at a high level, the driving transistor MND and the seventh NMOS transistor MN7 are both in a conducting state.

In fig. 4, the operational amplifier circuit includes an error amplifier circuit a1 and a fourth PMOS transistor MP4, wherein:

the first input end of the error amplifying circuit is coupled with the drain electrode of the driving tube MND; the second input end of the error amplifying circuit is coupled to the drain of the seventh NMOS transistor MN 7; the output end of the error amplifying circuit is coupled with the grid electrode of the fourth PMOS tube MP 4;

a fourth PMOS transistor MP4, the gate of which is coupled to the output terminal of the error amplifying circuit; the drain electrode is coupled with the second input end '+' of the error amplifying circuit; the source electrode is the output end of the operational amplification circuit.

The fourth PMOS transistor MP4 and the error amplifying circuit form a negative feedback loop.

The source of the seventh NMOS transistor MN7 is coupled to ground, the gate inputs the control signal, and the drain is coupled to the second input "+" of the error amplifier circuit;

a first current mirror circuit, wherein the current input end is coupled with the output end of the feedback circuit in the operational amplification circuit, and the current output end is coupled with the output end of the reference current source 11;

a reference current source 11, having one end coupled to ground and an output end coupled to the current output end of the first current mirror circuit.

In a specific application, the drain of the driving tube MPD is the output OUT of the driving tube, and may be connected to a driving load.

In specific implementation, the driving transistor MND and the seventh NMOS transistor MN7 are NMOS transistors of the same type and are disposed adjacent to each other on the same chip, so as to ensure that the process, temperature, and power supply voltage deviations have the same effect on the seventh NMOS transistor MN7 and the driving transistor MND.

In a specific implementation, the width-to-length ratio of the driving tube MND is different from that of the seventh NMOS tube MN7, and the width-to-length ratio of the driving tube MND is greater than that of the seventh NMOS tube MN 7. In the embodiment of the present invention, the width-to-length ratio of the driving tube MND is M times of the width-to-length ratio of the seventh NMOS tube MN7, where M > 1.

In a specific application, the width-to-length ratio of the driving transistor MND may exceed that of the seventh NMOS transistor MN7 by several orders of magnitude. In other words, the width-to-length ratio of the driving tube MND may be tens of times or more of the width-to-length ratio of the seventh NMOS tube MN 7. In an embodiment of the present invention, the width-to-length ratio of the driving tube MND is 5000 times that of the seventh NMOS tube MN 7.

In one implementation, the gate of the driving transistor MND may be coupled to the gate of the seventh NMOS transistor MN7, and the control signal is input to the gate of the driving transistor MND and the gate of the seventh NMOS transistor MN 7. The driving tube MND can be controlled to be turned off or turned on by the control signal, and the seventh NMOS tube MN7 can be controlled to be turned off or turned on.

Since the driving tube MND and the seventh NMOS tube MN7 are NMOS tubes of the same type, when the driving tube MND is turned off under the action of the control signal, the seventh NMOS tube MN7 is also turned off; on the contrary, when the driving transistor MND is turned on by the control signal, the seventh NMOS transistor MN7 is also turned on.

In the embodiment of the present invention, the control signal may be a high level signal VG. Under the action of the high level signal VG, the driving transistor MND and the seventh NMOS transistor MN7 are both in a conducting state.

In a specific implementation, the first current mirror circuit may include a fifth PMOS transistor MP5 and a sixth PMOS transistor MP 6.

The gate of the fifth PMOS transistor MP5 is coupled to the drain of the fifth PMOS transistor MP5, i.e., the gate of the fifth PMOS transistor MP5 is coupled to the drain thereof; the drain of the fifth PMOS transistor MP5 is the current input terminal of the first current mirror circuit, and is coupled to the source of the fourth PMOS transistor MP 4; the source of the fifth PMOS transistor MP5 receives the power supply voltage VCC.

The drain of the sixth PMOS transistor MP6 is the current output terminal of the first current mirror circuit, and is coupled to the output terminal of the reference current source 11 and the input terminal of the determination result output terminal OC of the driving overcurrent detection circuit; the gate of the sixth PMOS transistor MP6 is coupled to the gate of the fifth PMOS transistor MP 5; the source of the sixth PMOS transistor MP6 receives the power supply voltage VCC.

In the embodiment of the present invention, the width-to-length ratio of the fifth PMOS transistor MP5 is N times the width-to-length ratio of the sixth PMOS transistor MP6, where N > 1.

In a specific implementation, the output of the reference current source 11 may be presetThe current is applied. The setting of the output current of the reference current source 11 may be associated with three of: critical current value I of MND overcurrent of driving tube_maxThe ratio M of the width-length ratio of the driving tube MND to the width-length ratio of the seventh NMOS tube MN7, and the ratio N of the width-length ratio of the fifth PMOS tube MP5 to the width-length ratio of the sixth PMOS tube MP 6.

In the embodiment of the present invention, the output current of the reference current source 11 is set as: i is_max/(M.times.N). When the output current of the current output end of the first current mirror circuit is greater than the output current of the reference current source 11, it can be determined that the driving tube MND has an overcurrent condition; otherwise, the MND is judged to have no overcurrent condition.

From the above embodiments of the present invention, the driving tube MND and the seventh NMOS transistor MN7 are the same type NMOS transistor, and the production processes of the two NMOS transistors are the same, so the deviation of the power voltage and the temperature has the same influence on the driving tube MND and the seventh NMOS transistor MN 7. When the gate of the driving transistor MND and the gate of the seventh NMOS transistor MN7 both input the high level signal VG, the driving transistor MND and the seventh NMOS transistor MN7 are both turned on. Through the width-length ratio of the driving tube MND and the width-length ratio of the seventh NMOS tube MN7, the ratio between the resistance value of the driving tube MND and the resistance value of the seventh NMOS tube MN7 can be determined.

In the embodiment of the present invention, the width-length ratio of the driving tube MND is M times of the width-length ratio of the seventh NMOS transistor MN7, and therefore, the resistance R of the driving tube MND_MNDResistance value R of the seventh NMOS transistor MN7_MN7The ratio between is 1/M, that is: r_MND/R_MN7＝1/M。

When the current flowing through the drive tube MND is I_LIn time, the output voltage of the driving tube MND is known from ohm's law as follows:

V_OUT＝VCC-I_L×R_MND； (4)

therefore, the voltage of the first input end of the error amplifying circuit is VCC-I_L×R_MND。

At this time, the input voltage of the second input terminal of the error amplifying circuit is:

V₁＝V_OUT＝VCC-I_L×R_MND＝VCC-I₁×R_MN7； (5)

wherein, I₁Is the output current of the drain electrode of the seventh NMOS transistor MN 7.

From the above equation (4) and the above equation (5), it can be known that: i is_L×R_MND＝I₁×R_MN7。

Due to R_MND/R_MN71/M, so that: i is₁/I_L＝1/M。

I₁The current is input to the current input terminal of the first current mirror circuit, that is: the drain of the fifth PMOS transistor MP5 has a current of I₁. According to the mirror relationship between the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, since the width-to-length ratio of the fifth PMOS transistor MP5 is N times the width-to-length ratio of the sixth PMOS transistor MP6, the current at the drain of the sixth PMOS transistor MP6 is I₁/N。

When the current of the drain of the sixth PMOS transistor MP6 is larger than the output current I of the reference current source 11_RWhen, i.e. when I₁/N＞I_RAnd when the current is detected, the judgment result output end OC of the driving overcurrent detection circuit outputs a logic high level. At this time, it is determined that the overcurrent condition occurs in the drive pipe MND.

On the contrary, when the current of the drain of the sixth PMOS transistor MP6 is smaller than the output current of the reference current source 11, the output result of the determination result output terminal OC of the driving overcurrent detection circuit is a logic low level, and at this time, it is determined that the driving transistor MND has no overcurrent condition.

In a specific implementation, a current flowing through the driving tube MND may have a glitch, which causes an error in the determination result output by the determination result output terminal OC of the final current detection circuit. Therefore, for avoiding the influence of the burr of the electric current on the driving tube MND to the judgment result, in the embodiment of the present invention, the trigger 12 can be further provided between the current output end of the first current mirror circuit and the judgment result output end OC. Since a certain threshold and hysteresis are required for triggering the trigger 12, the influence of the glitch of the current on the driving tube MND on the judgment result can be effectively avoided.

Therefore, when the trigger 12 is added, when the level of the output signal of the judgment result output end OC is a logic low level, the condition that the driving tube MND has overcurrent is judged; and when the level of the output signal of the judgment result output end OC is a logic high level, judging that the MND has no overcurrent condition.

In a specific implementation, the error amplifying circuit may further include a bias current input terminal, and the driving overcurrent detecting circuit may further include a third bias current source 15 (as shown in fig. 5), where:

and a current output terminal of the third bias current source 15 is coupled to the bias current input terminal of the error amplifying circuit, and the other terminal is coupled to ground.

The error amplifying circuit may further include a second current mirror bias, a current input terminal of the second current mirror bias is a bias current input terminal of the error amplifying circuit, that is, the current input terminal of the second current mirror bias is coupled to a current output terminal of the third bias current source 15; and the current output end biased by the second current mirror is the output end of the error amplifying circuit. The second current mirror bias may mirror the third bias current output from the third bias current source 15 to the output terminal of the error amplification circuit and output the mirrored third bias current.

Referring to fig. 5, a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention is shown.

In fig. 5, the error amplifying circuit includes: an eighth NMOS transistor, a ninth NMOS transistor, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a ninth PMOS transistor MP9, wherein:

the gate and the drain of the eighth NMOS transistor MN8 are coupled, the source of the eighth NMOS transistor MN8 is coupled to the drain of the driver transistor MND, and the drain of the eighth NMOS transistor MN8 is coupled to the drain of the seventh PMOS transistor MP 7; the source electrode of the eighth NMOS transistor MN8 is a first input end of the error amplifying circuit;

a source of the ninth NMOS transistor MN9 is coupled to a drain of the seventh NMOS transistor MN7, a gate of the ninth NMOS transistor MN9 is coupled to a gate of the eighth NMOS transistor MN8, and a drain of the ninth NMOS transistor MN9 is coupled to a drain of the eighth PMOS transistor MP 8; the source electrode of the ninth NMOS transistor MN9 is a second input end of the error amplifying circuit;

the gate of the seventh PMOS transistor MP7 is coupled to the gate of the eighth PMOS transistor MP8, and the source of the seventh PMOS transistor MP7 is coupled to the power supply voltage VCC;

the gate of the eighth PMOS transistor MP8 is coupled to the gate of the seventh PMOS transistor MP7, and the drain of the eighth PMOS transistor MP8 is the output terminal of the error amplifying circuit and the current output terminal biased by the second current mirror; the source of the eighth PMOS transistor MP8 is coupled to the power supply voltage VCC;

the drain of the ninth PMOS transistor MP9 is a current input terminal biased by the second current mirror, the gate of the ninth PMOS transistor MP9 is coupled to the drain of the ninth PMOS transistor MP9, the gate of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8, and the source of the ninth PMOS transistor MP9 is inputted with the power voltage VCC.

In a specific implementation, the output current of the third bias current source 15 is I_B. In the embodiment of the present invention, the output current I of the third bias current source 15_BOn the μ a scale.

After the third bias current source 15 is provided, the ninth PMOS transistor MP9 may mirror the output current of the third bias current source 15 to the drain of the eighth PMOS transistor MP 8. At this time, I_B+I_L＝(I_B+I₁) Xm, so that the current flowing through the fourth PMOS transistor MP4 is:

I₁＝[I_L-(M-1)×I_B]＝I_L/M-(M-1)/M×I_B (6)。

in the formula (6), (M-1)/MXI_BAnd is generally negligible.

For example, when the current flowing through the driving tube MND is set to 500mA, M is 1000, I_B1 muA, then I₁There is an error of 0.2%, i.e. I_LThe error of (2) is 0.2%.

In order to reduce the error, in the embodiment of the present invention, a fourth bias current source 16 (as shown in fig. 6) may be further provided, and the output current of the current output terminal of the fourth bias current source 16 is also I_B. A current output terminal of the fourth bias current source 16 is coupled to a current input terminal of the first current mirror circuit, and the other terminal of the fourth bias current source 16 is coupled to ground.

Referring to fig. 6, a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention is shown. After the fourth bias current source 16 is set, the current flowing through the fourth PMOS transistor MP4 is:

I₁+I_B＝I_L/M-(M-1/M)×I_B+I_B＝I_L/M+I_B/M。

In specific implementation, in some special scenarios, it is necessary to determine that the output of the result output terminal OC is a low voltage domain signal. In the embodiment of the present invention, a second current mirror circuit may be further provided. Referring to fig. 7, a circuit structure diagram of another driving overcurrent detecting circuit according to an embodiment of the present invention is shown.

In fig. 7, the second current mirror circuit includes a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11, wherein:

the gate of the tenth NMOS transistor MN10 is coupled to the drain of the tenth NMOS transistor MN10, the drain of the tenth NMOS transistor MN10 is the current input terminal of the second current mirror circuit, the gate of the tenth NMOS transistor MN10 is coupled to the gate of the eleventh NMOS transistor MN11, and the source of the tenth NMOS transistor MN10 is coupled to ground;

the drain of the eleventh NMOS transistor MN11 is the current output terminal of the second current mirror circuit, the gate of the eleventh NMOS transistor MN11 is coupled to the gate of the tenth NMOS transistor MN10, and the source of the eleventh NMOS transistor MN11 is coupled to ground.

The output current of the first current mirror circuit is mirrored in equal proportion or in a certain multiple through the second current mirror circuit, and then compared with the output current of the reference current source 11. The output current of the reference current source 11 is the current output from the low voltage domain, and the flip-flop 12 is supplied with power from the low voltage power supply, so that the highest potential output from the determination result output terminal OC is the potential of the low voltage power supply.

In fig. 7, the output terminal of the reference current source 11 is coupled to the current output terminal of the second current mirror circuit, and the other terminal of the reference current source is connected to the power supply voltage VCC.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A drive overcurrent detection circuit, comprising: the MOS transistor of the same type as the driving transistor, an operational amplifier circuit, a first current mirror circuit and a reference current source, wherein:

the first input end of the operational amplifier circuit is coupled with the drain electrode of the driving tube, the second input end of the operational amplifier circuit is coupled with the drain electrode of the MOS tube, and the output end of the operational amplifier circuit is coupled with the current input end of the first current mirror circuit;

the grid electrode of the driving tube inputs a control signal;

the grid of the MOS tube inputs a control signal; when the driving tube and the MOS tube are both PMOS tubes, the source electrode of the driving tube and the source electrode of the MOS tube are both inputted with power supply voltage; when the driving tube and the MOS tube are both NMOS tubes, the source electrode of the driving tube and the source electrode of the MOS tube are both coupled with the ground; the output current of the operational amplification circuit is related to the current flowing on the driving tube;

the current output end of the first current mirror circuit is coupled with the output end of the reference current source and the judgment result output end of the driving overcurrent detection circuit; and when the output current of the current output end of the first current mirror is larger than the output current of the reference current source, judging that the driving tube is overcurrent.

2. The driving overcurrent detection circuit according to claim 1, wherein the driving transistor is a PMOS transistor, and the MOS transistor is a first PMOS transistor.

3. The driving overcurrent detection circuit according to claim 2, wherein the first current mirror circuit includes: second NMOS pipe and third NMOS pipe, wherein:

the grid electrode of the second NMOS tube is coupled with the drain electrode, the drain electrode is the current input end of the first current mirror circuit, and the source electrode is coupled with the ground;

and the drain electrode of the third NMOS tube is the current output end of the first current mirror circuit, the grid electrode of the third NMOS tube is coupled with the grid electrode of the second NMOS tube, and the source electrode of the third NMOS tube is coupled with the ground.

4. The driving overcurrent detection circuit of claim 3 wherein the width-to-length ratio of the second NMOS transistor is N times the width-to-length ratio of the third NMOS transistor, N > 1.

5. The driving overcurrent detection circuit according to claim 2, wherein the operational amplifier circuit includes: first NMOS pipe and error amplification circuit, wherein:

the first input end of the error amplifying circuit is the first input end of the operational amplifying circuit, the second input end of the error amplifying circuit is the second input end of the operational amplifying circuit, and the output end of the error amplifying circuit is coupled with the grid electrode of the first NMOS tube;

and the drain electrode of the first NMOS tube is coupled with the second input end of the error amplifying circuit, and the source electrode of the first NMOS tube is the output end of the operational amplifying circuit.

6. The driving overcurrent detection circuit of claim 5, further comprising: a first bias current source, wherein:

a current output end of the first bias current source is coupled with a bias current input end of the error amplification circuit;

the error amplifying circuit further comprises a first current mirror bias; the first current mirror is biased, the current input end is a bias current input end of the error amplification circuit, the current output end is an output end of the error amplification circuit, and the first current mirror is suitable for mirroring the first bias current output by the first bias current source to the output end of the error amplification circuit and outputting the mirrored first bias current.

7. The driving overcurrent detection circuit of claim 6, wherein the error amplification circuit comprises: second PMOS pipe, third PMOS pipe, fourth NMOS pipe, fifth NMOS pipe and sixth NMOS pipe, wherein:

the grid electrode of the second PMOS tube is coupled with the drain electrode of the second NMOS tube, the source electrode of the second PMOS tube is coupled with the drain electrode of the driving tube, and the drain electrode of the second PMOS tube is coupled with the drain electrode of the fourth NMOS tube;

the source electrode of the third PMOS tube is coupled with the drain electrode of the first PMOS tube, the grid electrode of the third PMOS tube is coupled with the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is coupled with the drain electrode of the fifth NMOS tube;

the grid electrode of the fourth NMOS tube is coupled with the grid electrode of the fifth NMOS tube, and the source electrode of the fourth NMOS tube is coupled with the ground;

the source electrode of the fifth NMOS tube is coupled with the ground, and the drain electrode of the fifth NMOS tube is the output end of the error amplifying circuit and the current output end biased by the first current mirror;

the drain of the sixth NMOS transistor is a current input end biased by the first current mirror, the grid of the sixth NMOS transistor is coupled with the grid of the fourth NMOS transistor, the grid of the fifth NMOS transistor and the drain of the sixth NMOS transistor, and the source of the sixth NMOS transistor is coupled with the ground.

8. The driving overcurrent detection circuit of claim 6, further comprising: and a current output end of the second bias current source is coupled with the current input end of the first current mirror circuit.

9. The driving overcurrent detection circuit of claim 1, wherein the driving transistor is an NMOS transistor, and the MOS transistor is a seventh NMOS transistor.

10. The driving overcurrent detection circuit according to claim 9, wherein the first current mirror circuit comprises: fifth PMOS pipe and sixth PMOS pipe, wherein:

the grid electrode and the drain electrode of the fifth PMOS tube are coupled, the drain electrode is the current input end of the first current mirror circuit, and the source electrode inputs the power supply voltage;

and the drain of the sixth PMOSS tube is the current output end of the first current mirror circuit, the grid of the sixth PMOSS tube is coupled with the grid of the fifth PMOS tube, and the source of the sixth PMOSS tube inputs the power supply voltage.

11. The driving overcurrent detection circuit of claim 10, wherein a width-to-length ratio of the fifth PMOS transistor is N times a width-to-length ratio of the sixth PMOS transistor, N > 1.

12. The driving overcurrent detection circuit according to claim 9, wherein the operational amplifier circuit includes: fourth PMOS pipe and error amplification circuit, wherein:

the first input end of the error amplifying circuit is the first input end of the operational amplifying circuit, the second input end of the error amplifying circuit is the second input end of the operational amplifying circuit, and the output end of the error amplifying circuit is coupled with the grid electrode of the fourth PMOS tube;

and the drain electrode of the fourth PMOS tube is coupled with the second input end of the error amplifying circuit, and the source electrode of the fourth PMOS tube is the output end of the operational amplifying circuit.

13. The driving overcurrent detection circuit of claim 12, further comprising: a third bias current source, wherein:

a current output end of the third bias current source is coupled with a bias current input end of the error amplification circuit;

the error amplifying circuit further comprises a second current mirror bias; and the second current mirror is biased, the current input end is a bias current input end of the error amplification circuit, and the current output end is an output end of the error amplification circuit, and is suitable for mirroring the third bias current output by the third bias current source to the output end of the error amplification circuit and outputting the mirrored third bias current.

14. The driving overcurrent detection circuit of claim 13, wherein the error amplification circuit comprises: eighth NMOS pipe, ninth NMOS pipe, seventh PMOS pipe, eighth PMOS pipe and ninth PMOS pipe, wherein:

the grid electrode of the eighth NMOS tube is coupled with the drain electrode, the source electrode of the eighth NMOS tube is coupled with the drain electrode of the driving tube, and the drain electrode of the eighth NMOS tube is coupled with the drain electrode of the seventh PMOS tube;

the source of the ninth NMOS tube is coupled with the drain of the seventh NMOS tube, the gate of the ninth NMOS tube is coupled with the gate of the eighth NMOS tube, and the drain of the ninth NMOS tube is coupled with the drain of the eighth PMOS tube;

the grid electrode of the seventh PMOS tube is coupled with the grid electrode of the eighth PMOS tube, and the source electrode of the seventh PMOS tube inputs the power supply voltage;

the source electrode of the eighth PMOS tube inputs the power supply voltage, and the drain electrode of the eighth PMOS tube is the output end of the error amplifying circuit and the current output end biased by the second current mirror;

the drain of the ninth PMOS transistor is a current input end biased by the second current mirror, the gate of the ninth PMOS transistor is coupled to the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor and the drain of the ninth PMOS transistor, and the source of the ninth PMOS transistor inputs the power voltage.

15. The driving overcurrent detection circuit of claim 12, further comprising: and a current output end of the fourth bias current source is coupled with the current input end of the first current mirror circuit.

16. The driving overcurrent detection circuit of claim 12, further comprising:

a second current mirror circuit; the current input end of the second current mirror circuit is coupled with the current output end of the first current mirror circuit, and the current output end of the second current mirror circuit is coupled with the output end of the reference current source.

17. The driving overcurrent detection circuit of claim 16, wherein the second current mirror circuit comprises: tenth NMOS pipe and eleventh NMOS pipe, wherein:

a grid electrode of the tenth NMOS tube is coupled with a drain electrode, the drain electrode is a current input end of the second current mirror circuit, the grid electrode is coupled with a grid electrode of the eleventh NMOS tube, and a source electrode is coupled with the ground;

and the drain electrode of the eleventh NMOS tube is the current output end of the second current mirror circuit, and the source electrode of the eleventh NMOS tube is coupled with the ground.

18. The driving overcurrent detection circuit of claim 1, further comprising: and the input end of the trigger is coupled with the current output end of the first current mirror circuit, and the output end of the trigger is coupled with the judgment result output end of the driving overcurrent detection circuit.

19. The drive overcurrent detection circuit of claim 18 wherein the flip-flop comprises a schmitt trigger.

20. The driving overcurrent detection circuit of claim 1 wherein the width-to-length ratio of the drive transistor is M times the width-to-length ratio of the MOS transistor, M > 1.

21. The driving overcurrent detection circuit of claim 1, wherein the reference current source is a current source with an adjustable output current.