CN209821604U

CN209821604U - Multichannel time-to-digital converter and photoelectric detection device

Info

Publication number: CN209821604U
Application number: CN201920720513.8U
Authority: CN
Inventors: 张玺; 徐青; 王麟; 谢庆国
Original assignee: Hubei Jing Bang Technology Co Ltd
Current assignee: Hubei Ruiguang Technology Co ltd
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2019-12-20
Anticipated expiration: 2029-05-17

Abstract

The utility model discloses a multichannel time digital converter and photoelectric detection device, this multichannel time digital converter can include a plurality of timing channels to every timing channel all includes: the time measurement device comprises a first input end used for receiving a time signal to be measured, a second input end used for receiving a reference voltage signal, a third input end used for receiving a reference clock signal and a time stamp output end used for outputting a time stamp obtained by measuring the time signal to be measured according to the reference voltage signal and the reference clock signal, wherein the second input ends of a plurality of timing channels are connected in parallel. Through utilizing the utility model provides a multichannel time digital converter can reduce shared chip area, improves time measurement accuracy.

Description

Multichannel time-to-digital converter and photoelectric detection device

Technical Field

The utility model relates to an integrated circuit technical field, in particular to multichannel time-to-digital converter and photoelectric detection device.

Background

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

The time-to-digital converter (TDC) can be widely used for time measurement of photoelectric signals in the technical fields of Positron Emission Tomography (PET), laser ranging and the like. In these fields of technology, it is generally required that the conversion accuracy of the TDC can reach 100ps or less to ensure sufficient sensitivity of the photodetector. However, due to the difference between the length of the signal transmission path and the parasitic parameters, the time information of the time signal to be measured may be deteriorated before reaching the TDC, so in the prior art, the TDC and the pixel array are usually integrated on the same chip when manufacturing the photodetector to reduce the influence of the signal transmission path on the time signal to be measured.

In order to further improve the spatial resolution of the photodetector, a plurality of individual TDCs are commonly arranged in parallel, which results in a larger chip area occupied by the TDCs, affects the effective detection area of the photodetector, and reduces the sensitivity, and there are more input ports and output ports of the existing high-precision TDCs, for example, as shown in fig. 1, the TDC 610 includes a coarse tuning circuit 610, a fine tuning circuit 620 and a phase detector 630, wherein the coarse tuning circuit 610 includes a first digitally controlled oscillator 611 and a first counting circuit 612 which are connected to each other, and the fine tuning circuit 620 includes a second digitally controlled oscillator 621 and a second counting circuit 622 which are connected to each other. The TDC 610 includes the following ports: 2 trigger signal inputs, a multi-bit control code input, a multi-bit count output, which inputs and outputs and corresponding connecting lines occupy a large chip area, which may make it difficult to integrate with the pixel array on the same chip and possibly reduce the time measurement accuracy.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a multichannel time-to-digital converter and photoelectric detection device to solve at least one technical problem who exists among the prior art.

In order to solve the above technical problem, the present invention provides a multi-channel time-to-digital converter, which may include a plurality of timing channels, and each of the timing channels includes: the time measurement device comprises a first input end used for receiving a time signal to be measured, a second input end used for receiving a reference voltage signal, a third input end used for receiving a reference clock signal and a time stamp output end used for outputting a time stamp obtained by measuring the time signal to be measured according to the reference voltage signal and the reference clock signal, wherein the second input ends of a plurality of timing channels are connected in parallel.

Optionally, each of the timing channels comprises:

a logic control circuit on which the first input terminal and the third input terminal are provided, and which generates a response signal corresponding to the received time signal to be measured from the received reference clock signal;

a plurality of oscillators, on which the second input terminals are arranged, for generating corresponding multi-path oscillation signals according to the multi-path trigger signals received from the logic control circuit;

the phase detector is used for comparing the phase relationship among the multiple paths of the oscillation signals generated by the oscillators to determine the difference value among the starting times of the multiple paths of the oscillation signals;

a counting circuit for counting a plurality of the oscillation signals generated by the plurality of the oscillators according to a control signal received from the logic control circuit and outputting a time stamp containing count data thereof,

wherein the response signal comprises a plurality of paths of the trigger signal, a first reset signal for resetting the phase detector and the control signal.

Optionally, the logic control circuit comprises a latch, a multi-bit counter and a combinational logic circuit connected to each other.

Optionally, the first reset terminal of the latch is connected to the first output terminal of the combinational logic circuit, one of a non-inverting output terminal and an inverting output terminal thereof is connected to the second reset terminal of the multi-bit counter, and the other of the non-inverting output terminal and the inverting output terminal is connected to a first oscillator of the plurality of oscillators to provide a first trigger signal to the first oscillator.

Optionally, the combinational logic circuit comprises:

the first output end is connected with the first reset end of the latch and the phase detector to output the first reset signal to the latch and the phase detector;

a second output terminal connected to a remaining oscillator of the plurality of oscillators other than the first oscillator to provide a second trigger signal to the remaining oscillator, wherein the first trigger signal and the second trigger signal are included in a plurality of the trigger signals;

a third output terminal connected with the counting circuit to output the control signal to the counting circuit.

Optionally, the counting circuit comprises:

a plurality of counters which are correspondingly connected with the plurality of oscillators and are used for counting a plurality of paths of oscillation signals generated by the plurality of oscillators and resetting according to a second reset signal received from the logic control circuit;

a shift register configured to output a time stamp containing count data of a plurality of the counters according to a shift clock signal and a shift control signal received from the logic control circuit,

wherein the second reset signal, the shift clock signal, and the shift control signal are included in the control signal and are each generated by the logic control circuit according to the reference clock signal.

Optionally, the timestamp further comprises a preset start indication bit and/or a check indication bit.

Optionally, each of the timing channels further includes an oscillation transmission circuit for generating a corresponding plurality of count signals according to a plurality of the oscillation signals received from the plurality of oscillators and the electric signal received from the phase detector, and sending the generated plurality of count signals to the counting circuit.

Optionally, the multichannel time-to-digital converter further comprises:

a global counter for receiving said reference clock signal and generating a corresponding global clock count, and having a clock input connected in parallel with said third input of each said clocking channel; and/or

A voltage generating circuit for receiving the reference clock signal and generating the reference voltage signal to control a difference between start times of a plurality of the oscillation signals generated by the plurality of the oscillators in each of the timing channels, and a voltage output terminal thereof is connected to the second input terminal in each of the timing channels,

wherein the clock input terminal of the global counter is connected in parallel with the clock input terminal of the voltage generation circuit.

The utility model also provides a photoelectric detection device, this photoelectric detection device can include pixel array and above-mentioned multichannel time digital converter, and multichannel time digital converter can set up pixel array's inside or near it.

By the above the technical scheme the utility model provides a it is visible, the utility model discloses a with each timing channel design among the multichannel time digital converter only including ports such as three input and a time stamp output and all timing channels be used for receiving reference voltage signal's second input and parallelly connected each other, this can reduce the shared chip area of multichannel time digital converter to can realize the purpose of integrating in same chip with pixel array, and can also reduce system complexity.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a schematic diagram of a TDC in the prior art;

fig. 2 is a schematic structural diagram of a multichannel time-to-digital converter provided by the present invention;

FIG. 3 is a schematic diagram of a timing channel in a multi-channel time-to-digital converter;

FIG. 4 is a schematic diagram of a logic control circuit in the timing channel;

FIG. 5 is a schematic diagram of another logic control circuit in the timing channel;

FIG. 6 is a schematic diagram of an oscillator in the timing channel;

FIG. 7 is a schematic diagram of another timing channel in a multi-channel time-to-digital converter;

FIG. 8 is a schematic diagram of an oscillating transmission circuit in a timing channel;

FIG. 9 is a timing chart corresponding to one timing channel obtained in actual operation;

fig. 10 is a schematic structural diagram of another multichannel time-to-digital converter provided by the present invention;

fig. 11 is a schematic structural diagram of another multichannel time-to-digital converter provided by the present invention;

fig. 12 is a schematic structural diagram of another multichannel time-to-digital converter provided by the present invention;

fig. 13 is a schematic structural diagram of a photodetection device provided by the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings in the present application, and it is obvious that the described embodiments are only used for explaining some embodiments of the present invention, but not all embodiments, and are not intended to limit the scope of the present invention or the claims. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected/coupled" to another element, it can be directly connected/coupled to the other element or intervening elements may also be present. The term "connected/coupled" as used herein may include electrical and/or mechanical physical connections/couplings. The term "comprises/comprising" as used herein refers to the presence of features, steps or elements, but does not preclude the presence or addition of one or more other features, steps or elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

In addition, in the description of the present invention, the terms "first", "second", and the like are used for descriptive purposes only and to distinguish similar objects, and there is no order of precedence between them, nor should they be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Furthermore, in the description of the present invention, the term "active level" may refer to a low level or a high level, which corresponds to an active low level or an active high level. Accordingly, the term "inactive level" may refer to a high level or a low level, as opposed to an "active level". Also, the active level and the inactive level of each element may be set according to actual circumstances.

The following describes the multi-channel time-to-digital converter and the optical detector in detail with reference to the accompanying drawings.

As shown in fig. 2, the present invention provides a multichannel time-to-digital converter 1000, which may include a plurality of timing channels 100, each timing channel 100 may be configured to independently generate a corresponding timestamp in response to a respective received time signal to be measured, and may each include the following ports: a first input terminal I1 for receiving a time signal to be measured; a second input terminal I2 for receiving a reference voltage signal and comprising a plurality of interfaces; a third input terminal I3 for receiving a reference clock signal; and a time stamp output terminal TS for outputting a time stamp obtained by measuring the time signal to be measured from the reference voltage signal and the reference clock signal. Fewer ports per timing channel 100 in the multi-channel time-to-digital converter may reduce the chip area it occupies. Moreover, the second inputs of the plurality of timing channels 100 are connected in parallel with each other, which can reduce the chip area occupied by the wiring.

As shown in fig. 3, each timing channel 100 may include a logic control circuit 110, a plurality of oscillators 120, a phase detector 130, and a counting circuit 140 connected to one another. Among them, the logic control circuit 110 may be provided with the first input terminal I1 and the third input terminal I3 or be connected with the first input terminal I1 and the third input terminal I3, and may be configured to generate a response signal corresponding to the received time signal to be measured according to the received reference clock signal, and the response signal may include a multi-way trigger signal (e.g., a pulse signal) for triggering the plurality of oscillators 120, a first reset signal for resetting the phase detector 130, a control signal for controlling the counting circuit 140, and the like. The plurality of oscillators 120 may be connected to the second input terminal I2 and configured to generate corresponding multiple oscillation signals according to multiple trigger signals received from the logic control circuit 110. Phase detector 130 may be configured to compare the phase relationship between the multiple oscillating signals generated by plurality of oscillators 120 to determine the difference between the start times of the multiple oscillating signals. The counting circuit 140 may be configured to count the multiple oscillation signals generated by the plurality of oscillators 120 according to a control signal received from the logic control circuit 110 and output a time stamp containing count data thereof.

According to the difference between the start times of the multiple oscillation signals determined by the phase detector 130, the timestamp output by the counting circuit 140, and the obtained global clock count, the complete time measured by the timing channel 100 can be determined, and the time difference between the time signals to be measured of any two timing channels can be obtained.

The logic control circuit 110 may be a common monostable flip-flop circuit, or may be a logic gate circuit including a latch (e.g., SR latch) 1101, a multi-bit counter 1102, a combinational logic circuit 1103, and the like connected to each other, as shown in fig. 4 and 5. Wherein the latch 1101 may be configured to receive a time signal to be measured and output a first trigger signal for triggering one oscillator (e.g., a first oscillator) 120; the multi-bit counter 1102 may be controlled by the latch 1101 and configured to count the received reference clock signal when the first trigger signal output by the latch 1101 is an active level (e.g., a high level), and reset when the first trigger signal output by the latch 1101 is an inactive level; the combinational logic circuit 1103 may generate corresponding output signals according to the counting state of the multi-bit counter 1103, and the output signals may include a second trigger signal for triggering other oscillators (e.g., a second oscillator) of the plurality of oscillators 120, a first reset signal for resetting the phase detector 130 and the latch 1101, a control signal for controlling the counting circuit 140, and the like, and may also include other signals. Wherein the first trigger signal, the second trigger signal, the first reset signal, and the control signal constitute a response signal generated in response to the time signal to be measured, and the first trigger signal and the second trigger signal are included in the multi-path trigger signal. It should be noted that the second trigger signal may include one or more signals, the specific number of which may be determined according to the number of the oscillators 120, and when it includes multiple signals, each signal may be at a different level.

The latch 1101 may include an SR latch, and may also include a logic circuit configured from a D latch and having a function equivalent to that of the SR latch. The latch 1101 may comprise a first input I1 for receiving a time signal to be measured, for receiving a reset inputFirst reset terminal R1, non-inverting output terminal Q, and inverting output terminal QWherein the in-phase output terminal Q and the reverse phase output terminalOne (e.g., the in-phase output Q) may be connected to the first oscillator 120 and the other (e.g., the anti-phase output Q)) May be connected to a second reset terminal R2 of the multi-bit counter 1102. Also, the non-inverting output Q and the inverting output Q are both stable at the latch 1101I.e. when the in-phase output terminal Q outputs a high level, the inverting output terminalOutput low level or vice versa. It should be noted that the latch 1101 changes state only when a rising edge or a falling edge of the time signal to be measured is received, and the latch 1101 may remain in the current state, i.e., in a stable state, until no rising edge or falling edge of the time signal to be measured is received.

The multi-bit counter 1102 may include a third input I3 to receive a reference clock signal, a second reset terminal R2 to receive a reset input, and a plurality of count outputs (e.g., Q)₀、Q₁、Q₂、Q₃……Q_n-1And n is a positive integer greater than 1). The multi-bit counter 1102 may be a multi-bit binary counter, a multi-bit decimal counter, or a multi-bit other binary counter, and may also be a multi-bit ring counter or a shift register type counter, etc., but is not limited thereto.

The logic function of the multi-bit counter 1102 is as follows: when the second reset terminal R2 is active high or low, the multi-bit counter 1102 is in an initial counting state, and its multiple counting outputs generate corresponding output signals according to a preset scale (e.g., 0 … 000, where 0 may represent high or low); when the second reset terminal R2 is at a low level, the multi-bit counter 1102 starts counting in a preset counting manner (e.g., an increasing or decreasing manner) in a current counting state (e.g., an initial counting state) every time the third input terminal I3 receives a rising edge or a falling edge of the reference clock signal, and the plurality of counting output terminals generate corresponding output signals (e.g., 0 … 001). The initial count state may be 0 … 000, may be 1 … 111, or may be any other count state. The preset bin is related to the type of multi-bit counter 1102, which may be binary, decimal, etc., for example.

The combinational logic circuit 1103 may include a count input connected to at least one count output of the multi-bit counter 1102. The number of connections and the connection manner between the count input terminal of the combinational logic circuit 1103 and the count output terminal of the multi-bit counter 1102 may be determined according to the width of the pulse signal (i.e., the first trigger signal) that needs to be generated. Preferably, the number of the counting input ends is the same as that of the counting output ends, and the counting input ends and the counting output ends are all correspondingly connected. The combinational logic circuit 1103 may further include: a first output terminal O1, which may be connected to the first reset terminal R1 of the latch 1101 and the phase detector 130 to output a first reset signal to the latch 1101 and the phase detector 130, which may be directly connected to the first reset terminal R1 and the phase detector 130, as shown in fig. 4, or indirectly connected to the first reset terminal R1 and the phase detector 130 through a not gate, as shown in fig. 5; a second output terminal O2 connected to the remaining oscillators of the plurality of oscillators 120 to provide a second trigger signal to the remaining oscillators, which may include a plurality of interfaces to be connected to the corresponding oscillators, respectively, or which may be plural; and a third output terminal O3, which is connected to the counting circuit 140 to output a control signal to the counting circuit 140, and which may be plural.

Taking the example where the plurality of oscillators 120 includes two oscillators (i.e., a first oscillator and a second oscillator), the combinational logic circuit 1103 may be constructed in accordance with the following logic functions: when inputting by countingWhen the count data (i.e., the value corresponding to the output signal of the multi-bit counter 1102) input at the terminal is a first preset value (e.g., 0), the output second trigger signal is at an inactive level (e.g., low level), and when the count data input at the terminal is not the first preset value (e.g., 0) (i.e., is a value other than the first preset value), the output second trigger signal is at an active level (e.g., high level); when the input count data is within a predetermined range (e.g., 28-31) or a second predetermined value (e.g., 2)ⁿN is a positive integer greater than 1), the output control signal is at an active level (e.g., high level), and conversely, when the input count data is not within a predetermined range (e.g., 28-31) or is not at a second predetermined value (e.g., 2)ⁿWhich may be the same as or different from the first preset value), the output control signal is at an inactive level (e.g., low level); when the input count data does not reach the upper limit of the count of the multi-bit counter 1102 (i.e., 2)ⁿ+1), the output first reset signal is kept at a low level, and jumps to a high level when the count data input through the count input terminal reaches the upper limit of the count of the multi-bit counter 1102.

The plurality of oscillators 120 may be respectively interfaced with corresponding ones of the second input terminals I2, and may preferably include two oscillators (e.g., a first oscillator and a second oscillator). Furthermore, each oscillator 120 may be composed of a voltage-controlled delay unit and a nand gate, as shown in fig. 6, or a voltage-controlled inverse delay unit and an and gate, wherein the voltage-controlled delay unit and the voltage-controlled inverse delay unit may be fabricated by using related devices in the prior art, for example, the voltage-controlled inverse delay unit may be composed of a current-controlled inverter using 4 transistors. The operating principle of each oscillator 120 is as follows: when the received trigger signal is at an active level (e.g., a high level), the oscillator 120 outputs an oscillation signal that is an oscillation pulse, and an oscillation period thereof may be controlled by the received reference voltage signal; when the trigger signal is at an inactive level (e.g., a low level), the oscillator 120 outputs an oscillation signal that is a steady-level signal, e.g., a high-level signal or a low-level signal. It should be noted that the trigger signal herein may refer to the first trigger signal or the second trigger signal.

The phase detector 130 may be connected to the logic control circuit 110 (specifically, the first output O1 of the combinational logic circuit therein) and the plurality of oscillators 120, and may be configured to compare phase relationships (e.g., phase coincidence, phase lead or phase lag, etc.) between the plurality of oscillation signals generated by the plurality of oscillators 120 under the control of the logic control circuit 110. Specifically, for the case where the plurality of oscillators 120 includes two oscillators, i.e., a first oscillator and a second oscillator, when the first reset signal received from the logic control circuit 110 is at an inactive level, the phase detector 130 may compare whether the phases of the oscillation signals generated by the first oscillator and the second oscillator are identical or the lead/lag relationship of the phases of the oscillation signals generated by the second oscillator is changed, and if the phases of the two oscillation signals are identical or the lead/lag relationship is changed, a difference between start times of the two oscillation signals, i.e., a difference between times at which the two oscillators start oscillating, may be determined. For the case that the plurality of oscillators 120 includes more oscillators (e.g., m oscillators, m is a positive integer greater than 2), the phase detector 130 may sequentially compare whether the phases of each two of m oscillation signals generated by the m oscillators received successively are consistent or the lead/lag relationship of the phases of the two oscillation signals is changed, so as to determine the difference between the start times of the m oscillation signals. For example, the phase detector 130 may compare whether the phases of the two oscillation signals generated by the first oscillator and the second oscillator are consistent or whether the lead/lag relationship of the phases of the two oscillation signals is changed to determine the difference between the start times of the two oscillation signals; then, whether the phases of the two oscillation signals generated by the second oscillator and the third oscillator are consistent or whether the lead/lag relationship of the phases of the two oscillation signals is changed can be compared to determine the difference between the starting times of the two oscillation signals, and so on until the difference between the starting times of the two oscillation signals generated by the m-1 th oscillator and the m-th oscillator is determined. In addition, when the first reset signal received from the logic control circuit 110 is at an active level, the electrical signal output by the phase detector 130 is at an inactive level; when the first reset signal is at an inactive level, it is at an active level.

The counting circuit 140 may include a plurality of counters 1401 and shift registers 1402. Each counter 1401 may be a multi-bit counter, and may be connected to a corresponding oscillator 120. The plurality of counters 1401 may be configured to count the plurality of oscillation signals generated by the plurality of oscillators 120 and to be reset according to a second reset signal received from the logic control circuit 110. Specifically, each time a valid edge (i.e., a rising edge or a falling edge) of the corresponding oscillation signal is received, the counter 1401 may count in a preset counting manner (e.g., an increasing or decreasing manner) in a current counting state (e.g., an initial counting state), e.g., increase the initial counting by 1, and transmit counting data corresponding to its current counting state (i.e., counting data corresponding to a previous trigger event, e.g., an initial counting) to the shift register 1402. If a second reset signal (i.e., a signal for resetting the counter 1401, which is included in the control signal) is received from the logic control circuit 110 in the process of counting and is at an inactive level, the counter 1401 continues counting and transmits corresponding count data to the shift register, and if the second reset signal is at an active level, the counter 1401 resets to be restored to its initial count state and restarts counting. It should be noted that the trigger event may refer to an event that the oscillator 120 generates an oscillation signal during the process of the trigger signal jumping from the active level to the inactive level.

The shift register 1402 may be configured to receive count data transmitted from the plurality of counters 1401 and a shift clock signal and a shift control signal transmitted from the logic control circuit 110, and output a time stamp containing the count data according to the received shift clock signal and shift control signal. Wherein the second reset signal, the shift clock signal, and the shift control signal are all included in the control signal, and may be generated by the logic control circuit 110 according to the reference clock signal. Also, whether the second reset signal is an active level may be determined according to whether count data about the reference clock signal (specifically, count data input to the combinational logic circuit 1103) recorded by the logic control circuit 110 is a second preset value. For example, when the count data is not the second predetermined value, the second reset signal is active; when the counting data is a second preset value, the second reset signal is at an invalid level. When the first trigger signal or the second trigger signal generated by the logic control circuit 110 is at an active level (i.e., when the count data recorded by the logic control circuit 110 about the reference clock signal is a value other than the first preset value), the logic control circuit 110 may use the reference clock signal as the shift clock signal, that is, the shift clock signal is the same as the reference clock signal. The shift control signal is at an active level when count data on the reference clock signal (i.e., count data input to the combinational logic circuit) recorded by the logic control circuit 110 is within a preset range, and at an inactive level when the count data is not within the preset range.

The working principle of the shift register 1402 is as follows: when the shift clock signal received from the logic control circuit 110 is at an inactive level, the shift register 1402 maintains the current data state and outputs a time stamp as a stable level signal; when the shift clock signal is at an active level and the shift control signal is also at an active level, the shift register 1402 shifts the received count data of each counter 1401 to one end at an active edge of the shift clock signal, and outputs the count data shifted out of the shift register 1402 and a preset start flag bit (i.e., a bit for marking the start of effective output of a time stamp) as a time stamp to the outside; when the shift clock signal is at an active level and the shift control signal is at an inactive level, the shift register 1402 may store the received count data and preset start flag bits and check flag bits (i.e., bits for checking the validity of the time stamp). The time stamp output from the shift register 1402 may generally include count data of each counter 1401, and may also include a start flag bit and/or a check flag bit.

The coarse time may be obtained from the start flag in the timestamp output by the shift register 1402 in combination with the obtained global clock count, the fine time may be obtained from the difference between the start times of the multiple oscillation signals determined by the phase detector 130 and the respective count data in the timestamp output by the shift register 1402, and the complete time measured by the timing channel 100 may be obtained from the combination of the coarse time and the fine time. As to how to determine the complete time of the time signal to be measured from the coarse time and the fine time, reference may be made to methods in the prior art, which are not described in detail here.

In another embodiment of the present invention, as shown in fig. 7, each timing channel may further include an oscillation transmission circuit 135, which may be connected with the plurality of oscillators 120, the phase detector 130, and the counting circuit 140. The oscillation transmission circuit 135 may be formed of an and gate as shown in fig. 8. In addition, oscillation transmission circuit 135 may be configured to generate multiple count signals corresponding to the multiple oscillation signals, respectively, from the received multiple oscillation signals and the electric signals generated by phase detector 130, and send the generated multiple count signals to a plurality of counters 1401 in counting circuit 140. Moreover, when the electric signal generated by the phase detector 130 is at an effective level, the multiple counting signals generated by the oscillation transmission circuit 135 are all stable level signals, and at this time, the plurality of counters 1401 stop counting; when the electric signal is at an inactive level, the plurality of counters 1401 count the plurality of count signals respectively, and the plurality of count signals generated by the oscillation transmission circuit 135 respectively match the plurality of oscillation signals. The oscillation transmission circuit 135 may function as a switch, so that the counting operation of the plurality of counters 1401 can be effectively controlled.

The operation principle of a timing channel and the output time stamp are described below by way of specific examples.

Taking the example that the plurality of oscillators includes a first oscillator and a second oscillator and the plurality of counters includes a first counter and a second counter, and the rising edge of the reference clock signal is an active edge with a period of 10ns, the timing diagram of the timing channel is shown in fig. 9. When the timing channel is in an initial state, the time signal to be measured is at a low level, and the first trigger signal, the second trigger signal and the two-path oscillation are carried outThe signals are all low levels, the first reset signal and the second reset signal are both high levels, the electric signal generated by the phase discriminator is high levels, the first counting data of the first counter and the second counting data of the second counter are both 0, the shifting clock signal is kept at low levels, the shifting control signal is high levels, and the output timestamp is low levels. When the time signal to be measured is at an active level (i.e., low level), the edge with the time information is a falling edge, the falling edge of the time signal to be measured makes the first trigger signal at an active level (i.e., high level) and maintains a predetermined width, such as 330ns, and the first oscillator is controlled by the first reference voltage signal for a first oscillation period (T;)_s) Oscillation is started until the first trigger signal changes to a low level (this process is referred to as a "trigger event"), and then the oscillation transmission circuit generates a corresponding count signal according to the first oscillation signal output by the first oscillator, and the first counter counts the count signal, and the first count data changes accordingly. When the reference clock signal is at a rising edge after a falling edge of the time signal to be measured, the second trigger signal is at an active level (i.e., a high level) and maintains a preset width consistent with the first count signal, and the second oscillator is controlled by the second reference voltage signal for a second oscillation period (T)_f) Starting oscillation until the second trigger signal changes to low level, wherein the second oscillation period may be slightly less than the first oscillation period, and the difference (T) between the start times of the two oscillation signals generated by the two oscillators_diff＝T_s-T_f) The oscillation transmission circuit generates a corresponding counting signal according to the oscillation signal output by the second oscillator, the second counter counts the counting signal, and the second counting data is changed accordingly. When the phase discriminator detects that the phases of the two oscillation signals are consistent or the lead/lag relationship is changed, the electric signal is at an effective level (namely, a low level), the oscillation transmission circuit generates a stable level signal, the corresponding first counter and the second counter do not count any more, and the current first counting data and the second counting data are kept. When the second trigger signal is at effective level, the shift clock signal is in effective stateThe signal changes along with the reference clock signal, the shift control signal is invalid level in the first 280ns of the period when the second trigger signal is valid level, at this time, the shift register outputs the time stamp of the last falling edge of the time signal to be measured to the outside, the shift control signal is valid level in the period of 280ns to 320ns of the period when the second trigger signal is valid level, at this time, the shift register saves the time of the falling edge of the time signal to be measured, the preset starting mark bit and the checking mark bit as the time stamp, and the time stamp is output to the outside when the time signal to be measured is valid level next time. After the shift control signal is no longer at the active level, if the last 10ns during the period when the second trigger signal is at the active level, the first reset signal and the second reset signal are at the active level, the first count data and the second count data are both reset to 0, and the electrical signal is reset to the high level, the timing channel is reset to the initial state and waits for the next falling edge of the time signal to be measured.

The timestamp output by the timing channel may be in the format of "2 bits start flag bit +8 bits second count data +4 bits check indication bit +8 bits first count data", where the start flag bit is "11" and the check flag bit is "1111". That is, when it is detected that a certain timing channel continuously outputs a high level for 2 clock cycles from a low level state, it is decided to start outputting a time stamp, and level states from the 3 rd clock cycle to the 10 th clock cycle are read out as second count data C₂Then, the level from the 11 th clock cycle to the 14 th clock cycle is checked, if it is high, the time stamp is verified to be valid, and the level state from the 15 th clock cycle to the 22 th clock cycle is read out as the first count data C₁. Therefore, in fig. 9, the first count data C₁To "00011110" (i.e., 30), second count data C₂Is "00011101" (i.e., 29).

The first count data and the second count data in the time stamp can be used to calculate the fine time of the falling edge of the time signal to be measured: t is_fine＝T_diff*C₂+T_s*(C₁-C₂) For example, according toThe time stamp in fig. 9 can calculate a fine time: t is_fine0.02 × 29+2 × 30-29 × 2.580 ns. In addition, the start marker bit indicates the global time count C corresponding to the first bit period₀Can be used to calculate the coarse time of the time signal to be measured: t is_coarse＝C₀*T_ref(T_refThe period of the reference clock signal). The measurement result of the complete time of the time signal to be measured is: t ═ T_coarse-T_fine. Therefore, based on the global time count and the timestamp of each timing channel, the time of the time signal to be measured corresponding to each timing channel relative to the reference clock signal can be obtained, and the time difference of the time signal to be measured of any two timing channels can be obtained.

In another embodiment of the present invention, as shown in fig. 10, the multichannel time-to-digital converter 1000 may further include a global counter 200, which may be configured to receive the reference clock signal and generate a corresponding global clock count, and may include a clock input for receiving the reference clock signal and a count output for outputting the global clock count, and the clock input thereof is connected in parallel with the third input of each timing channel 100.

In the embodiment, one global counter is set for all timing channels, instead of one global counter for each timing channel, so that the occupied chip area can be reduced, and the cost can also be reduced.

In another embodiment of the present invention, as shown in fig. 11, the multichannel time-to-digital converter 1000 may further include a voltage generation circuit 300, which may be configured to receive a reference clock signal and generate a reference voltage to control a difference between start times of multiple oscillation signals generated by the plurality of oscillators 120 in each timing channel 100, and may include a clock input terminal for receiving the reference clock signal and a voltage output terminal for outputting the reference voltage to each timing channel 100. The voltage output may include a plurality of interfaces that may be respectively connected to a plurality of interfaces in the second input of each timing channel 100 to provide a reference voltage to the plurality of oscillators 120. Additionally, the clock input of the voltage generation circuit 300 may be connected in parallel with the third input of each timing channel 100.

The voltage generation circuit 300 may be formed of a Delay Locked Loop (DLL) or a Phase Locked Loop (PLL), or an analog voltage division circuit may also be employed.

In another embodiment of the present invention, as shown in fig. 12, the multichannel time-to-digital converter 1000 may further include the global counter 200 in fig. 10 and the voltage generating circuit 300 in fig. 11.

As can be seen from the above description, the present invention designs each timing channel in the multi-channel time-to-digital converter to only include three input terminals and a time stamp output terminal and all timing channels are used for receiving the second input terminal of the reference voltage signal in parallel, which can reduce the chip area occupied by the multi-channel time-to-digital converter, thereby realizing the purpose of integrating with the pixel array in the same chip and reducing the system complexity. In addition, each timing channel measures the time of one time signal to be measured relative to a reference clock signal, rather than measuring the time difference between two time signals to be measured, which can achieve high-precision time measurement with a large dynamic range, and can also obtain the relative time relationship of a plurality of timing channels. In addition, the logic control circuit in each timing channel can be completely composed of logic gate circuits, so that the circuit structure can be simplified, the chip area occupied by a single timing channel can be reduced, and the integration in the pixel array of the photoelectric detector can be further realized. In addition, each timing channel can save the counting data when the current trigger event is ended by using the shift register and simultaneously output the counting data of the last trigger event in the form of a time stamp, so that the timing channel only needs one port to output the thin time, and the global time counting is marked by using the time stamp start marking bit, so that the coarse time information transmission can be realized, and the time measurement precision is improved. Therefore, utilize the utility model discloses not only can guarantee time measuring information integrality, can reduce multichannel time digital converter's wiring complexity moreover based on this and on the unchangeable basis of timing channel measuring frequency.

The present invention also provides a photo detection device, as shown in fig. 13, the photo detection device may include the multi-channel time-to-digital converter 1000 and the pixel array 2000 described in the above embodiments, and the multi-channel time-to-digital converter 1000 may be disposed inside or outside the pixel array 2000, for example, on the outer side thereof, and the two may be integrated on the same chip. The pixel array 2000 may include one or more pixels. The description of the pixel array can refer to the prior art and is not repeated herein.

By using the photoelectric detection device, the effective photosensitive area can be increased, and the system sensitivity can be improved.

The devices, modules, units, etc. set forth in the above embodiments may be embodied as chips and/or entities (e.g., discrete components) or as products having certain functions. For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functions of the units can be integrated in one or more chips in implementing the present invention.

Although the present invention provides components as described in the above embodiments or figures, more or fewer components may be included in the device based on conventional or non-inventive efforts. The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments.

The above-described embodiments are described in order to enable those of ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to these embodiments may be made, and the generic principles described herein may be applied to other embodiments without the use of the inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications within the scope of the present invention according to the disclosure of the present invention.

Claims

1. A multi-channel time-to-digital converter, wherein the multi-channel time-to-digital converter comprises a plurality of timing channels, and wherein each of the timing channels comprises: the time measurement device comprises a first input end used for receiving a time signal to be measured, a second input end used for receiving a reference voltage signal, a third input end used for receiving a reference clock signal and a time stamp output end used for outputting a time stamp obtained by measuring the time signal to be measured according to the reference voltage signal and the reference clock signal, wherein the second input ends of a plurality of timing channels are connected in parallel.

2. The multi-channel time-to-digital converter of claim 1, wherein each of the timing channels comprises:

a logic control circuit, provided with the first input terminal and the third input terminal, for generating a response signal corresponding to the received time signal to be measured according to the received reference clock signal;

3. The multi-channel time-to-digital converter of claim 2, wherein the logic control circuit comprises a latch, a multi-bit counter, and a combinational logic circuit connected to each other.

4. The multi-channel time-to-digital converter of claim 3, wherein the first reset terminal of the latch is connected to the first output terminal of the combinational logic circuit, one of its non-inverting and inverting output terminals is connected to the second reset terminal of the multi-bit counter, and the other of the non-inverting and inverting output terminals is connected to a first oscillator of the plurality of oscillators to provide a first trigger signal to the first oscillator.

5. The multi-channel time-to-digital converter of claim 4, wherein the combinational logic circuit comprises:

6. The multi-channel time-to-digital converter of claim 2, wherein the counting circuit comprises:

7. The multi-channel time-to-digital converter of claim 2, wherein the time stamp further comprises preset start indicator bits and/or check indicator bits.

8. The multi-channel time-to-digital converter of claim 2, wherein each of the timing channels further comprises an oscillation transmission circuit for generating a corresponding plurality of count signals from a plurality of the oscillation signals received from the plurality of oscillators and an electrical signal received from the phase detector, and sending the generated plurality of count signals to the count circuit.

9. The multi-channel time-to-digital converter of claim 2, further comprising:

10. A photo detection device comprising a pixel array and a multi-channel time-to-digital converter as claimed in any of claims 1 to 9, and arranged either internally or externally of the pixel array.