CN209804266U

CN209804266U - Low-load 64GB capacity novel server memory bank

Info

Publication number: CN209804266U
Application number: CN201920005983.6U
Authority: CN
Inventors: 沈泽斌
Original assignee: Hitech Semiconductor Wuxi Co Ltd
Current assignee: Hitech Semiconductor Wuxi Co Ltd
Priority date: 2019-01-02
Filing date: 2019-01-02
Publication date: 2019-12-17
Anticipated expiration: 2029-01-02

Abstract

The utility model discloses a novel server memory strip of 64GB capacity of low load aims at providing an increase load capacity, and the consumption is few, makes the more stable memory strip of server, and its technical scheme main points are including the electronic circuit board, be equipped with memory chip module, read-write error correction module and mode register module and golden finger through the circuit connection on the electronic circuit board, read-write error correction module and mode register module that part among the golden finger corresponds typical connection. The product adopts a novel architecture form, and the architecture form has a new breakthrough. The original common processor can support 3 memory channels, each memory channel can support at most 3 RDIMMs, and after the LRDIMM memory adopting the new architecture is adopted, the same system can support 9 DIMMs per channel, and the memory capacity is improved to three times.

Description

Low-load 64GB capacity novel server memory bank

Technical Field

The utility model belongs to the semiconductor chip field especially relates to a novel server memory bank of 64GB capacity of low load.

Background

With the continuous development of various internet technologies, the amount of cloud storage data is continuously increased, the requirements on the accuracy and capacity of memory processing data on high-end servers and some graphic processing stations are continuously increased, and the development of low-load server memories becomes a major topic of manufacturers of large semiconductor memories.

At present, a Chinese patent with publication number CN104168324 discloses a secure cloud storage layer, which relates to the field of network storage security and comprises a storage device, a bottom disk storage array and a back plate facilitating data communication, wherein an FPGA is adopted to form isolation logic to divide the storage device into an internal network unit and an external network unit, the external network unit comprises a gigabit network interface used for connecting an external network and an external network main control chip, the isolation unit comprises isolation logic realized by the FPGA, the isolation logic is in interactive communication with the external network main control chip, the internal network unit comprises an internal network main control chip, and the internal network main control chip is in interactive communication with the isolation logic; the internal and external network main control chips synchronize data through a high-speed data synchronization channel of the backboard, and the disk storage array is connected to the backboard for storing final data.

The high-speed computing capability, long-time reliable operation, strong external data throughput capability and high index requirement of energy conservation of the server are met, the existing server memory architecture mode is broken through, a new architecture, low load, high capacity and low error rate are urgently needed to be developed, and the high-speed computing capability, the long-time reliable operation, the strong external data throughput capability and the high index requirement of energy conservation of the server become necessary trends of future development of various manufacturers. In consideration of market prospect, the novel server with low load and large capacity has great development space worldwide, and new products are continuously developed and improved to meet market demands. The company is also beginning to develop new low-Load, high-capacity Load Reduced DIMMs to meet customer demand and to broaden the market.

The novel low-Load high-capacity LRDIMM is an abbreviation of Load-Reduced DIMM, and the aim of reducing the Load and the power consumption of a server memory bus is fulfilled by using a new technology and a lower working voltage, and the server memory bus can reach a higher working frequency and greatly improve the memory support capacity.

With the continuous increase of the requirements of data storage capacity and storage speed, the traditional server load capacity reaches the limit. Especially, the memory capacity of the server cannot be greatly improved due to load limitation, and the power consumption of the traditional server memory is huge because the traditional server memory needs to be continuously self-refreshed due to the working principle of the traditional server memory, and meanwhile, more powerful heat treatment equipment is needed for heat dissipation of all devices of the server, otherwise, the server is unstable.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a 64GB capacity novel server memory strip of low load. The method has the advantages of increasing load capacity, reducing power consumption and stabilizing the server.

The purpose of the utility model can be realized through the following technical scheme:

The utility model provides a novel server memory strip of 64GB capacity of low load, includes the electronic circuit board, be equipped with memory chip module, read-write error correction module and mode register module and golden finger through the circuit connection on the electronic circuit board, part in the golden finger corresponds typical read-write error correction module and the mode register module of connecting.

Preferably, the number of the read-write error correction modules is two, and the two read-write error correction modules are respectively arranged on the front side and the back side of the electronic circuit board.

Preferably, the mode register module is arranged on the front surface of the electronic circuit board.

Preferably, the distribution of each memory chip module on the electronic circuit board adopts a staggered arrangement mode.

The utility model has the advantages that:

Compared with a normal Unbuffered DIMM, the Registered DIMM used by the server improves the memory support capacity by buffering signals on a memory strip and redriving memory granules, and the LRDIMM memory reduces the load of a memory bus by changing a Register chip on the current RDIMM memory into an IMB memory isolation buffer chip and correspondingly further improves the memory support capacity. Compared with the common RDIMM, the power consumption of the memory of the 2Rank LRDIMM is only 50% of that of the memory, and the power consumption of the memory of the 4Rank LRDIMM can be as low as 75% of that of the memory of the 4Rank LRDIMM.

The product adopts a novel architecture form, and the architecture form has a new breakthrough. The original common processor can support 3 memory channels, each memory channel can support at most 3 RDIMMs, and after the LRDIMM memory adopting the new architecture is adopted, the same system can support 9 DIMMs per channel, and the memory capacity is improved to three times.

Drawings

FIG. 1 is a schematic diagram of a front structure of a memory bank;

Fig. 2 is a schematic diagram of a memory bank backside structure.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

Example 1: a low-load 64GB capacity new server memory bank is shown in figure 1,

Fig. 2 shows that the electronic device comprises an electronic circuit board 1, wherein the electronic circuit board 1 is provided with a memory chip module 2, a read-write error correction module 3, a mode register module 4 and a golden finger 5 through circuit connection, and a part of the golden finger 5 corresponds to the typically connected read-write error correction module 3 and the mode register module 4.

Preferably, two read-write error correction modules 3 are arranged and respectively arranged on the front side and the back side of the electronic circuit board 1.

Preferably, the mode register module 4 is disposed on the front surface of the electronic circuit board 1.

Preferably, the distribution of the memory chip modules 2 on the electronic circuit board 1 adopts a staggered arrangement mode.

As shown in fig. 1, the memory chip modules 2 are distributed in a staggered arrangement manner, so that for a 64GB memory with a relatively large capacity, a circuit board per unit area can accommodate more memory particles, and it is possible to realize a large capacity of 64 GB.

The DDR4 DRAM dynamic random access memory particle based on the 2Z nanometer manufacturing technology has the single particle capacity reaching 16Gb, the working voltage stabilizing at 1.20V, and is one of the leading DRAM particles.

Compared with the parity check technology which can only check errors, the server memory adopts a mode register control chip and an ECC error check and correction technology. The method adds an error correction function, so that data can be corrected by itself under the condition of read-write errors, and the normal operation of the server is ensured.

In addition, compared with a common memory 8 physical Rank, the newly developed server memory adopts 2-4 physical ranks, so that the working controllability of the server memory is stronger, and the server memory can communicate with external equipment more quickly.

It should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Finally, it should be noted that: the above embodiments are only used for illustrating but not limiting the technical solutions of the present invention, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made thereto without departing from the spirit and scope of the invention, and the appended claims are intended to cover such modifications and equivalents as fall within the spirit and scope of the invention.

Claims

1. a novel 64GB capacity server memory bank of low load, its characterized in that: the electronic circuit board comprises an electronic circuit board (1), wherein a storage chip module (2), a read-write error correction module (3), a mode register module (4) and a golden finger (5) are arranged on the electronic circuit board (1) in a circuit connection mode, and part of the golden finger (5) corresponds to the typically connected read-write error correction module (3) and the mode register module (4).

2. a low-load 64GB capacity novel server memory bank according to claim 1, wherein: the two read-write error correction modules (3) are respectively arranged on the front side and the back side of the electronic circuit board (1).

3. A low-load 64GB capacity novel server memory bank according to claim 2, wherein: the mode register module (4) is arranged on the front surface of the electronic circuit board (1).

4. A low-load 64GB capacity novel server memory bank according to claim 3, wherein: the distribution of each memory chip module (2) on the electronic circuit board (1) adopts a staggered arrangement mode.