WO2024001962A1 - Memory, chip stack structure, chip package structure, and electronic device - Google Patents

Abstract

The present application relates to the technical field of memories, and provides a memory, a chip stack structure, a chip package structure, and an electronic device, capable of providing storage spaces of different bandwidths on a same memory, and meeting the bandwidth, power consumption and capacity requirements. The memory comprises a first storage region and a second storage region; the first storage region and the second storage region each comprise multiple banks, each bank comprises one or more arrays, and each array has the same number of input and output ports; the number of arrays of banks located in the first storage region is different from the number of arrays of banks located in the second storage region, for example, the number of arrays of banks in the first storage region is greater than the number of arrays of banks in the second storage region, and the number of banks in the first storage region is less than the number of banks in the second storage region. In this way, the first storage region can have a greater bandwidth; excessive power consumption can be avoided; and the capacity of the second storage region is larger, and therefore, the memory can simultaneously meet the bandwidth, power consumption and capacity requirements.

Description

Memory, chip stack structure, chip packaging structure and electronic equipment

This application requires the priority of the Chinese patent application submitted to the State Intellectual Property Office on June 29, 2022, with the application number 202210753276.1 and the application name "Memory, chip stack structure, chip packaging structure and electronic equipment", and all its contents have been approved This reference is incorporated into this application.

Technical field

The present application relates to the field of memory technology, and in particular to a memory, a chip stack structure, a chip packaging structure and electronic equipment.

Background technique

Electronic devices such as mobile phones and tablets have three requirements for main memory: large capacity, low power consumption and high bandwidth. However, existing solutions can often only meet the needs of one of them and cannot achieve all three at the same time. Both. Solutions to increase storage density and capacity often lead to a reduction in read and write bandwidth and an increase in power consumption; designs that increase bandwidth are often not conducive to an increase in storage capacity and a reduction in power consumption.

By stacking multiple memory chips and connecting data signals, control signals and address signals through "interconnect terminals" and "internet networks", multiple separate, low-capacity chips can be implemented into a high-capacity single chip. Stacking multiple identical memory chips in a single package to achieve higher storage density packaging can increase storage capacity, but this can only solve the problem of insufficient storage capacity and cannot increase the bandwidth of the memory chip.

Or you can divide the memory chip into finer granularities to get more data transmission channels to increase bandwidth. However, this method cannot solve the problem of insufficient capacity and will also increase power consumption.

Contents of the invention

Embodiments of the present application provide a memory, a chip stack structure, a chip packaging structure and an electronic device to improve the problem that existing main memories cannot meet the requirements for bandwidth, capacity and power consumption.

In a first aspect, a memory is provided, including: a first storage area and a second storage area, the first storage area and the second storage area including a plurality of storage banks, each storage bank including one or more arrays, each The arrays have the same number of input and output ports; wherein the number of arrays of the bank located in the first storage area is different from the number of arrays of the bank located in the second storage area, so that the banks of the first storage area and the banks of the second storage area have different The number of input and output ports and the amount of data that can be read and written in unit time are different, so the bandwidth of the first storage area is different from the bandwidth of the second storage area. The first storage area and the second storage area can be suitable for different bandwidth requirements. Application scenarios. Most of the traditional solutions for increasing bandwidth are to increase the overall bandwidth of the memory, which will lead to an increase in the overall power consumption of the memory. The memory provided by the embodiments of the present application has different bandwidth sizes between the first storage area and the second storage area, which can meet the requirements. Different bandwidth requirements, while only increasing the bandwidth of a part of the storage area, can avoid the increase in overall power consumption of the memory due to the increase in bandwidth; when expanding the memory capacity, the memory capacity can also be expanded according to the bandwidth requirements or capacity requirements, for example, if the memory If you need to meet the requirements of smaller bandwidth and larger storage capacity, you can increase the area of the storage area with smaller bandwidth in the first storage area and the second storage area. This can also prevent the memory from expanding the memory capacity due to the larger overall bandwidth. This results in an increase in the overall power consumption of the memory.

In a possible implementation, the number of arrays of banks located in the first storage area is greater than the number of arrays of banks in the second storage area, and each array has the same number of input and output ports. The first storage area The number of arrays of the bank in the second storage area is greater than the number of arrays in the bank in the second storage area. Compared with the bank in the second storage area, the bank in the first storage area has more input and output ports and can be read and written per unit time. There is more data, so the bandwidth of the first storage area is greater than the bandwidth of the second storage area. The first storage area can be suitable for large-bandwidth storage requirements, and the second storage area can be suitable for low-bandwidth storage requirements.

In a possible implementation, the number of arrays of banks located in the first storage area is 2 ⁿ times the number of arrays of banks located in the second storage area, and n is a positive integer, such as the number of arrays of banks in the first storage area. It is twice the number of bank arrays in the second storage area, so that the bandwidth of the first storage area can also be twice the bandwidth of the second storage area.

In a possible implementation, the number of banks in the first storage area is smaller than the number of banks in the second storage area, and the capacity of any two banks is the same, so that the storage capacity of the first storage area is smaller than the storage capacity of the second storage area. Capacity, due to the increase in bandwidth, will lead to an increase in power consumption. The bandwidth of the first storage area in the memory provided by the embodiment of the present application is greater than the second storage area, and the number of banks in the first storage area is less than the number of banks in the second storage area. , that is, the capacity of the first storage area is smaller than the capacity of the second storage area, which can avoid excessive power consumption. Compared with the first storage area and the second storage area, that is, the overall bandwidth of the memory, the embodiment of the present application Provides memory with lower power consumption.

In a possible implementation, the memory includes a first data bus and a second data bus; the first data bus is used to read and write data to the first storage area, and the second data bus is used to read and write data to the second storage area. , the first storage area and the second storage area can operate independently. When the first storage area is working, the second storage area does not need to work. When the second storage area is working, the first storage area does not need to work. This can reduce the memory cost. of power consumption.

In the second aspect, embodiments of the present application provide a chip stack structure. The chip stack structure includes a system and a chip SoC and one or more memories. The SoC and one or more memories are stacked in sequence; At least one memory provided for any implementation of the first aspect.

In a possible implementation, the stacking method includes one or more of the following methods: through silicon via TSV connection, chip on chip, chip on wafer, chip on wafer, wafer on wafer Yuan wafer on wafer.

In a third aspect, embodiments of the present application provide a chip packaging structure, including a packaging substrate and a chip stack structure provided in any implementation manner of the second aspect. The chip stack structure is disposed on the packaging substrate.

In the fourth aspect, embodiments of the present application provide a chip packaging structure, including a packaging substrate, a system-on-chip SoC, and a memory provided in any implementation manner of the first aspect; the packaging substrate includes a first plane, and the first plane includes The first area and the second area, the SoC is arranged in the first area, the memory is arranged in the second area, and the memory is electrically connected to the SoC through connecting lines.

In the fifth aspect, embodiments of the present application provide a chip packaging structure, including a packaging substrate, a system-level chip, and multiple memories; the packaging substrate includes a first plane, and the first plane includes a first region and a second region that do not want to intersect. , the SoC is disposed in the first area; a plurality of memory stacks are disposed in the second area to form a chip stack structure, at least one of the plurality of memories is a memory provided by any implementation method of the first aspect; the chip stack structure is connected to the chip stack structure through connecting lines. SoC electrical connections.

In a sixth aspect, embodiments of the present application provide an electronic device, including a printed circuit board and a chip packaging structure as provided in any one of the second to fifth aspects; the packaging substrate and the printed circuit board in the chip packaging structure Electrical connection.

Description of drawings

Figure 1 is a schematic diagram of data exchange between various sensors and processors;

Figure 2 is a schematic diagram of the pyramid structure of multi-level storage;

Figure 3 is a schematic diagram of a computer system provided by an embodiment of the present application;

Figure 4 is a schematic diagram of a storage unit provided by an embodiment of the present application;

Figure 5 is a schematic diagram of a memory provided by an embodiment of the present application;

Figure 6 is a schematic diagram of an array provided by an embodiment of the present application;

Figure 7 is a schematic structural diagram of a memory provided by an embodiment of the present application;

Figure 8 is a schematic diagram of main memory power consumption in mobile devices;

Figures 9 and 10 are schematic diagrams of the main parameters of the main memory of the mobile device;

Figure 11 is a schematic diagram of a memory package;

Figure 12 is a schematic diagram of a solution for improving main memory frequency;

Figure 13 is a schematic structural diagram of a memory provided by an embodiment of the present application;

Figure 14 is a schematic diagram of the storage library divided into multiple arrays;

Figure 15 is a schematic diagram of the distribution of the first storage area and the second storage area;

Figure 16 is a schematic diagram of a chip stack structure provided by an embodiment of the present application;

Figure 17 is a schematic diagram of a chip packaging structure provided by an embodiment of the present application;

Figure 18 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application;

Figure 19 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application;

Figure 20 is a schematic diagram of another chip stack structure provided by an embodiment of the present application;

Figure 21 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application;

Figure 22 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application;

Figure 23 is a schematic diagram of another chip packaging structure provided by an embodiment of the present application;

Figure 24 is a schematic layout diagram of an SoC and memory provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described The embodiments are only part of the embodiments of this application, rather than all the embodiments.

Hereinafter, the terms "first", "second", etc. are only used for convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined by "first," "second," etc. may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise stated, "plurality" means two or more. For example, multiple processing units refers to two or more processing units.

In addition, in the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to being defined relative to the schematically placed orientations of the components in the drawings. It should be understood that these directional terms may be Relative concepts, which are used for relative description and clarification, may change accordingly according to changes in the orientation of the components in the drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity, and the dimensional proportions between the various parts in the illustrations do not reflect actual dimensional proportions.

In the embodiments of this application, unless otherwise clearly stated and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection, They can also be connected indirectly through intermediaries. In addition, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediary.

In the embodiments of this application, the term "module" usually refers to a functional structure divided according to logic. The "module" can be implemented by pure hardware, or a combination of software and hardware. In the embodiment of this application, "and/or" describes the association of associated objects, indicating that there can be three relationships. For example, A and/or B can represent: A exists alone, B exists alone, and A and B exist simultaneously. situation.

In the embodiments of this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

In 1945, von Neumann proposed the concept of "stored program". Various computers based on this concept are collectively called von Neumann computers. The Von Neumann computer consists of five major components: input device, output device, memory, arithmetic unit and controller. The arithmetic unit is used to complete arithmetic operations and logical operations, and the intermediate results of the operations are temporarily stored in the arithmetic unit; the controller is used to control and direct the input, operation and processing of operation results of programs and data; the memory is used to store data and programs; input Devices are used to convert information forms that people are familiar with into information forms that computers can recognize. Common examples include keyboards, mice, microphones, scanners, etc.; output devices can convert computer calculation results into information forms that people are familiar with, such as monitors, Printers, speakers, etc. At this stage, the controller and arithmetic unit of the computer are combined into one, collectively called the central processing unit (CPU), while the input devices and output devices are referred to as I/O devices (input/output equipment).

With the development of computers, the speed of the CPU has become very high, and the access speed of the memory is difficult to match. This makes the running speed of the computer largely restricted by the memory, which is the so-called "memory wall problem". ”, which also makes the status of memory more prominent.

Memory is a memory component used to store programs and various data information. From different dimensions, memories in computer systems can be divided into different types.

For example, memory can be divided into read-only memory (read-only-memory) and random-access memory (random-access memory, RAM) according to different working principles. ROM works in a non-destructive reading mode. It can only read information but cannot write it. Once the information is written, it is fixed. Even if the power is cut off, the information will not be lost, so it is also called fixed memory. RAM is a readable/writable memory with fast reading and writing speeds. It is usually used as a temporary data storage medium for the operating system or other running programs. RAM can be written or read from any specified address at any time when working. The biggest difference between data and ROM is the volatility of data, that is, the stored data will be lost once the power is turned off. RAM is used in computers or digital systems to temporarily store programs, data and intermediate results. RAM can be divided into dynamic random access memory (dynamic random access memory, DRAM) and static random access memory (static random access memory, SRAM).

According to different uses, memory can be divided into main memory, auxiliary memory and cache. Figure 1 shows a schematic diagram of data exchange between main memory, auxiliary memory and cache and CPU.

Main memory, also known as main memory, is also called memory. Main memory can directly exchange data or information with the CPU. It is used to temporarily store the CPU's operation data, data exchanged with auxiliary storage, etc. Main memory is the bridge between the CPU and auxiliary memory. All computer programs run in the main memory. The performance of the main memory will affect the overall performance of the computer. While the computer is running, The operating system will transfer the data that needs to be processed from the main memory to the CPU for calculation, and the computer cannot operate normally without the main memory.

Auxiliary memory, also known as auxiliary memory, is also called external memory. It refers to memory other than computer memory and CPU cache. Compared with memory, the read and write speed is slower. This type of memory can still save data after a power outage. It is generally used Stores programs and data that are used less frequently. Auxiliary storage cannot directly exchange data with the CPU. Data needs to be exchanged with the CPU through main memory. Common auxiliary storage includes hard disks, floppy disks, optical disks, U disks, flash memory, etc.

Cache, or buffer memory (cache), is a technology used to solve the speed mismatch between the CPU and the main memory. The cache is a small-capacity memory between the CPU and the main memory and has a faster reading speed.

There are three main indicators of memory: speed, capacity and cost. Generally speaking, the higher the speed, the greater the cost; the higher the capacity, the slower the speed. For computer systems, multi-level storage systems are generally used. Memories with different storage capacities, reading and writing speeds, and costs are composed into multi-level memories according to a hierarchical structure. They are organically combined into a whole through management software and auxiliary hardware, so that The stored programs and data are distributed hierarchically in various memories.

Figure 2 shows the storage hierarchy pyramid structure of a computer system. From top to bottom, it is: register file (RF), cache (cache), main memory (main memory) and auxiliary storage (storage). Storage from top to bottom. The capacity is getting bigger, but the access speed is getting slower and slower.

The register file is an array of multiple registers in the processor. It usually consists of dozens of 32/64bits registers. It can be used to temporarily store instructions, data, addresses, etc. The registers are generally integrated in the CPU. For mobile For end devices, they are usually integrated on a system on chip (SoC). The register has a read and write speed close to that of the processor, but the cost is higher, so the capacity is generally smaller.

Cache, also known as cache memory, is a small-capacity but high-speed memory located between the CPU and the main memory. The capacity is usually in the order of MB. The cache generally does not use DRAM technology, but it is expensive to use. But faster SRAM technology. Since the speed of the CPU is much higher than that of the main memory, the CPU has to wait for a certain period of time to directly access data from the main memory. Therefore, a cache is set up to solve the problem of speed mismatch between the CPU and the main memory. The cache stores the data that the CPU has just used or A part of the data used in the cycle can be directly called from the cache when the CPU uses this part of the data again. This reduces the waiting time of the CPU and improves the efficiency of the system. The setting of the cache is an important factor in the high performance of all modern computer systems. one.

Main memory is mainly used to store programs and data that need to be run. There is a big gap between the speed of main memory and the speed of the CPU. In order to match the speed of the main memory and the CPU, a speed ratio of the main memory is inserted between the main memory and the CPU. Faster and smaller cache memory. Main memory generally uses DRAM technology. Its capacity restricts the number of programs that the device can run at the same time, which directly affects the performance of the device. It is an important storage device in computers. The storage capacity of main memory can reach the GB level. For mobile devices For end devices, the main memory usually does not belong to the same chip (die) as the SoC.

The last level of large-capacity auxiliary storage is used to store data, such as images, videos, etc. The read and write speed of this level of memory is slow, but the capacity can be very large. For example, the capacity can reach the GB or even TB level. When the device is running, the data stored in the memory is loaded into the main memory for processing.

The multi-level structure of the storage system is mainly reflected in the two storage levels of main memory-cache and main memory-auxiliary memory. The main memory-cache level is mainly used to solve the speed problem of the storage system. The speed of main memory does not match the speed of the CPU. Since the speed of main memory is lower and the speed of cache is higher than that of main memory, you only need to transfer the data to be used by the CPU into the cache, and the CPU can directly obtain the data from the cache, thereby increasing the access speed; main memory - The auxiliary storage level mainly solves the capacity problem of the storage system. The speed of auxiliary storage is lower than that of main memory, and it cannot directly exchange data with the CPU. However, its capacity is much larger than that of main memory. When the CPU needs data in auxiliary storage, it will After being loaded into the main memory, it is used by the CPU.

The main memory can exchange data with the CPU, cache and auxiliary memory, and is an important part of the storage system. Various parameters of the main memory: such as capacity, bandwidth, cost, etc., restrict the development of this computer system. The computer system referred to in the embodiments of this application can be a computer, and of course it can also refer to a mobile device, such as a mobile phone, a tablet, and other devices. Figure 3 shows a schematic architectural diagram of a computer system provided by an embodiment of the present application. As shown in Figure 3, the computer system 100 may at least include a processor 101, a memory controller 102 and a memory 103. Typically, the memory controller 102 may be integrated into the processor 101 and the memory 103 may be main memory. It should be noted that in the computer system provided by the embodiment of the present application, in addition to the devices shown in FIG. 3 , the computer system 100 may also include other devices such as communication interfaces and disks as auxiliary storage, which are not limited here.

The processor 101 is the computing core and control unit of the computer system 100. Processor 101 may include multiple cores 104 . An operating system and other software programs are installed in the processor 101, so that the processor 101 can access the memory 103, cache and disk. In the embodiment of the present application, the core 104 in the processor 101 may be a central processing unit (CPU), an artificial intelligence (artificial intelligence, AI) processor, a digital signal processor (digital signal processor), or a neural network processor. A network processor can also be other application specific integrated circuit (ASIC), etc. The memory controller 102 is a bus circuit controller that controls the memory 103 internally in the computer system 100 and is used to manage and plan data transmission from the memory 103 to the core 104. Through the memory controller 102, data can be exchanged between the memory 103 and the core 104. Memory controller 102 may be a separate chip and connected to core 104 via a system bus. The memory controller 102 may also be integrated into the processor 101 or built into the northbridge. The embodiments of the present application do not limit the specific location of the memory controller 102. In practical applications, the memory controller 102 can control necessary logic to write data to the memory 103 or read data from the memory 103 .

The memory 103 is the main memory of the computer system 100 and is usually used to store various running software in the operating system, input and output data, and information exchanged with external memory. Dynamic random access memory (DRAM) is usually used as the memory 103. The processor 101 can access the memory 103 at high speed through the memory controller 102, and perform read operations and write operations on any storage unit in the memory 103. In the embodiment of the present application, the memory 103 is a DRAM as an example for description. Unless otherwise specified, the main memory referred to in the embodiment of the present application is also called DRAM.

The smallest unit used to store data in DRAM is called a memory cell (MC). Usually, a memory cell can store 1 bit of data. The memory unit of DRAM is usually composed of a transistor and a capacitor. If it contains two transistors and two capacitors, it is called 2T2C; if it contains two transistors and one capacitor, it is called 2T1C; if it contains one transistor and one capacitor, it is called 2T1C. The capacitor is called 1T1C. The transistor can be a metal-oxide-semiconductor field effect transistor (MOSFET). The transistor is divided into two types: N (negative, negative) type transistor and P (positive, positive) type transistor. A transistor includes a source, a drain, and a gate. By controlling the level of the input transistor gate, the transistor can be turned on or off. When the transistor is turned on, the source and drain are turned on, generating a conduction current. Moreover, when the gate levels of the transistors are different, the magnitude of the conduction current generated between the source and the drain is also different; the transistor is When turned off, the source and drain will not conduct, and no current will flow. In the embodiment of the present application, the gate of the transistor is also called the control terminal, the source is called the first terminal, and the drain is called the second terminal; or, the gate is called the control terminal, and the drain is called the second terminal. It is called the first terminal and the source is called the second terminal.

Taking the structure of 1T1C as an example, Figure 4 shows a schematic structural diagram of a memory unit of DRAM, including a transistor T and a capacitor C. The first end of the transistor T is connected to the bit line (BL), and the second end of the transistor T is connected to the bit line (BL). Connected to the first end of the capacitor C, the control end of the transistor T is connected to the word line (WL), and the second end of the capacitor C is connected to the source line (SL), which can be connected to A specific voltage (such as ground). Capacitor C is used to store data. For example, when the voltage at the first terminal of capacitor C is high level and the voltage at the second terminal is low, it stores 1. When the voltage at the first terminal is low level and the voltage at the second terminal is high, it stores 1. Store 0; or, store 0 when the voltage at the first end of the capacitor C is high level and the voltage at the second end is low level, store 1 when the voltage at the first end is low level and the voltage at the second end is high.

The memory cells in the memory 103 are arranged and distributed into a matrix. This matrix is called a sub-array. Referring to Figure 5, the memory 103 may include a command decoder 110, a control logic circuit 120, and a sub-array 130. , input/output circuit 140, specific embodiments are not limited thereto and may include a smaller or larger number of constituent components. The command decoder 110 may receive a command CMD (command, CMD) from the memory controller 102 and may decode the received command CMD. For example, write commands (write, WR), read commands (read, RD), etc., the memory controller 102 can locate any storage unit in the bank through the corresponding row-column decoder, that is, locate any bit of data.

One or more subarrays form an array core tile, referred to as an array. As shown in Figure 6, an array can include multiple sub-arrays. In some implementations, storage units in the same array share row decoders, column decoders, and interfaces (such as input output (IO) ports). For example, the array shown in Figure 6 has 64 parallel IO port. The number of IO ports is related to the bandwidth of the entire memory, so manufacturers generally increase the number of IO ports in the array to the maximum extent within the allowable range of the process. It is understandable that different manufacturers may have different process levels, so different The number of IO ports in the arrays produced by the manufacturer may be different; but for the same manufacturer, the process level is stable, that is to say, the number of IO ports in the arrays produced is basically the same.

DRAM uses the amount of electricity stored in the capacitor to represent data 0 and 1. Due to leakage in capacitors, if there is insufficient charge in the capacitor, errors will occur in the stored data. Therefore, every once in a while, the memory controller 102 refreshes the data in the DRAM 103 to prevent the DRAM from losing data. Moreover, DRAM is volatile. When the computer system 100 is powered off, the information in the DRAM will no longer be saved.

Since DRAM and the processor are usually on different chips (die), the memory unit needs to be packaged and combined before it can be connected to the processor. The memory unit from the processor to the DRAM is divided into channels from large to small according to the hierarchy. ), storage column (rank), storage bank (bank), storage array (array), row or column (row/column).

As shown in Figure 7, a schematic diagram of a DRAM is shown. A channel is an independent accessible storage space, and the storage space may include one or a storage rank. Usually, a channel includes a certain capacity of storage space and a hardware circuit for accessing the storage space. The hardware circuit may include control logic, interfaces and other related circuits.

Channels can be composed of storage columns (ranks). The memory rank refers to the memory particles (chips) connected to the same chip select signal. The memory particles are also called chips; because these chips are connected to the same chip select signal, the memory controller 102 can Write operations are performed on chips in the same storage column, and chips in the same storage column also share the same control signal.

Each storage column may include one or more storage banks (banks). For example, a storage column may include 4 banks, or may also include 8 banks. A DRAM bank includes one or more storage arrays. Each storage array includes multiple memory cells (memory cells) distributed in rows and columns, or each storage array can also include multiple sub-arrays. (sub-array), the sub-array includes multiple storage cells distributed in rows and columns.

With the development of mobile SoCs such as mobile phones and tablets, they have three requirements for main memory: large capacity, low power consumption and high bandwidth. First of all, as the scale of mobile software becomes larger and larger and user data increases, mobile devices require larger-capacity main memory to save programs and data. As shown in Figure 8, the power consumption of main memory in mobile devices It accounts for a large proportion; in addition, mobile devices have high requirements for battery life, heat generation and other performance, so the main memory is required to have low read and write power consumption; finally, for scenarios such as video image processing and artificial intelligence (AI), the main The storage needs to provide high enough bandwidth to meet its huge computing power needs. Therefore, it is necessary to find a solution that can not only meet the mobile SoC's demand for large-capacity main memory, but also achieve lower read and write power consumption and provide sufficient bandwidth to support the computing power needs.

However, existing solutions often only meet the needs of one aspect and cannot achieve large capacity, low power consumption and high bandwidth at the same time. As shown in Figure 9, solutions to increase storage density and storage capacity often lead to reductions in read and write bandwidth and increases in power consumption; as shown in Figure 10, designs that increase bandwidth are often detrimental to increases in storage capacity and power consumption. Reducing, for example, increasing the bandwidth by increasing the read and write frequency will lead to an increase in power consumption.

Figure 11 shows a memory in which data signals, control signals and addresses are connected through interconnection terminals and interconnection networks by stacking multiple main memory chips (for example, memory 1 and memory 2) on a packaging substrate in one package. Signal, implements multiple separate, low-capacity main memory chips into a high-capacity single chip, and achieves higher storage density packaging by stacking multiple identical memory chips in a single package.

However, achieving higher storage density by stacking multiple identical main memory chips can only solve the problem of insufficient storage capacity and does not help improve transmission bandwidth. Considering stacking multiple main memory chips, the read and write lines of some main memory chips The length will increase, which will also lead to increased read and write power consumption.

The speed of reading data is one of the reasons that affects the computing power of the processor. The processor reads data from the main memory for processing, so it is particularly important to increase the transmission bandwidth of the main memory. Bandwidth refers to the amount of data that can be read or written per unit time. In order to improve the bandwidth of main memory, one possible implementation method is to increase the number of main memory channels or expand the data bit width of each channel. bandwidth.

However, expanding the overall main memory bandwidth can meet the large bandwidth requirements of scenarios such as video image processing and AI. However, 90% of mobile terminal scenarios have small bandwidth requirements. This solution wastes bandwidth; and increasing the entire main memory bandwidth will lead to higher power consumption. , due to the thermal design power (TDP) constraints of mobile applications, the running time under high bandwidth will be limited.

Another possible way is to adjust the read and write bandwidth of the main memory by adjusting the read and write frequency of the main memory. For example, see Figure 12, which provides a way to use a combination of software and hardware to solve the problem of bandwidth and function of the main memory. Consumption and other needs. In order to reduce power consumption and increase transmission bandwidth, the software adjusts the read and write frequency in real time according to the data flow. The storage controller includes a traffic statistics unit and a clock controller. At the software level, a frequency function is set in the storage control module. According to the statistics of the traffic statistics unit According to the traffic demand, the frequency function is used to determine the target frequency according to the traffic demand, and the frequency output by the clock controller is adjusted through the storage driver. in data flow When the memory requirement is small and the bandwidth requirement is low, the clock controller is controlled to output a low-frequency clock signal to reduce the read and write frequency of the main memory chip, reduce the read and write bandwidth, and also reduce power consumption; when the bandwidth requirement is high, , controlling the clock controller to output a high-frequency clock signal to increase the read and write frequency of the main memory chip and increase the read and write bandwidth. However, the high energy efficiency area of the main memory particles is located at high frequency. Running at low frequency will cause poor main memory energy efficiency and increase the access delay and power consumption of the SoC.

The application scenarios of mobile devices are complex, so there are three requirements for main memory: large capacity, high bandwidth, and low power consumption. However, existing main memory solutions can often only solve the needs of one of the above aspects and cannot take into account the above requirements at the same time. three aspects. Based on this, embodiments of the present application provide a memory to simultaneously meet the mobile device's requirements for main memory in terms of power consumption, bandwidth, and capacity.

Referring to Figure 13, an embodiment of the present application provides a memory, including: a first storage area and a second storage area; the first storage area and the second storage area can each be provided with one or more channels, so that the first storage area and the second storage area can each be provided with one or more channels. The first storage area and the second storage area can be accessed or read and write data independently. For example, channel 1 (abbreviated as ch1) and ch2 are set in the first storage area; ch3 to ch8 are set in the second storage area. Each channel includes one or more storage banks (banks). For example, for the first storage area, taking ch1 as an example, ch1 includes 4 banks such as b1, b2, b3, and b4. For the second storage area, , taking ch4 as an example, ch4 includes 4 banks such as b5, b6, b7, and b8. Each bank includes one or more arrays, where each array has the same number of input and output ports (IO). The number of arrays in the bank located in the first storage area is different from the number of arrays located in the second storage area. , in this way, the number of IO ports of the bank in the first storage area is different from the number of IO ports of the bank in the second storage area, that is to say, the bank in the first storage area and the bank in the second storage area can read and write in unit time. The amount of data is different, so the first storage area and the second storage area may have different read and write bandwidths. Due to the complex working scenarios of mobile devices, there are different bandwidth requirements. For example, when running high-computing power programs, the bandwidth requirements for the main memory are large; when running ordinary programs, the bandwidth requirements for the main memory are small. The embodiments of this application provide The memory can be adapted to usage scenarios with different bandwidth requirements. For example, the read and write bandwidth of the first storage area is greater than the read and write bandwidth of the second storage area. The first storage area can serve usage scenarios with large bandwidth requirements, such as neural networks, artificial intelligence, etc. Intelligence, graphics processing, etc.; the second storage area can serve usage scenarios with low bandwidth requirements, such as ordinary program running, etc. The first storage area and the second storage area can be accessed independently, which can meet the diverse demands for bandwidth under different operating states of the SoC.

For example, taking the memory 103 shown in FIG. 13 as an example, the first storage area includes 2 channels: ch1, ch2; the second storage area includes 6 channels: ch3, ch4, ch5, ch6, ch7, and ch8. Each channel includes multiple banks. For example, taking ch1 as an example, ch1 includes 4 banks such as b1, b2, b3, and b4. For the second storage area, taking ch4 as an example, ch4 includes b5, b6, b7, and b8. etc. 4 banks, and the number of arrays of the bank located in the first storage area is greater than the number of arrays of the bank located in the second storage area. For example, b1 of the first storage area includes 2 arrays, and b5 of the second storage area includes 1 array. In this way, the banks of the first storage area are divided into finer granularities, and more IO ports can be used. The number of IO ports of the bank in the storage area is greater than the number of IO ports of the bank in the second storage area. In unit time, the amount of data that the bank in the first storage area can read and write is greater than the amount of data that the bank in the second storage area can read and write. , the read and write bandwidth of the first storage area is greater than the read and write bandwidth of the second storage area.

Generally speaking, the number of IO ports per array is generally 2 ⁿ . For example, the most commonly used configuration is that each array has 64 IO ports. The number of arrays in each bank can be 1, 2, 4 or 8, etc. That is, the number of arrays in each bank can be ²⁰ , ²¹ , ²² , ²³ , etc. Based on this, In the embodiment of the present application, the number of bank arrays located in the first storage area is 2 ⁿ times the number of bank arrays located in the second storage area.

Taking the memory shown in Figure 13 as an example, each bank (taking b5 as an example) of the second storage area includes 1 array, and each array includes 64 IO ports. In this way, each bank of the second storage area has 64 IO ports. IO ports; the number of arrays in each bank (taking b1 as an example) in the first storage area is ²¹ times the number of arrays in the bank in the second storage area. Each array includes 64 IO ports, so that the number of arrays in the first storage area is Each bank has 128 IO ports, the number of which is ^2.1 times the number of IO ports of each bank in the first storage area. When the read and write frequencies are the same, the bandwidth of each channel in the first storage area is that of the second storage area. 2 ¹ times the bandwidth of each channel in the area.

The above example is not a limitation on each bank. The number of arrays in each bank can be determined according to actual needs and process level. For example, as shown in Figure 14, a, b, c, and d in Figure 14 show one bank respectively. Schematic diagram of the arrays divided into ²⁰ , ²¹ , ²² , and ²³ arrays respectively. Since the capacity of each bank is the same, the more arrays the bank includes, the smaller the capacity of each array, and the more IO ports the bank has. Take a 256Mb bank as an example, divided into 1 When divided into two arrays, the capacity of each array is 128Mb, and the number of IO ports of the bank is 128; When divided into 4 arrays, the capacity of each array is 64Mb, and the number of IO ports of the bank is 256; when divided into 8 arrays, the capacity of each array is 32Mb, and the number of IO ports of the bank is 512. It can be seen that when the number of bank arrays is larger, the number of IO ports is also larger, and the memory bandwidth is also larger.

The shapes of the first storage area and the second storage area can be diverse. For example, as shown in Figure 13, the channels in the first storage area can be distributed horizontally within the memory chip plane, or as shown in Figure 15, they can also be vertically distributed. Straight distribution.

Mobile devices only have large bandwidth requirements in some scenarios, such as video image processing, artificial intelligence and other scenarios. In other application scenarios, the bandwidth requirements of mobile terminals are smaller. When the bandwidth is increased, the data read and written per unit time increases. , will inevitably increase the read and write power consumption, and the solution of using the overall memory to expand the bandwidth will waste bandwidth. Since the demand for large bandwidth is small, the capacity requirements for the large-bandwidth storage area are low; the demand for low bandwidth is greater, and the capacity requirements for the low-bandwidth storage area are higher. The memory provided by the embodiment of the present application has a first storage area The number of banks is less than the number of banks in the second storage area. For example, the first storage area of the memory 103 shown in Figure 13 includes two channels ch1 and ch2, each channel includes 4 banks, and the first storage area has a total of 8 banks; if The capacity of each bank is 256Mb, so the capacity of the first storage area is 2048Mb. The second storage area includes 6 channels: ch3~ch8. Each channel includes 4 banks. The second storage area has a total of 24 banks. If the capacity of each bank is 256Mb, the capacity of the second storage area is 6114Mb. 3 times the capacity of a storage area. Since the capacity of each bank is basically the same, the number of banks in the first storage area is smaller than the number of banks in the second storage area, and the capacity of the first storage area is smaller than the capacity of the second storage area; the first storage area is suitable for large bandwidth , low storage capacity usage requirements, while avoiding excessive power consumption; the second storage area is suitable for low bandwidth, large storage capacity usage requirements, which can not only ensure large-capacity storage (second storage area), but also ensure that the memory has Large read and write bandwidth (first storage area).

The first storage area and the second storage area can independently read and write data. For example, the first storage area can only work in large-bandwidth usage scenarios. In low-bandwidth demand usage scenarios, the first storage area can be configured as The closed state can reduce the power consumption of the memory; in addition, the number of banks in the first storage area is smaller than the number of banks in the second storage area, and the scale of the first storage area is smaller. Compared with the solution to increase the overall bandwidth of the memory, this application implements The memory provided in the example can achieve lower reading and writing power consumption.

The memory provided by the embodiment of the present application includes a first storage area and a second storage area. The first storage area and the second storage area can be read and written independently. The first storage area and the second storage area include multiple storage areas with the same capacity. bank, where the number of banks in the first storage area is less than the number of banks in the second storage area, and the banks located in the first storage area are divided into finer granularities and have more arrays; the banks located in the second storage area have With a smaller number of arrays, the same memory chip simultaneously provides a large-bandwidth, small-capacity first storage area and a small-bandwidth, large-capacity second storage area, taking into account the bandwidth and capacity of the main memory of the mobile device SoC. requirements, and the first storage area and the second storage area can be read and written independently. Compared with increasing the bandwidth of the entire memory, the memory provided by the embodiment of the present application only improves the read and write bandwidth of the first storage area, and The first storage area only occupies a smaller part of the entire memory area, so it can achieve lower reading and writing power consumption.

In mobile devices, the main memory and the SoC are usually on different dies. However, in order to reduce the internal space occupation of the device and simplify wiring, the SoC and the main memory are usually packaged in the same package.

For example, refer to Figure 16. Figure 16 shows a chip stack structure provided by an embodiment of the present application, including an SoC and a memory 103. The SoC and the memory 103 are stacked. The SoC and the memory 103 are connected through a contact (bump) and a silicon pass. Through-silicon-via (TSV) technology realizes the transmission of data signals, control signals and address signals, so that the SoC can read data from the memory 103 or write data to the memory 103.

The memory 103 includes a first storage area and a second storage area. The first storage area and the second storage area can be read and written independently. The first storage area and the second storage area include a plurality of banks with the same capacity, where The number of banks in the first storage area is smaller than the number of banks in the second storage area, and the banks located in the first storage area are divided into finer granularities, with more arrays and more IO ports, so the first storage area A higher density of contacts is required between the second storage area and the SoC; the bank located in the second storage area has a smaller number of arrays and fewer IO ports, so a lower density of contacts is required between the second storage area and the SoC. In this way, the same memory 103 chip simultaneously provides a first storage area with large bandwidth and small capacity and a second storage area with small bandwidth and large capacity, taking into account the main memory bandwidth and capacity requirements of the mobile device SoC.

The first storage area and the second storage area can each be provided with one or more channels, so that the first storage area and the second storage area can be independently accessed or read and write data. For example, the memory 103 is provided with a first data bus, a third an address bus and a first control bus; the memory 103 is also provided with a second data bus, a second address bus and a second control bus, wherein the first data bus, the first control bus and the first address bus are used to implement the first storage The second data bus, the second control bus and the second address bus are used to read and write data in the second storage area.

A first memory controller and a second memory controller are respectively provided in the SoC corresponding to the first storage area and the second storage area of the memory 103. The first memory controller connects the first data bus, the first control bus and the third memory controller. An address bus is connected to the first storage area for realizing read and write control of the first storage area of the memory 103. The second memory controller communicates with the second storage area through the second data bus, the second control bus and the second address bus. The connection is used to realize read and write control of the second storage area of the memory 103.

SoC and main memory can adopt a variety of packaging forms, such as 2.5D packaging, 3D packaging, multichip module (MCM) packaging, and package on package (PoP) packaging. For example, on the basis of Figure 16, refer to Figure 17, which shows a chip packaging structure provided by the embodiment of the present application. The chip packaging structure includes a packaging substrate and the above-mentioned chip stacking structure. The chip stacking structure is arranged on the packaging substrate. This packaging form in which all chips are stacked together is called 3D packaging.

The chip stack structure here includes SoC and memory 103. In the chip packaging structure, as shown in Figure 18, the SoC can be close to the packaging substrate and the memory 103 is far away from the packaging substrate; as shown in Figure 17, the memory 103 can also be close to the packaging substrate. , the SoC is far away from the packaging substrate.

Combined with Figure 19, Figure 19 shows another chip packaging structure provided by an embodiment of the present application, including a packaging substrate, an SoC and a memory 103. The packaging substrate includes a first plane, and the first plane includes a first area and a first area that do not want to intersect. In the second area, the SoC is arranged in the first area, and the memory 103 is arranged in the second area. The memory 103 is electrically connected to the SoC through connecting lines. This type of packaging that assembles multiple chips on the same packaging substrate is called multichip module (MCM) packaging.

The memory 103 simultaneously provides a first storage area with large bandwidth and small capacity and a second storage area with small bandwidth and large capacity, taking into account the bandwidth and capacity requirements of the main memory of the mobile device SoC. However, in some cases, the memory 103 The capacity is limited and cannot meet the SoC's demand for main memory capacity. In this way, the capacity can be expanded by stacking multiple memory chips.

Exemplarily, refer to FIG. 20 , which shows another chip stack structure provided by an embodiment of the present application, including an SoC and multiple memories. At least one memory among the multiple memories here is provided by the previous embodiment of the present application. The memory 103 includes a first storage area with large bandwidth and small capacity, and a second storage area with small bandwidth and large capacity.

For example, the chip stack structure includes an SoC, a memory 103 and a memory 105. The memory 103 includes a first storage area and a second storage area. The first storage area and the second storage area can be read and written independently. The first storage area and the second storage area can be read and written independently. The second storage area includes multiple banks with the same capacity. The number of banks in the first storage area is smaller than the number of banks in the second storage area, and the banks located in the first storage area are divided into finer granularities and have more arrays. Quantity; the bank located in the second storage area has a smaller number of arrays, so that the same memory 103 chip provides both a large bandwidth and small capacity first storage area and a small bandwidth and large capacity second storage area, taking into account Mobile device SoC’s requirements for main memory bandwidth and capacity. The number of arrays of each bank in the storage area of the memory 105 is the same, and the bandwidth provided is also the same. For example, the number of arrays of each bank in the storage area of the memory 105 is the same as the number of arrays of each bank in the second storage area of the memory 103. , so that the memory 105 can have the same read and write bandwidth as the second storage area of the memory 103 .

Based on the chip stack structure shown in Figure 20, this embodiment of the present application provides another chip packaging structure, including a packaging substrate, an SoC and multiple memories. Among the multiple memories here, at least one memory is provided by the previous embodiment of the present application. The memory 103 includes a first storage area with large bandwidth and small capacity, and a second storage area with small bandwidth and large capacity.

For example, referring to Figure 21, the chip packaging structure includes a packaging substrate, SoC, memory 103 and memory 105, wherein the memory 103 includes a first storage area with large bandwidth and small capacity and a second storage area with small bandwidth and large capacity, wherein the The number of banks in one storage area is smaller than the number of banks in the second storage area. The banks located in the first storage area are divided into finer granularities and have more arrays; the banks located in the second storage area have fewer arrays. , taking into account the bandwidth and capacity requirements of mobile device SoC for main memory. The structure of memory 105 is different from that of memory 103. The number of arrays of each bank in the storage area of memory 105 is the same. For example, the number of arrays of each bank in the storage area of memory 105 is the same as that of each bank in the second storage area of memory 103. number of arrays, so that the second memory of memory 105 can be combined with the second memory of memory 103 The storage area has the same read and write bandwidth.

Illustratively, referring to Figure 22, this embodiment of the present application also provides another chip packaging structure. The chip packaging structure includes a packaging substrate, an SoC, a memory 103 and a memory 105. The memory 103 includes a large-bandwidth, small-capacity first memory. area and a second storage area with small bandwidth and large capacity. The number of banks in the first storage area is smaller than the number of banks in the second storage area. The banks located in the first storage area are divided into finer granularities and have more arrays. ; The bank located in the second storage area has a smaller number of arrays, taking into account the main memory bandwidth and capacity requirements of the mobile device SoC. The structure of the memory 105 is the same as that of the memory 103, which is equivalent to doubling the storage capacity of the large-bandwidth storage area and the low-bandwidth storage area provided by the memory 103 at the same time.

The above is only an explanation of the solution for expanding the main memory capacity in a stacking manner provided by the embodiment of the present application. In any packaging form, multiple memory chips can be stacked to expand the capacity of the main memory. The stacked multiple memory chips may include at least one memory 103 provided in the previous embodiments of the present application, that is, a memory including a large-bandwidth, low-capacity first storage area and a low-bandwidth, large-capacity second storage area. Of course, stacking All of the multiple memory chips may be the memory 103 provided in the previous embodiments of the present application.

The stacking methods of each chip stack structure provided by the embodiments of the present application include one or more of the following methods, such as: through-silicon-via (TSV) connection, chip on chip (Chip on chip) Chip), chip on wafer (Chip on Wafer), wafer on wafer (wafer on wafer), and of course other stacking methods are also possible.

MCM packaging encapsulates multiple chips on the same packaging substrate. On this basis, memory chips can also be stacked to expand the capacity of main memory. For example, on the basis of Figure 19, referring to Figure 23, the embodiment of the present application provides another chip packaging structure, including a packaging substrate, SoC and multiple memories; the packaging substrate includes a first plane, and the first plane includes an unintended The first area and the second area, the SoC is disposed in the first area; a plurality of memory stacks are disposed in the second area to form a chip stack structure, and at least one of the plurality of memories is the memory provided in the previous embodiment of the present application, that is, it includes a large bandwidth , a low-capacity first storage area and a low-bandwidth, large-capacity second storage area memory 103. Of course, the multiple stacked memory chips may all be the memories 103 provided in the previous embodiments of the present application.

In addition, since the SoC can independently access the first storage area and the second storage area, that is to say, taking the memory 103 and the memory 105 as an example, the memory 103 includes the first storage area and the second storage area, and the bank of the first storage area The number of arrays is different from the number of arrays of banks in the second storage area. For example, the number of arrays of banks in the first storage area is greater than the number of arrays of banks in the second storage area. The SoC is provided with a first memory controller and a second memory controller. The first memory controller is used to perform read and write control on the first storage area, and the second memory controller is used to perform read and write control on the second storage area; the number of arrays of each bank in the storage area of the memory 103 is the same, for example, The number of arrays of each bank in the storage area of the memory 103 is the same as the number of banks in the second storage area of the memory 103. In this way, the bandwidth of the memory 105 and the second storage area of the memory 103 can be the same, and the SoC can use the second memory controller to The memory 105 performs read and write control.

Since the memory 103 has two independent storage areas, the first storage area and the second storage area need to be provided with an address bus, a control bus and a data bus respectively; while the memory 105 only has one overall storage area, so there is no connection between the memory 103 and the SoC. The interconnection lines used for read and write control are more and more complex, and the interconnection lines used for read and write control between the memory 105 and the SoC are fewer and simpler, and in the case of stacking settings, part of the interconnection lines between the memory 103 and the SoC can be used. Interconnect lines, so in the case of multiple memory stacks, the memory with the first storage area and the second storage area is located on the side closer to the SoC among the multiple stacked memories to reduce the length of the interconnect lines and reduce the wiring. Capacitors reduce the complexity of read and write control circuits such as address decoders, and further reduce read and write power consumption.

In addition, the memory 103 includes a first storage area and a second storage area. The first storage area has a larger read and write bandwidth and can meet the high bandwidth requirements of high computing power modules in the SoC. The high computing power modules here generally include graphics. processor (graphic processing unit, GPU) or network processor (neural-network processing unit, NPU), etc., then when the SoC is stacked on the memory, for example, see Figure 24, the high computing power module of the SoC can be combined with the third A storage area is aligned in the stacking direction. For example, the projection of the SoC's high computing power module on the packaging substrate and the projection of the first storage area on the packaging substrate are located in the same area. This can also reduce the length of the interconnection line between the two. Reducing the connection capacitance will help reduce reading and writing power consumption.

An embodiment of the present application also provides a storage device. The storage device includes a printed circuit board (PCB) and a memory connected to the printed circuit board. The memory can be any of the memories provided above. . Wherein, the printed circuit board is used to provide electrical connections for electronic components included in the memory. Optionally, the storage device can be a computer, Different types of user devices or terminal devices such as mobile phones, tablets, wearable devices, and vehicle-mounted devices.

Optionally, the storage device may further include a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB through solder balls, the memory is fixed on the packaging substrate through solder balls, and the packaging substrate is used to package the memory.

In another aspect of the present application, a storage device is also provided. The storage device includes a first controller, a second controller and a memory. The first controller and the second controller are used to control reading and writing in the memory. The memory may be the memory 103 provided in the embodiment of this application. For example, the storage device can be applied to mobile devices, such as mobile phones, tablet computers, etc., the first controller can be a first memory controller, the second controller can be a second memory controller, and the memory includes large bandwidth, low A first storage area with a large capacity and a second storage area with a low bandwidth and a large capacity, the first memory controller is used to control the reading and writing of the first storage area, and the second memory controller is used to control the reading and writing of the second storage area.

In another aspect of the present application, an electronic device is also provided. The electronic device includes a printed circuit board (PCB) and a chip packaging structure as provided in Figures 17 to 23 in the above embodiments. The chip packaging structure Including memory, SoC and packaging substrate, the chip packaging structure is connected to the printed circuit board, for example, the packaging substrate and the printed circuit board can be electrically connected.

Optionally, the electronic device is different types of user equipment or terminal equipment such as computer systems, mobile phones, tablets, wearable devices, and vehicle-mounted equipment. It should be noted that the above-mentioned relevant descriptions of the memory can be correspondingly cited in the storage device and electronic equipment provided in the present application, and the embodiments of the present application will not be repeated here.

Finally, it should be noted that the above are only specific implementation modes of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application shall be covered by this application. within the scope of protection applied for. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (12)

1. A memory, characterized in that it includes: a first storage area and a second storage area;

   The first storage area and the second storage area each include a plurality of storage banks, each bank includes one or more array arrays, and each of the arrays has the same number of input and output ports;

   Wherein, the number of bank arrays located in the first storage area is different from the number of bank arrays located in the second storage area.
2. The memory according to claim 1, wherein the number of bank arrays located in the first storage area is greater than the number of bank arrays in the second storage area.
3. The memory according to claim 1, wherein the number of bank arrays located in the first storage area is 2 ⁿ times the number of bank arrays located in the second storage area, and n is a positive integer. .
4. The memory of claim 2, wherein the number of banks in the first storage area is smaller than the number of banks in the second storage area.
5. The memory according to any one of claims 1 to 4, characterized in that any two banks have the same capacity.
6. The memory according to any one of claims 1 to 5, characterized in that the memory includes a first data bus connecting the first storage area and a second data bus connecting the second storage area;

   The first data bus is used to read and write data to the first storage area, and the second data bus is used to read and write data to the second storage area.
7. A chip stack structure, characterized in that the chip stack structure includes a system and a chip SoC and one or more memories, and the SoC and the one or more memories are stacked in sequence;

   At least one of the one or more memories is the memory according to any one of claims 1 to 6.
8. The chip stack structure according to claim 7, wherein the stacking method includes one or more of the following methods: through silicon via TSV connection, chip on chip, chip on wafer, wafer Upper wafer.
9. A chip packaging structure, characterized by comprising a packaging substrate and the chip stack structure according to any one of claims 7 to 8, the chip stack structure being arranged on the packaging substrate.
10. A chip packaging structure, characterized in that it includes a packaging substrate, a system-on-chip SoC, and the memory according to any one of claims 1 to 6;

    The packaging substrate includes a first plane, the first plane includes a first area and a second area, the SoC is disposed in the first area, the memory is disposed in the second area, and the memory is connected through lines are electrically connected to the SoC.
11. A chip packaging structure, characterized by including a packaging substrate, a system-level chip and multiple memories;

    The packaging substrate includes a first plane, the first plane includes a first area and a second area, and the SoC is disposed in the first area;

    A plurality of the memory stacks are arranged in the second area to form a chip stack structure, and at least one of the plurality of memories is the memory according to any one of claims 1 to 6;

    The chip stack structure is electrically connected to the SoC through connecting wires.
12. An electronic device, characterized by comprising a printed circuit board and a chip packaging structure as claimed in any one of claims 9 to 11;

    The packaging substrate in the chip packaging structure is electrically connected to the printed circuit board.