CN209765493U

CN209765493U - I2C converting circuit

Info

Publication number: CN209765493U
Application number: CN201920780789.5U
Authority: CN
Inventors: 吕英杰
Original assignee: Tianjin Pengxiang Huaxia Technology Co Ltd
Current assignee: Tianjin Pengxiang Huaxia Technology Co Ltd
Priority date: 2019-05-27
Filing date: 2019-05-27
Publication date: 2019-12-10
Anticipated expiration: 2029-05-27

Abstract

The utility model provides an I2C converting circuit, including SCL converting circuit and SDA converting circuit, SCL converting circuit has MCU controller through SCL terminal electric connection, SDA converting circuit has MCU controller electric connection through SDA terminal; the SCL switching circuit comprises a first phase inverter, a second phase inverter, a first level shifter, a first field effect transistor and a third phase inverter, wherein the input end of the first phase inverter is electrically connected with an SCL terminal, the output end of the first phase inverter is electrically connected with the input end of the second phase inverter, the output end of the second phase inverter is electrically connected with the input end of the first level shifter, and the output end of the first level shifter is connected with the grid electrode of the first field effect transistor. The utility model discloses can realize the signal selection process to signal transmission through signal selection circuit's logic control, circuit structure is simple, the signal transmission of being convenient for.

Description

I2C converting circuit

Technical Field

The utility model relates to a I2C bus technical field, concretely relates to I2C converting circuit.

Background

With the development of integrated circuit technology, electronic products, especially mobile phones, have increasingly stronger performance and higher power consumption, in order to reduce power consumption and improve performance, chip manufacturing adopts high-order processes such as 10nm/16nm, and the logic level of an IO interface is increasingly low, so that currently, LVCOMS 1.8V is common.

In the whole machine application system, besides the application main processor AP, some peripheral main control MCUs such as a battery metering, detecting and managing IC and the like exist, due to the fact that the tube core area is small, the performance requirement is not high and the like, the cost performance is worse in a high-order process, the whole machine application system is relatively suitable for process production with the line width of about 180nm, and the IO interface voltage standard is generally 3.3V in LVCMOS.

in a whole machine application system, an application main processor AP is usually communicated with a peripheral main control MCU through an I2C bus, and the interface logic level standards of the main processor AP and the peripheral main control MCU are different, so that the problem of level conversion exists.

The I2C bus is a bidirectional two-wire synchronous serial bus, which includes two wires, a clock line scl (signal clock line) and a Data line sda (signal Data line), and the I2C bus can be used for Data communication between the master device and the slave device. There are various level standards for master and slave devices on the I2C bus, such as 5V, 3.3V, and 1.8V, and communication between master and slave devices using the I2C bus requires level shifting.

In the existing level conversion design, the converted slave device voltage value is relatively single, the application flexibility is poor, once the circuit is packaged for use, only fixed slave devices are applicable, when the slave devices hooked in an I2C bus circuit are changed, the logic levels supported by the slave devices are also correspondingly changed, at the moment, in order to ensure the correct transmission of signals with different logic levels, the circuit needs to be redesigned, especially the slave power line needs to be rearranged, and the circuit complexity and the hardware design cost can be greatly increased when the I2C level conversion circuit is applied to replace devices with different logic levels.

SUMMERY OF THE UTILITY MODEL

in view of the above, the present invention provides an I2C conversion circuit.

In order to solve the technical problem, the utility model discloses a technical scheme is: an I2C conversion circuit comprises an SCL conversion circuit and an SDA conversion circuit, wherein the SCL conversion circuit is electrically connected with an MCU controller through an SCL terminal, the SDA conversion circuit is electrically connected with the MCU controller through an SDA terminal, and the SCL conversion circuit, the SDA conversion circuit and the MCU controller form bidirectional transmission;

The SCL conversion circuit comprises a first phase inverter, a second phase inverter, a first level shifter, a first field effect transistor and a third phase inverter, wherein the input end of the first phase inverter is electrically connected with the SCL terminal, the output end of the first phase inverter is electrically connected with the input end of the second phase inverter, the output end of the second phase inverter is electrically connected with the input end of the first level shifter, the output end of the first level shifter is connected with the grid electrode of the first field effect transistor, the source electrode of the first field effect transistor is connected with a VCC _ SW terminal, the drain electrode of the first field effect transistor is connected with the input end of the third phase inverter, the output end of the third phase inverter is connected with an SCL _ OUT terminal, and an I2C _ SCL _ W terminal is connected between the output end of the second phase inverter and the first level shifter.

In the present invention, preferably, the input terminal of the first phase inverter is connected to a DVDD terminal through a first resistor.

In the present invention, preferably, the drain electrode of the first field effect transistor is connected to a VCC terminal through a second resistor.

In the present invention, preferably, the SDA conversion circuit includes a fourth inverter, a fifth inverter, a second level shifter, a second field effect transistor, a sixth inverter and a seventh inverter, an input end of the fourth inverter is electrically connected to the SDA terminal, an output end of the fourth inverter is electrically connected to an input end of the fifth inverter, an output end of the fifth inverter is electrically connected to an input end of the second level shifter, an output end of the second level shifter is connected to a gate of the second field effect transistor, a source of the second field effect transistor is connected to the VCC _ SW terminal, a drain of the second field effect transistor is connected to an input end of the sixth inverter, an output end of the sixth inverter is connected to an input end of the seventh inverter, and an SDA _ OUT terminal is connected between an output end of the sixth inverter and an input end of the seventh inverter, an I2C _ SDA _ W terminal is communicated between the output end of the fifth inverter and the input end of the second level shifter.

In the present invention, preferably, an input terminal of the fourth phase inverter is connected to the DVDD terminal through a third resistor.

In the present invention, preferably, the drain electrode of the first field effect transistor is connected to the VCC terminal through a fourth resistor.

In the utility model, preferably, the SDA conversion circuit is electrically connected to a signal selection circuit through a third field effect transistor, the signal selection circuit includes a fourth field effect transistor, an eighth phase inverter, a selection switch, a ninth phase inverter, a fifth field effect transistor and a sixth field effect transistor, an output terminal of the seventh phase inverter is connected to a gate of the third field effect transistor, a gate and a source of the third field effect transistor are both connected to the VCC _ SW terminal, a drain of the third field effect transistor is connected to a gate of the fourth field effect transistor, a gate of the fourth field effect transistor is connected to an input terminal of the eighth phase inverter, an output terminal of the eighth phase inverter is connected to a contact at one end of the selection switch, the other end of the selection switch is connected to an input terminal of the ninth phase inverter, an output terminal of the ninth phase inverter is connected to a gate of the fifth field effect transistor, and the source electrode of the fifth field effect transistor and the source electrode of the sixth field effect transistor are both connected with the SDA terminal, and the grid electrode of the sixth field effect transistor is connected with an ACK terminal.

In the present invention, preferably, the a contact and the B contact of the selector switch are both connected to CHIP _ SELECT terminals, and the B contact of the selector switch is connected to I2C _ SDA _ R terminals.

In the present invention, preferably, drain electrodes of the fourth field effect transistor, the fifth field effect transistor and the sixth field effect transistor are all connected to a VSS terminal.

In the present invention, preferably, the first field effect transistor, the second field effect transistor, the fourth field effect transistor, the fifth field effect transistor and the sixth field effect transistor are all set to be MOS type field effect transistors, and the third field effect transistor is set to be an NMOS transistor.

The utility model has the advantages and positive effects that:

(1) through the mutual cooperation of the SCL conversion circuit, the SDA conversion circuit and the signal selection circuit, the I2C signal from the MCU control machine is firstly subjected to level conversion through the level converter and then transmitted to the LSI1 of the upper IC circuit and the LSI2 of the upper IC circuit, and in addition, the signal lines of the LSI1 of the upper IC circuit and the LSI2 of the upper IC circuit are transmitted to the MCU controller through the level shifting process, so that the bidirectional transmission of the I2C signal between the upper IC circuit and the MCU controller is realized.

(2) The signal selection circuit is arranged to comprise a fourth field effect tube, an eighth phase inverter, a selection switch, a ninth phase inverter, a fifth field effect tube and a sixth field effect tube, the output end of the seventh phase inverter is connected with the grid electrode of the third field effect tube, the grid electrode and the source electrode of the third field effect tube are both connected with a VCC _ SW terminal, the drain electrode of the third field effect tube is connected with the grid electrode of the fourth field effect tube, the grid electrode of the fourth field effect tube is connected with the input end of the eighth phase inverter, the output end of the eighth phase inverter is connected with an A contact at one end of the selection switch, the other end of the selection switch is connected with the input end of the ninth phase inverter, the output end of the ninth phase inverter is connected with the grid electrode of the fifth field effect tube, the source electrode of the fifth field effect tube and the source electrode of the sixth field effect tube are both connected with an SDA terminal, the grid electrode of the sixth field effect tube, the circuit structure is simple, and the signal transmission is more convenient and accurate.

Drawings

Fig. 1 is a schematic circuit diagram of an SCL converter circuit of an I2C converter circuit of the present invention;

Fig. 2 is a schematic circuit diagram of an SDA conversion circuit of an I2C conversion circuit of the present invention;

Fig. 3 is a schematic diagram of signal transmission from the MCU controller to the protection IC of the I2C switching circuit according to the present invention;

Fig. 4 is a schematic diagram of the signal transmission from LSI2 to MCU controller of an I2C conversion circuit of the present invention;

Fig. 5 is a schematic diagram of signal transmission from LSI1 to MCU controller of an I2C conversion circuit according to the present invention;

In the figure: 1-SCL conversion circuit; 2-SDA conversion circuit; a 3-SCL terminal; a 4-SDA terminal; 5-a first inverter; 6-a second inverter; 7-a first level shifter; 8-a first field effect transistor; 9-a third inverter; 10-VCC _ SW terminal; 11-SCL _ OUT terminal; 12-I2C _ SCL _ W terminal; 13-a first resistance; 14-DVDD terminal; 15-a second resistance; a 16-VCC terminal; 17-a fourth inverter; 18-a fifth inverter; 19-a second level shifter; 20-a second field effect transistor; 21-a sixth inverter; 22-seventh inverter; 23-SDA _ OUT terminal; a 24-I2C _ SDA _ W terminal; 25-a third resistance; 26-a fourth resistance; 27-a third field effect transistor; 28-a fourth field effect transistor; 29-eighth inverter; 30-a selection switch; 31-ninth inverter; 32-a fifth field effect transistor; 33-a sixth field effect transistor; 34-ACK terminal; 35-CHIP _ SELECT terminal; 36-I2C _ SDA _ R terminal; 37-VSS terminal.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1 to 5, the utility model provides an I2C converting circuit, including SCL converting circuit 1 and SDA converting circuit 2, SCL converting circuit 1 has the MCU controller through SCL terminal 3 electric connection, SDA converting circuit 2 through SDA terminal 4 with MCU controller electric connection, SCL converting circuit 1, SDA converting circuit 2 and the MCU controller constitute two-way transmission;

In the present embodiment, further, the SCL switching circuit 1 includes a first inverter 5, a second inverter 6, a first level shifter 7, a first field effect transistor 8 and a third inverter 9, the input terminal of the first inverter 5 is electrically connected to the SCL terminal 3, the output terminal of the first inverter 5 is electrically connected to the input terminal of the second inverter 6, the output terminal of the second inverter 6 is electrically connected to the input terminal of the first level shifter 7, the output end of the first level shifter 7 is connected with the grid electrode of the first field effect transistor 8, the source electrode of the first field effect transistor 8 is connected with a VCC _ SW terminal 10, the drain of the first field effect transistor 8 is connected to the input terminal of the third inverter 9, the output terminal of the third inverter 9 is connected to an SCL _ OUT terminal 11, an I2C _ SCL _ W terminal 12 is connected between the output of the second inverter 6 and the first level shifter 7.

In this embodiment, a DVDD terminal 14 is connected to an input terminal of the first inverter 5 through a first resistor 13.

In this embodiment, the drain of the first field effect transistor 8 is further connected to a VCC terminal 16 via a second resistor 15.

In this embodiment, further, the SDA conversion circuit 2 includes a fourth inverter 17, a fifth inverter 18, a second level shifter 19, a second field effect transistor 20, a sixth inverter 21 and a seventh inverter 22, an input end of the fourth inverter 17 is electrically connected to the SDA terminal 4, an output end of the fourth inverter 17 is electrically connected to an input end of the fifth inverter 18, an output end of the fifth inverter 18 is electrically connected to an input end of the second level shifter 19, an output end of the second level shifter 19 is connected to a gate of the second field effect transistor 20, a source of the second field effect transistor 20 is connected to the VCC _ SW terminal 10, a drain of the second field effect transistor 20 is connected to an input end of the sixth inverter 21, an output end of the sixth inverter 21 is connected to an input end of the seventh inverter 22, an SDA _ OUT terminal 23 is connected between the output end of the sixth inverter 21 and the input end of the seventh inverter 22, and an I2C _ SDA _ W terminal 24 is communicated between the output end of the fifth inverter 18 and the input end of the second level shifter 19.

In this embodiment, further, the input terminal of the fourth inverter 17 is connected to the DVDD terminal 14 through a third resistor 25.

In this embodiment, further, the drain of the first fet 8 is connected to the VCC terminal 16 through a fourth resistor 26.

In this embodiment, the SDA conversion circuit 2 is further electrically connected to a signal selection circuit through a third field-effect transistor 27, the signal selection circuit includes a fourth field-effect transistor 28, an eighth phase-effect transistor 29, a selection switch 30, a ninth phase-effect transistor 31, a fifth field-effect transistor 32 and a sixth field-effect transistor 33, an output terminal of the seventh phase-effect transistor 22 is connected to a gate of the third field-effect transistor 27, a gate and a source of the third field-effect transistor 27 are both connected to the VCC _ SW terminal 10, a drain of the third field-effect transistor 27 is connected to a gate of the fourth field-effect transistor 28, a gate of the fourth field-effect transistor 28 is connected to an input terminal of the eighth phase-effect transistor 29, an output terminal of the eighth phase-effect transistor 29 is connected to an a contact at one end of the selection switch 30, and the other end of the selection switch 30 is connected to an input terminal of the ninth phase, the output end of the ninth inverter 31 is connected to the gate of the fifth field effect transistor 32, the source of the fifth field effect transistor 32 and the source of the sixth field effect transistor 33 are both connected to the SDA terminal 4, and the gate of the sixth field effect transistor 33 is connected to the ACK terminal 34.

In the present embodiment, CHIP _ SELECT terminal 35 is connected to both the a contact and the B contact of selection switch 30, and I2C _ SDA _ R terminal 36 is connected to the B contact of selection switch 30.

in this embodiment, the drains of the fourth fet 28, the fifth fet 32, and the sixth fet 33 are all connected to a VSS terminal 37.

In this embodiment, further, the first fet 8, the second fet 20, the fourth fet 28, the fifth fet 32, and the sixth fet 33 are all configured as MOS fets, and the third fet 27 is configured as an NMOS transistor.

The utility model discloses a theory of operation and working process as follows: when the signal of the MCU controller is transmitted to the upper IC circuit, firstly, the SCL converting circuit 1 receives the signal from the MCU controller through the SCL terminal 3, the signal is transmitted to the first level shifter 7 through the first inverter 5 and the second inverter 6 for level shifting, and then transmitted to the upper IC circuit through the first fet 8 and the third inverter 9, as shown in fig. 3, and at the same time, the SDA converting circuit 2 receives the signal from the MCU controller through the SDA terminal 4, the signal is transmitted to the second level shifter 19 through the fourth inverter 17 and the fifth inverter 18 for level shifting, and then transmitted to the upper IC circuit through the sixth inverter 21, thereby completing the signal transmission from the MCU controller to the upper IC circuit; when a signal is transmitted from the LSI2 to the MCU controller, the SDA conversion circuit 2 receives the signal from the SDA _ OUT terminal 32, at which time the signal is transmitted to the signal selection circuit via the seventh inverter 22 and the third field effect transistor 27, the signal is transmitted through the fourth field effect transistor 28 and the eighth inverter 29, the CHIP _ SELECT terminal 35 performs signal selection for CHIP connection, the a contact of the selection switch 30 is on, the B contact is off, as shown in fig. 4, and thus the signal transmission from the LSI2 of the upper IC circuit to the MCU controller is completed; when signal transmission is performed from the LSI1 of the upper IC circuit to the MCU controller, the SDA output signal from the LSI1 of the upper IC circuit is received via the I2C _ SDA _ R terminal 36, the CHIP _ SELECT terminal 35 performs signal selection for CHIP connection, the a contact of the selection switch 30 is turned off, and the B contact is turned on, as shown in fig. 5, thereby completing signal transmission from the LSI1 of the upper IC circuit to the MCU controller.

The embodiments of the present invention have been described in detail, but the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by the present patent.

Claims

1. The I2C conversion circuit comprises an SCL conversion circuit (1) and an SDA conversion circuit (2), wherein the SCL conversion circuit (1) is electrically connected with an MCU controller through an SCL terminal (3), the SDA conversion circuit (2) is electrically connected with the MCU controller through an SDA terminal (4), and the SCL conversion circuit (1), the SDA conversion circuit (2) and the MCU controller form bidirectional transmission;

The SCL conversion circuit (1) comprises a first phase inverter (5), a second phase inverter (6), a first level shifter (7), a first field effect transistor (8) and a third phase inverter (9), wherein the input end of the first phase inverter (5) is electrically connected with the SCL terminal (3), the output end of the first phase inverter (5) is electrically connected with the input end of the second phase inverter (6), the output end of the second phase inverter (6) is electrically connected with the input end of the first level shifter (7), the output end of the first level shifter (7) is connected with the grid electrode of the first field effect transistor (8), the source electrode of the first field effect transistor (8) is connected with a VCC _ SW terminal (10), the drain electrode of the first field effect transistor (8) is connected with the input end of the third phase inverter (9), the output end of the third phase inverter (9) is connected with an SCL _ OUT terminal (11), an I2C _ SCL _ W terminal (12) is connected between the output end of the second inverter (6) and the first level shifter (7).

2. An I2C switching circuit according to claim 1, characterized in that the input of the first inverter (5) is connected to the DVDD terminal (14) via a first resistor (13).

3. An I2C switching circuit according to claim 1, wherein the drain of the first FET (8) is connected to a VCC terminal (16) through a second resistor (15).

4. The I2C switching circuit of claim 2, wherein the SDA switching circuit (2) comprises a fourth inverter (17), a fifth inverter (18), a second level shifter (19), a second field effect transistor (20), a sixth inverter (21) and a seventh inverter (22), an input of the fourth inverter (17) is electrically connected to the SDA terminal (4), an output of the fourth inverter (17) is electrically connected to an input of the fifth inverter (18), an output of the fifth inverter (18) is electrically connected to an input of the second level shifter (19), an output of the second level shifter (19) is connected to a gate of the second field effect transistor (20), a source of the second field effect transistor (20) is connected to the VCC _ SW terminal (10), and a drain of the second field effect transistor (20) is connected to an input of the sixth inverter (21), an output end of the sixth inverter (21) is connected with an input end of the seventh inverter (22), an SDA _ OUT terminal (23) is connected between the output end of the sixth inverter (21) and the input end of the seventh inverter (22), and an I2C _ SDA _ W terminal (24) is communicated between the output end of the fifth inverter (18) and the input end of the second level shifter (19).

5. An I2C switching circuit according to claim 4, wherein the input of the fourth inverter (17) is connected to the DVDD terminal (14) via a third resistor (25).

6. an I2C switching circuit according to claim 3, wherein the drain of the first FET (8) is connected to the VCC terminal (16) through a fourth resistor (26).

7. The I2C switching circuit of claim 4, wherein the SDA switching circuit (2) is electrically connected with a signal selection circuit through a third FET (27), the signal selection circuit comprises a fourth FET (28), an eighth inverter (29), a selection switch (30), a ninth inverter (31), a fifth FET (32) and a sixth FET (33), the output terminal of the seventh inverter (22) is connected with the gate of the third FET (27), the gate and the source of the third FET (27) are both connected with the VCC _ SW terminal (10), the drain of the third FET (27) is connected with the gate of the fourth FET (28), the gate of the fourth FET (28) is connected with the input terminal of the eighth inverter (29), the output terminal of the eighth inverter (29) is connected with one A contact of the selection switch (30), the other end of the selection switch (30) is connected with the input end of a ninth phase inverter (31), the output end of the ninth phase inverter (31) is connected with the grid electrode of a fifth field effect tube (32), the source electrode of the fifth field effect tube (32) and the source electrode of a sixth field effect tube (33) are both connected with the SDA terminal (4), and the grid electrode of the sixth field effect tube (33) is connected with an ACK terminal (34).

8. An I2C switching circuit according to claim 7, characterized in that CHIP _ SELECT terminal (35) is connected to both the A and B contacts of the selection switch (30), and I2C _ SDA _ R terminal (36) is connected to the B contact of the selection switch (30).

9. An I2C switching circuit according to claim 7, characterized in that the drains of the fourth FET (28), the fifth FET (32) and the sixth FET (33) are all connected to a VSS terminal (37).

10. An I2C switching circuit according to claim 7, characterized in that the first fet (8), the second fet (20), the fourth fet (28), the fifth fet (32) and the sixth fet (33) are MOS fets and the third fet (27) is an NMOS fet.