CN209729885U - Encapsulate the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ - Google Patents
Encapsulate the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ Download PDFInfo
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- CN209729885U CN209729885U CN201920911775.2U CN201920911775U CN209729885U CN 209729885 U CN209729885 U CN 209729885U CN 201920911775 U CN201920911775 U CN 201920911775U CN 209729885 U CN209729885 U CN 209729885U
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Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
This application provides the ceramic shell for encapsulating double metal-oxide-semiconductors and replacement SOP8 plastic device in situ, including base of ceramic, becket frame, metal cover boards, lower buried layer metalization layer, upper buried layer metalization layer, side metallization, 8 pins, 8 inner via holes metallization columns, 8 external groove metalization layers；It is filled with by the match group of multi-layer ceramics and multiple-layer metallization and the synchronous welding of via metal cofiring, ceramic metallization face and different materials metal, multiple material and wetting of the silver-copper brazing alloy on different materials surface is distributed, realize the optimization and combination among the strong ones of structure optimization, optimization of material and processing technology, so that the ceramic shell provided can be used for encapsulating binary channels metal-oxide-semiconductor, SOP8 plastic device can be replaced in situ, and resistance is smaller, intensity is higher, reliability is higher, high temperature resistance is more preferable.
Description
Technical field
The utility model relates to technical field of semiconductor encapsulation, encapsulate double metal-oxide-semiconductors and replacement in situ more particularly, to a kind of
The ceramic shell of SOP8 plastic device.
Background technique
Metal-oxide-semiconductor full name metal-oxide-semiconductor field effect transistor or metal insulater-semiconductor field effect
Transistor is answered, English name metal oxide semiconductor belongs to the insulated-gate type in field-effect tube, therefore, MOS pipe
Sometimes it is also known as isolated gate FET.Metal-oxide-semiconductor is high with input impedance, noise is low, thermal stability is good；Manufacturing process letter
Single, radiation by force, thus is normally used for amplifying circuit or switching circuit.
Chip is also referred to as integrated circuit (English: IC is made in integrated circuit, abbreviation) or microcircuit
(microcircuit), microchip (microchip), wafer/chip (chip) are a kind of that circuit is (main in electronics
Including semiconductor equipment, also including passive component etc.) mode of miniaturization, and it manufactures on semiconductor wafer surface often.
Encapsulation (Package) be integrated circuit assembly be chip final products process, briefly, be exactly
The integrated circuit die (Die) that Foundry is produced is placed on the substrate that one piece is played the role of carrying, and pin is extracted,
Then fixation is packaged into as an entirety.By taking " dual-inline package " (Dual In-line Package, DIP) as an example,
The process of encapsulation are as follows: the bare die (Die) marked on wafer is close to be placed in the fixed work of support after test passes
In substrate (there are also one layer of good materials of heat dissipation in substrate), then with more wires the metal contact on Die
(Pad, pad), by being welded to connect, is then embedded to resin, is sealed with plastic case, form core with external pin
Piece is whole.
SOP (Small Outline Package) small outline packages refer to wing (L shape) lead of gull from two sides of encapsulation
A kind of surface mount packages that face is drawn.1968~1969 years PHILIPS Co.s just develop small outline packages (SOP).After
Gradually derive SOJ (the small outline packages of J-type pin), TSOP (small thin outline package), VSOP (very small outline packages), SSOP
(scaled-down version SOP), TSSOP (thin scaled-down version SOP) and SOT (small outline transistor), SOIC (small outline integrated circuit) etc..
It is no more than 40 field in pin number, SOP is universal most wide surface mount package, and typical pin center is away from 1.27mm
(50mil), it is other to have 0.65mm, 0.5mm；Number of pins is mostly 8~32；SOP of the assembly height less than 1.27mm is also referred to as TSOP.
Ceramic metallization, including buried layer metallization, via metal and surface metalation.Aluminium oxide ceramics metallization
Common method includes: chemical nickel plating, sintering by Ag method, physical vapour deposition (PVD) and chemical vapor deposition, tungsten cofiring method, molybdenum manganese method.
The standard size device products of the fields such as space flight at present, aviation, ship, weapons wilderness demand SOP8 series, it is desirable that
The features such as integrated, low resistance, low thermal resistance, impact resistance be good, high reliablity provides safeguard to improve whole aircraft reliability.
Plastic packaging SOP8 device outer case material is epoxy resin, and self-strength is poor, cannot bear 150 DEG C or more high temperature, no
It can be used for highly reliable devices field.SOP8 (SO8) plastic device is general international standard outline devices, and there are many models, mainly
For civilian goods, market demand is very big.Plastic device is because the performances such as high temperature resistant, mechanical resistant impact, leakproofness are poor, Bu Nengyong
In military products.
Therefore, SOP8 plastic device can be substituted in situ by how providing one kind, and for encapsulating double metal-oxide-semiconductors, and resistance it is smaller,
The problem of package casing that intensity is higher, reliability is higher, high temperature resistance is more preferable etc. is those skilled in the art's urgent need to resolve.
Utility model content
The purpose of this utility model is to provide a kind of ceramics for encapsulating double metal-oxide-semiconductors and replacement SOP8 plastic device in situ are outer
Shell.
In order to solve the above technical problems, technical solution provided by the utility model are as follows:
Encapsulate the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ, including base of ceramic, becket frame, gold
Belong to cover board, the lower buried layer metalization layer as conducting channel, the upper buried layer metalization layer as conducting channel, surface metalation
Layer, 8 pins, 8 inner via holes metallization columns, 8 external groove metalization layers；
The base of ceramic is top opening-box, is provided on the inner box bottom surface of the base of ceramic for placing metal-oxide-semiconductor
The pit of chip；
The lower buried layer metalization layer, upper buried layer metalization layer, side metallization, 8 inner via holes metallization columns, 8
External groove metalization layer and 8 pins be in the base of ceramic during sintering porcelain into pre-buried sintering be connected to it is described
In base of ceramic；
The lower buried layer metalization layer is embedded in the lower section of the pit and the hole bottom wall as the pit in advance, buries under described
Layer metalization layer includes lower conductive pattern one and lower conductive pattern two, and the lower conductive pattern one and lower conductive pattern two are mutual
Every with electrical isolation, the lower conductive pattern one with welding thereon place a metal-oxide-semiconductor chip and with corresponding metal-oxide-semiconductor chip
Electrode points electrical connection on lower surface, the lower conductive pattern two with welding thereon place another metal-oxide-semiconductor chip and with phase
Electrode points electrical connection on the lower surface for the metal-oxide-semiconductor chip answered；
The upper buried layer metalization layer the is embedded in the base of ceramic in advance and remaining inner box bottom surface in addition to the pit
On, the upper buried layer metalization layer includes upper conductive pattern one, upper conductive pattern two, upper conductive pattern three and upper conductive pattern
Four, the upper conductive pattern one, upper conductive pattern two, upper conductive pattern three and upper conductive pattern four be respectively used to it is corresponding
Electrode points electrical connection on the upper surface of metal-oxide-semiconductor chip, the upper conductive pattern one, upper conductive pattern two, upper conductive pattern three
And upper conductive pattern four is spaced apart from each other to be electrically insulated；
The side metallization is embedded in the open box of the base of ceramic along face in advance；
8 pins are ceramic metallized layer, and 8 pins are all set on the outer box bottom surface of the base of ceramic to be used for
It can so that the arrangement pattern of 8 pins on the base of ceramic is identical as the arrangement pattern of 8 pins of SOP8 plastic device
SOP8 plastic device is replaced in situ, 8 pins are spaced apart from each other to be electrically insulated；
8 inner via hole metallization columns are embedded in respectively in 8 through-holes in the base of ceramic, 8 inner via hole metallization
Column and 8 through-holes correspond, and 8 external groove metalization layers are separately positioned on 8 on the outer side surface of the base of ceramic
In semi-circular cross-sections groove, 8 external groove metalization layers are corresponded with 8 semi-circular cross-sections grooves；
The lower conductive pattern one is electrically connected with 2 pins respectively with lower conductive pattern two；
The upper conductive pattern one, upper conductive pattern two, upper conductive pattern three and upper conductive pattern four respectively with it is surplus
4 pins of remaininging correspond electrical connection；
2 pins being electrically connected with the lower conductive pattern one and 2 pin positions being electrically connected with lower conductive pattern two
A side edge in the outer box bottom surface of the base of ceramic, with upper conductive pattern one, upper conductive pattern two, upper conductive pattern three with
And 4 pins of residue for being electrically connected of upper conductive pattern four are located at the B side edge of the outer box bottom surface of the base of ceramic, the side A and
The side B is two sides being parallel to each other；
Each of 2 pins being electrically connected with the lower conductive pattern one pin passes through in 1 corresponding to it
Via metal column and 1 external groove metalization layer are electrically connected with the lower surface of the lower conductive pattern one；
Each of 2 pins being electrically connected with the lower conductive pattern two pin passes through in 1 corresponding to it
Via metal column and 1 external groove metalization layer are electrically connected with the lower surface of the lower conductive pattern two；
1 pin being electrically connected with the upper conductive pattern one passes through 1 inner via hole metallization column and 1 corresponding to it
A external groove metalization layer is electrically connected with the lower surface of the upper conductive pattern one；
1 pin being electrically connected with the upper conductive pattern two passes through 1 inner via hole metallization column and 1 corresponding to it
A external groove metalization layer is electrically connected with the lower surface of the upper conductive pattern two；
1 pin being electrically connected with the upper conductive pattern three passes through 1 inner via hole metallization column and 1 corresponding to it
A external groove metalization layer is electrically connected with the lower surface of the upper conductive pattern three；
1 pin being electrically connected with the upper conductive pattern four passes through 1 inner via hole metallization column and 1 corresponding to it
A external groove metalization layer is electrically connected with the lower surface of the upper conductive pattern four；
The top of inner via hole metallization column and the following table of corresponding time buried layer metalization layer or upper buried layer metalization layer
Face is the top of external groove metalization layer and corresponding in the integrally connected of the base of ceramic sintered into during sintering porcelain into
Lower buried layer metalization layer or upper buried layer metalization layer lower surface be being sintered during sintering porcelain into the base of ceramic
At integrally connected, the bottom end of inner via hole metallization column is with the upper surface of corresponding pin in the burning of the base of ceramic
Form the integrally connected sintered into during porcelain, the bottom end of the external groove metalization layer and the upper surface of corresponding pin for
The base of ceramic sinters the integrally connected sintered into during porcelain into；
The first nickel coating is provided on the side metallization, pricker on the first nickel coating on the side metallization
Weldering is connected with becket frame, and the open ceramics to constitute sealing that the metal cover board is used to cover the becket frame are outer
Shell；
The becket frame, lower buried layer metalization layer, upper buried layer metalization layer, 8 pins and 8 external groove metallization
The first nickel coating being sequentially arranged from inside to outside, the second nickel coating, Gold plated Layer are provided on whole exposed metal surfaces of layer.
Preferably, 8 pins are entirely located within the surrounding edge of outer box bottom surface of the base of ceramic.
Preferably, the becket frame is set on the side metallization by the soldering connection of silver-copper brazing alloy
On one nickel coating.
The application has advantageous effects below:
(1) stage construction multicomponent synchronous welding
The utility model has five layers by the welding surface of matrix of base of ceramic, and soldering part is more, and technological design is with dedicated
Graphite jig as positioning tool, complete stage construction multicomponent synchronous welding in dedicated atmosphere protection high temperature sintering furnace, this
Kind technique has the advantages such as high production efficiency, accurate positioning, stability of the welding quality is good, air-tightness is high, high reliability.
(2) the match materials assembling of close linear expansion coefficient
The utility model ceramic shell is by Al2O3The combination of materials of the close linear expansion coefficient such as ceramics, kovar alloy forms,
Different materials are reduced in high temperature using soft base silver-copper brazing alloy as welding material using the technique of substep assembling synchronous welding
The stress that sintering process generates, improves the reliability of such assembling product technique.
(3) base of ceramic is processed using HTCC high-temperature co-fired ceramics
HTCC high-temperature co-fired ceramics technique is by multilayer Al2O3Ceramic chips laminate, and have silk-screen printing golden on corresponding ceramic chips
Categoryization circuit is connected by via metal between different layers, and the circuit being connected to up and down is formed, then high in privacy protection atmosphere
In warm furnace, ceramic chips are sintered to ripe tile, while the cream that metallizes is sintered the metalization layer to be formed in conjunction with ceramic seal.
(4) multilayer circuit printing conducting
This product circuit is the integrated circuit for including two metal-oxide-semiconductors, and structure is more complicated, is distributed to each circuit mutual insulating
In each layer ceramics.Then circuit fabrication technique will connect each layer circuit using each layer ceramic circuit plate layering printing, solidification
Through-hole by the process filling tungsten of vacuum injection slurry metallization cream, then each layer ceramics are laminated, form multilayer circuit combination
Body.
(5) outer dimension and pad line space design of the ceramic shell provided by the present application according to former SOP8 plastic device, pottery
The arrangement pattern of 8 pins on ceramic shell is identical as the arrangement pattern of 8 pins of SOP8 plastic device, guarantees replacement in situ
SOP8 plastic device.
(6) in SOP8 shape limitation space, two gold being electrically insulated between each other are set in the inner bottom surface of a pit
Independently installed space of the categoryization layer as double metal-oxide-semiconductor chips, structure novel.
(7) requirement on electric performance different according to each pin designs the conductive pattern of different spaces and size, realizes accurate
Circuit output.
(8) high-strength high-temperature cofiring Al is used2O3Ceramic material has high value, high-intensity performance as insulating body.
(9) pin uses low resistive metal, and inner via hole metallization column and external groove metalization layer use low resistive metal, under
Buried layer metalization layer is electrically connected using inside and outside two-way via metalization with corresponding pin, and upper buried layer metalization layer uses inside and outside two
Road via metalization is electrically connected with corresponding pin, can make that the resistance of entire circuit is small, thermal resistance is small, and with ceramic material matching
It can be good.
(10) the lower buried layer metalization layer as chip region and the upper buried layer metalization layer as pressure welding area are upper layer and lower layer
Layered arrangement both ensure that insulation performance, and the space of chip region and pressure welding area has also been enlarged.
(11) manufacture craft mass designs, convenient for operation, it is easy to accomplish batch production improves production efficiency.
(12) working range of ceramic shell provided by the present application is wide, and reachable -65 DEG C~200 DEG C.
Detailed description of the invention
Fig. 1 is the overlooking structure diagram of SOP8 plastic device in the prior art；
Fig. 2 is the main view schematic diagram of Fig. 1；
Fig. 3 is the right view structural schematic diagram of Fig. 1；
Fig. 4 is a kind of pottery for encapsulating double metal-oxide-semiconductors and replacement SOP8 plastic device in situ provided by the embodiment of the utility model
The overlooking structure diagram of ceramic shell removed after metal cover board；
Fig. 5 is the present invention looks up structural representation of Fig. 4；
Fig. 6 is the A-A of the base of ceramic in Fig. 4 to schematic cross-sectional view；
Fig. 7 is that the ceramic shell in Fig. 4 covers the overlooking structure diagram after metal cover board；
Fig. 8 is the left view structural representation of Fig. 7；
Fig. 9 is the present invention looks up structural representation of Fig. 7.
In figure: 001 pin；
1 base of ceramic, 2 becket frames, 3 metal cover boards；
4 lower buried layer metalization layers, 401 lower conductive patterns one, 402 lower conductive patterns two；
Buried layer metalization layer on 5, conductive pattern one on 501, conductive pattern two on 502, conductive pattern three on 503,504
Upper conductive pattern four；
6 pins, 7 inner via holes metallization column, 8 external groove metalization layers, 9 pits, 10 side metallizations, 11 semicircles are transversal
Face groove.
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is a part of the embodiment of the utility model, instead of all the embodiments.Based on the reality in the utility model
Apply example, those of ordinary skill in the art's every other embodiment obtained without making creative work, all
Belong to the range of the utility model protection.
In the description of the present invention, it should be understood that term " center ", " axial direction ", " radial direction ", " longitudinal direction ", " cross
To ", " length ", " width ", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outside", " clockwise ",
The orientation or positional relationship of the instructions such as " counterclockwise ", "vertical", "horizontal" is to be based on the orientation or positional relationship shown in the drawings, only
It is the utility model and simplified description for ease of description, rather than the device or element of indication or suggestion meaning must have spy
Fixed orientation is constructed and operated in a specific orientation, therefore should not be understood as limiting the present invention.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features directly contact, also may include the first and second features be not direct contact but
Pass through the other characterisation contact between them.Moreover, fisrt feature includes above the second feature " above ", " above " and " above "
Fisrt feature is in the surface and oblique upper of second feature, or is merely representative of first feature horizontal height higher than second feature.
Fisrt feature includes fisrt feature in the underface of second feature and obliquely downward under the second feature " below ", " below " and " below "
Side, or first feature horizontal height is merely representative of less than second feature.
Referring to Fig.1~Fig. 9, Fig. 1 are the overlooking structure diagram of SOP8 plastic device in the prior art；Fig. 2 is Fig. 1's
Main view schematic diagram；The right view structural schematic diagram that Fig. 3 is Fig. 1 (label has 001 in Fig. 1-3)；Fig. 4 is that this is practical
The ceramic shell of a kind of double metal-oxide-semiconductors of encapsulation that new embodiment provides and replacement SOP8 plastic device in situ removes metal cover board
Overlooking structure diagram afterwards；Fig. 5 is the present invention looks up structural representation of Fig. 4；Fig. 6 is the A-A of the base of ceramic in Fig. 4 to section view knot
Structure schematic diagram；Fig. 7 is that the ceramic shell in Fig. 4 covers the overlooking structure diagram after metal cover board；Fig. 8 is the left view knot of Fig. 7
Structure schematic diagram；Fig. 9 is the present invention looks up structural representation of Fig. 7.
Embodiment 1 encapsulates the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ, including base of ceramic 1, gold
Belong to ring frame 2, metal cover board 3, the lower buried layer metalization layer 4 as conducting channel, the upper buried layer metalization layer as conducting channel
5, the inner via hole of pin 6,8 of side metallization 10,8 metallization 7,8 external groove metalization layers 8 of column；
The base of ceramic 1 is top opening-box, is provided on the inner box bottom surface of the base of ceramic 1 for placing MOS
The pit 9 of tube chip；
10,8 the lower buried layer metalization layer 4, upper buried layer metalization layer 5, side metallization inner via holes metallization columns
7,8 external groove metalization layers 8 and 8 pins 6 are to connect in pre-buried sintering during sintering porcelain into of the base of ceramic 1
It connects in the base of ceramic 1；
The lower buried layer metalization layer 4 is embedded in the lower section of the pit 9 and the hole bottom wall as the pit 9 in advance, described
Lower buried layer metalization layer 4 includes lower conductive pattern 1 and lower conductive pattern 2 402, and the lower conductive pattern 1 is under
Conductive pattern 2 402 is spaced apart from each other to be electrically insulated, and the lower conductive pattern 1 places a metal-oxide-semiconductor core with welding thereon
It piece and is electrically connected with the electrode points on the lower surface of corresponding metal-oxide-semiconductor chip, the lower conductive pattern 2 402 with welding thereon
It connects and places another metal-oxide-semiconductor chip and be electrically connected with the electrode points on the lower surface of corresponding metal-oxide-semiconductor chip；
The upper buried layer metalization layer 5 the is embedded in the base of ceramic 1 in advance and remaining interior cassette bottom in addition to the pit 9
On face, the upper buried layer metalization layer 5 include upper conductive pattern 1, upper conductive pattern 2 502, upper conductive pattern 3 503 with
And upper conductive pattern 4 504, the upper conductive pattern 1, upper conductive pattern 2 502, upper conductive pattern 3 503 and on lead
Electrograph shape 4 504 is respectively used to be electrically connected with the electrode points on the upper surface of corresponding metal-oxide-semiconductor chip, the upper conductive pattern one
501, upper conductive pattern 2 502, upper conductive pattern 3 503 and upper conductive pattern 4 504 are spaced apart from each other to be electrically insulated；
The side metallization 10 is embedded in the open box of the base of ceramic 1 along face in advance；
8 pins 6 are ceramic metallized layer, 8 pins 6 be all set on the outer box bottom surface of the base of ceramic 1 with
For making the arrangement sample of the arrangement pattern of 8 pins 6 on the base of ceramic 1 and 8 pins 6 of SOP8 plastic device
Formula is identical can to replace SOP8 plastic device in situ, and 8 pins 6 are spaced apart from each other to be electrically insulated；
8 inner via hole metallization columns 7 are embedded in respectively in 8 through-holes in the base of ceramic 1,8 inner via hole metals
Change column 7 and 8 through-hole to correspond, 8 external groove metalization layers 8 are separately positioned on the outer side surface of the base of ceramic 1
8 semi-circular cross-sections grooves 11 in, 8 external groove metalization layer 8 and 8 semi-circular cross-sections grooves 11 correspond；
The lower conductive pattern 1 is electrically connected with 2 pins 6 respectively with lower conductive pattern 2 402；
The upper conductive pattern 1, upper conductive pattern 2 502, upper conductive pattern 3 503 and upper conductive pattern four
504 are electrically connected with remaining 4 pins 6 one-to-one correspondence respectively；
2 pins 6 being electrically connected with the lower conductive pattern 1 and be electrically connected with lower conductive pattern 2 402 2
A pin 6 is located at the A side edge of the outer box bottom surface of the base of ceramic 1, with upper conductive pattern 1, upper conductive pattern two
502,4 pins 6 of residue that upper conductive pattern 3 503 and upper conductive pattern 4 504 are electrically connected are located at the base of ceramic 1
The B side edge of outer box bottom surface, the side A and the side B are two sides being parallel to each other；
Each of 2 pins 6 being electrically connected with the lower conductive pattern 1 pin 6 passes through corresponding to it
1 inner via hole metallization column 7 and 1 external groove metalization layer 8 are electrically connected with the lower surface of the lower conductive pattern 1；
Each of 2 pins 6 being electrically connected with the lower conductive pattern 2 402 pin 6 passes through corresponding to it
1 inner via hole metallization column 7 and 1 external groove metalization layer 8 are electrically connected with the lower surface of the lower conductive pattern 2 402；
1 pin 6 being electrically connected with the upper conductive pattern 1 passes through 1 inner via hole metallization column corresponding to it
7 and 1 external groove metalization layers 8 are electrically connected with the lower surface of the upper conductive pattern 1；
1 pin 6 being electrically connected with the upper conductive pattern 2 502 passes through 1 inner via hole metallization column 7 corresponding to it
And 1 external groove metalization layer 8 is electrically connected with the lower surface of the upper conductive pattern 2 502；
1 pin 6 being electrically connected with the upper conductive pattern 3 503 passes through 1 inner via hole metallization column corresponding to it
7 and 1 external groove metalization layers 8 are electrically connected with the lower surface of the upper conductive pattern 3 503；
1 pin 6 being electrically connected with the upper conductive pattern 4 504 passes through 1 inner via hole metallization column corresponding to it
7 and 1 external groove metalization layers 8 are electrically connected with the lower surface of the upper conductive pattern 4 504；
The top of inner via hole metallization column 7 under corresponding time buried layer metalization layer 4 or upper buried layer metalization layer 5
Surface be in the integrally connected of the base of ceramic 1 sintered into during sintering porcelain into, the top of external groove metalization layer 8 with
The lower surface of corresponding lower buried layer metalization layer 4 or upper buried layer metalization layer 5 is to sinter porcelain process into the base of ceramic 1
In the integrally connected that sinters into, the bottom end of the inner via hole metallization column 7 is with the upper surface of corresponding pin 6 in the ceramics
Pedestal 1 sinters the integrally connected sintered into during porcelain into, the bottom end of the external groove metalization layer 8 and corresponding pin 6
Upper surface be in the integrally connected of the base of ceramic 1 sintered into during sintering porcelain into；
The first nickel coating, the first nickel coating on the side metallization 10 are provided on the side metallization 10
Upper soldering connection is provided with becket frame 2, and the metal cover board 3 is used to cover the open to constitute sealing of the becket frame 2
Ceramic shell；
The becket frame 2, lower buried layer metalization layer 4,5,8 pins 6 of upper buried layer metalization layer and 8 external groove gold
The first nickel coating being sequentially arranged from inside to outside, the second nickel coating, gold-plated is provided on whole exposed metal surfaces of categoryization layer 8
Layer.
Embodiment 2, on the basis of the technical solution of embodiment 1,8 pins 6 are entirely located in the base of ceramic 1
Within the surrounding edge of outer box bottom surface.
Embodiment 3, on the basis of the technical solution of embodiment 1, the becket frame 2 is connected by the soldering of silver-copper brazing alloy
It connects on the first nickel coating being set on the side metallization 10.
Embodiment 4 encapsulates the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ described in above-mentioned any one
Preparation method, include the steps that next coming in order carry out:
1) base of ceramic 1 is prepared:
A) punching prepares through-hole and semi-circular cross-sections groove 11 on corresponding ceramic chips first, then in corresponding green
Screen-printed metallization cream on the upper surface of piece, added metal cream in the through hole, in semi-circular cross-sections groove 11
Paint metals cream on wall surface, the screen-printed metallization cream on the lower surface of undermost ceramic chips；
B) then multiple ceramic chips are laminated；
C) static pressure suppressions are then carried out etc. using equal pressing equipment, etc. after static pressure suppressions laminated ceramic chips be extruded and be linked to be one
Body, etc. after static pressure suppressions in the metallization cream, metallization cream and semi-circular cross-sections groove 11 in the through-hole of silk-screen printing
Metallization cream be extruded and be connected；
D) it is then placed in protective atmosphere high temperature furnace and is sintered, the ceramic chips of Multi-stacking compaction are sintered the ripe porcelain being integrated
Part, the metallization cream of silk-screen printing is sintered to lower buried layer metalization layer 4, the metallization of upper buried layer accordingly on the upper surface of ceramic chips
Layer 5 or side metallization 10, the metallization cream in through-hole are sintered to inner via hole metallization column 7, in semi-circular cross-sections groove 11
The metallization cream of brushing is sintered to external groove metalization layer 8, the metallization of silk-screen printing on the lower surface of undermost ceramic chips
Cream is sintered to pin 6；
E) then furnace cooling is come out of the stove after the completion of cooling, and base of ceramic 1 is made；
2) electronickelling: base of ceramic 1 made from step 1) is subjected to an electronickelling, at this moment base of ceramic 1
The first nickel coating is electroplated on whole exposed metal surfaces, it is for subsequent sintering brazing metal ring that the first nickel coating is electroplated herein
Frame, ceramic metallized layer cannot direct brazing metal ring frames；
3) sintering soldering: by base of ceramic 1, becket frame 2 and the silver-copper brazing alloy graphite after an electronickelling of step 2)
Mold fits together, and is then placed in the chain belt of nitrogen nitrogen atmosphere protection chain-type sintering furnace and is sintered soldering, silver-copper brazing alloy
Melting occurs at a sintering temperature to by 2 soldering connection of becket frame on the first nickel coating on side metallization 10,
Then furnace cooling is come out of the stove after the completion of cooling, and ceramic shell semi-finished product are made；
4) second time electroplating nickel and electroplating gold: by ceramic shell semi-finished product elder generation second time electroplating nickel made from step 3), then again
Electroplating gold, so that the second nickel coating and one layer of Gold plated Layer are successively plated on whole exposed metal surfaces of ceramic shell semi-finished product,
Ceramic shell finished product is made after the completion of plating.
Nitrogen nitrogen atmosphere in step 3), is protected chain-type sintering furnace on the basis of the technical solution of embodiment 4 by embodiment 5
800 DEG C -840 DEG C of welding temperature of silver-copper brazing alloy are warming up to, nitrogen hydrogen hybrid protection gas is passed through, nitrogen hydrogen hybrid protection gas
Flow is 80L/min-200L/min, and nitrogen nitrogen atmosphere protection chain-type sintering furnace is first preheated 30min-60min before sintering soldering；
Entirely sintering soldering operational process is 1.5-3 hours to step 3)；
In step 3), entire be sintered guarantees the constant of sintering temperature and nitrogen hydrogen flowing quantity in brazing process, each warm area
Temperature error is no more than ± 3 DEG C, and nitrogen and hydrogen mixture flow error is no more than ± 5L/min.
Embodiment 6, on the basis of the technical solution of embodiment 4, in step 4), the first nickel coating for being superimposed with
Overall thickness >=3 μm of second nickel coating, thickness >=1.2 μm of Gold plated Layer.
Up and down direction in the application is subject to up and down direction shown in fig. 6, in the up and down direction and Fig. 6 in Fig. 4-9
Up and down direction is consistent.Inner via hole metallization column 7 in the application is right cylinder.
" chip " in the application, refers to integrated circuit die, is also unencapsulated；And the metal-oxide-semiconductor in the application, in fact
It is exactly chip on border, he is exactly chip piece from the appearance, therefore can be referred to as metal-oxide-semiconductor chip.
In the application, base of ceramic 1 is HTCC high-temperature co-fired ceramics, can be preparatory according to circuit design needs between every layer
Tungsten slurry metallization cream is printed as metallic circuit.After the completion of sintering, layering cannot be clearly seen in multi-layer ceramics firing one, appearance
Trace.
In the application, lower buried layer metalization layer, upper buried layer metalization layer, side metallization, 8 pins and 8 are outer
The thickness of excess metal layer is very thin thickness between 0.02mm-0.05mm, therefore upper layer and lower layer ceramic chips laminate afterwards substantially
On be that can't see the ceramic metallized layer being clipped in the middle, in the cross-sectional view in the attached drawing of the application, in order to by lower buried layer metal
Change layer, upper buried layer metalization layer, side metallization, 8 pins and 8 external groove metalization layers to embody, so
That draws is so thick, in fact actually their very thin thickness, and actually there is no draw so thick in cross-sectional view.
In the application, the base of ceramic 1 is the ripe porcelain piece of one formed by 5 layers of ceramic chips co-sintering, and 5 layers of ceramic chips are folded
Be followed successively by from top to bottom after forcing together first layer ceramic chips, second layer ceramic chips, third layer ceramic chips, the 4th layer of ceramic chips,
Layer 5 ceramic chips, wherein sintering the metallization cream silk-screen printing of 8 pins 6 into the lower length and width surface of first layer ceramic chips
On, it is not coated by metallization cream on the upper length and width surface of first layer ceramic chips, sinters the metallization cream of lower buried layer metalization layer 4 into
Silk-screen printing sinters the metallization cream silk-screen printing of buried layer metalization layer 5 on the upper length and width surface of second layer ceramic chips
In on the upper length and width surface of third layer ceramic chips, it is not coated by metallization cream on the upper length and width surface of the 4th layer of ceramic chips, is sintered into
The metallization cream silk-screen printing of side metallization 10 is on the upper length and width surface of layer 5 ceramic chips.Above-mentioned 5 layers of ceramic chips are simultaneously
It is not all solid thin slice, above according to the hole having, slot, the hole etc. is designed, has all been set, then corresponding
Screen-printed metallization cream on the upper surface of ceramic chips, added metal cream in the through hole, in semi-circular cross-sections groove 11
Inner wall on paint metals cream, the screen-printed metallization cream on the lower surface of undermost ceramic chips.5 in the application
Layer ceramic chips are Al2O3Ceramic chips.
In the application, metalization layer distribution map: conductive pattern may also be referred to as printed circuit, and the thickness of printed circuit is general
It is that, according to the needs of circuitous resistance, can be completed between 0.02mm-0.05mm with one-step print, 2-3 printing can also be divided to increase
Add circuit thickness, increase cross-sectional area, reduces resistance.The welding section of printed circuit being exposed, sometimes according to packaging technology
It needs, one layer of thin metal layer can be welded.If it is desired to realizing higher resistance or current capability requirement, every circuit point can be taken
It is connected to for multilayer, every circuit is connected to according to single layer and draws in the attached drawing of the application, and multilayer circuit design is also protected in this patent
It protects in range.
It in the application, is connected between each layer circuit by via metal, until leading to corresponding pin 6.Except external groove gold
Outside categoryization layer 8, every circuit in the attached drawing of the application, which is connected to according to single hole, to be drawn, and can also use porous connection, porous
Connection design is also in the scope of this patent.
In the application, the conductive pattern in every layer of metallization is designed according to circuit layout, and length and width dimensions are according to electricity
Road resistance parameter requires to calculate design.
In the application, external groove metalization layer 8: respectively there are semi-circular cross-sections groove at one, cell wall gold in the side of each pin 6
Categoryization, there are two effects: first is that increasing internal circuit with the circuit cross-sectional area of pin 6 to reduce resistance, second is that being the ceramics
Shell, which is installed in circuit board, reserves solder bath, further decreases electrode resistance, improves the weld strength of device.
In the application, the distribution of pin 6 is according to plastic packaging SOP8 pad design, and No. 1 pin 6 reserves oblique angle label.Pin 6
Can be tungsten slurry metalization layer, one layer of metal layer can also be welded again on it, finally will nickel plating with it is gold-plated.
In step 1), base of ceramic 1 laminates technique using multilayer circuit: in order to guarantee 1 each layer of ceramic chips of base of ceramic
It closely can uniformly be combined with circuit, after ceramic chips superposition, using the equal pressing equipment pressure equal to the comprehensive application of tile
Power such as carries out at the static pressure suppressions, and by the base of ceramic 1 that isostatic pressing process produces, dense materials and mechanical strength can be mentioned
It rises.
In step 3), first has to for metal parts and base of ceramic 1 being assembled in graphite jig, welding all parts
It is in positioning states always in the process.By adjusting sintering furnace furnace temperature, chain tape speed, nitrogen and hydrogen flowing quantity, silver-bearing copper under high temperature
Solder fusing, realizes the welding of metal and ceramic metallization face, and soldering reliability is high.
The application uses the welding procedure in ceramic metallization face and metal material and the match materials of close linear expansion coefficient
Packaging technology has the advantages such as resistance to a wide range of temperature shock, connection is reliable, thermal resistance is small.It realizes this manufacturing process, needs to integrate
Consider the composition matchings of different materials, silver-copper brazing alloy welding performance, the ceramic surface metallization on different materials surface etc. because
Element meets thermal resistance, mechanical strength, electric current transmission etc. and requires.Therefore, it realizes the secure makeup of product, to consider the ginseng of the product
Number feature and architectural characteristic, the key technology finally solved have: the synchronous welding skill in ceramic metallization face and different materials metal
Art, the matching package technique of multiple material, silver-copper brazing alloy different materials surface wetting distribution technique.
The theoretical foundation of the application:
(1) different materials surface is different from the welding performance of silver-copper brazing alloy, i.e., wettability is variant.Ceramic material itself
There is no wettability with brazing metal, cannot be directly used to weld, needing to do metalization layer in ceramic surface could be used to weld.
(2) welding temperature of silver-copper brazing alloy participates in the metal and ceramic surface of welding generally at 800 DEG C~840 DEG C, will
Guarantee that welding performance is good in this temperature range.
(3) 92%Al2O3The linear expansion coefficient of ceramics is 6.8 × 10-6/ DEG C or so, the line of 4J29 kovar alloy expands system
Number is 5.7-6.2 × 10-6/ DEG C, these types of linear expansion coefficient is close, can be used for matching welding.
(4) base of ceramic 1 is HTCC high-temperature co-fired ceramics, and bending strength is up to 400MPa, bulk resistor >=1 × 1012Ω
(500VDC survey), meets requirement of the highly reliable device for Enclosure Strength and insulation performance.HTCC high-temperature co-fired ceramics: pottery
Porcelain and metallization are that step sintering is completed, and sintering temperature is at 1500 DEG C -1550 DEG C, during this, are made pottery by the multilayer laminated
Porcelain green blank changes into hard ripe porcelain by soft tire, and is mutually fused to form fine and close sealing layer with metallization material interface, this
Process is exactly high temperature co-firing technique.
The selection of material in the application: base of ceramic 1 uses 92%Al2O3High-temperature co-fired ceramics, becket frame 2 use
4J29 kovar alloy, above-mentioned metallization cream be all made of tungsten system metallization cream, main material is tungsten powder, by addition aluminium oxide,
The glass-ceramics phase material such as silica improves the bond strength of metallization.According to metallization position, the metallization cream subdivision of tungsten system
It is divided into welding section slurry (sealing frame and 6 position of pin), internal printing slurry (lower buried layer metalization layer 4, upper buried layer metalization layer
5 and side metallization) and orifice slurry (inner via hole metallize column 7 and external groove metalization layer 8).Different tungsten system gold
Difference, purpose both ensure that the metallization quality of route to the component and viscosity of categoryization cream.
The method and apparatus of the not detailed description of the utility model are the prior art, are repeated no more.
Specific embodiment used herein is expounded the principles of the present invention and embodiment, the above implementation
The explanation of example is merely used to help understand the method and its core concept of the utility model.It should be pointed out that for the art
Those of ordinary skill for, without departing from the principle of this utility model, can also to the utility model carry out it is several
Improvement and modification, modifications and modifications also fall within the protection scope of the claims of the utility model.
Claims (3)
1. encapsulating the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ, which is characterized in that including base of ceramic, gold
Belong to ring frame, metal cover board, the lower buried layer metalization layer as conducting channel, the upper buried layer metalization layer as conducting channel, table
Face metalization layer, 8 pins, 8 inner via holes metallization columns, 8 external groove metalization layers；
The base of ceramic is top opening-box, is provided on the inner box bottom surface of the base of ceramic for placing metal-oxide-semiconductor chip
Pit；
The lower buried layer metalization layer, upper buried layer metalization layer, side metallization, 8 inner via holes metallization columns, 8 it is outer recessed
Slot metalization layer and 8 pins are to be connected to the ceramics in pre-buried sintering during sintering porcelain into of the base of ceramic
In pedestal；
The lower buried layer metalization layer is embedded in the lower section of the pit and the hole bottom wall as the pit, the lower buried layer gold in advance
Categoryization layer includes lower conductive pattern one and lower conductive pattern two, the lower conductive pattern one and lower conductive pattern two be spaced apart from each other with
Electrical isolation, the lower conductive pattern one with welding thereon place a metal-oxide-semiconductor chip and with the following table of corresponding metal-oxide-semiconductor chip
Electrode points electrical connection on face, the lower conductive pattern two with welding thereon place another metal-oxide-semiconductor chip and with it is corresponding
Electrode points electrical connection on the lower surface of metal-oxide-semiconductor chip；
The upper buried layer metalization layer be embedded in advance the base of ceramic and in addition to the pit on remaining inner box bottom surface, institute
Stating buried layer metalization layer includes upper conductive pattern one, upper conductive pattern two, upper conductive pattern three and upper conductive pattern four, institute
Conductive pattern one, upper conductive pattern two, upper conductive pattern three and upper conductive pattern four is stated to be respectively used to and corresponding metal-oxide-semiconductor
On the upper surface of chip electrode points electrical connection, the upper conductive pattern one, upper conductive pattern two, upper conductive pattern three and on
Conductive pattern four is spaced apart from each other to be electrically insulated；
The side metallization is embedded in the open box of the base of ceramic along face in advance；
8 pins are ceramic metallized layer, 8 pins be all set on the outer box bottom surface of the base of ceramic to be used for so that
The arrangement pattern of 8 pins on the base of ceramic is identical as the arrangement pattern of 8 pins of SOP8 plastic device can be former
Position replacement SOP8 plastic device, 8 pins are spaced apart from each other to be electrically insulated；
8 inner via hole metallization columns are embedded in respectively in 8 through-holes in the base of ceramic, 8 inner via holes metallization columns and 8
A through-hole corresponds, and 8 external groove metalization layers are separately positioned on 8 semicircle cross on the outer side surface of the base of ceramic
In section grooves, 8 external groove metalization layers are corresponded with 8 semi-circular cross-sections grooves；
The lower conductive pattern one is electrically connected with 2 pins respectively with lower conductive pattern two；
The upper conductive pattern one, upper conductive pattern two, upper conductive pattern three and upper conductive pattern four respectively with remaining 4
Pin corresponds electrical connection；
2 pins being electrically connected with the lower conductive pattern one and 2 pins being electrically connected with lower conductive pattern two are located at institute
The A side edge for stating the outer box bottom surface of base of ceramic, with upper conductive pattern one, upper conductive pattern two, upper conductive pattern three and on
4 pins of residue that conductive pattern four is electrically connected are located at the B side edge of the outer box bottom surface of the base of ceramic, the side A and the side B
While being two sides being parallel to each other；
Each of 2 pins being electrically connected with the lower conductive pattern one pin passes through 1 inner via hole corresponding to it
Metallization column and 1 external groove metalization layer are electrically connected with the lower surface of the lower conductive pattern one；
Each of 2 pins being electrically connected with the lower conductive pattern two pin passes through 1 inner via hole corresponding to it
Metallization column and 1 external groove metalization layer are electrically connected with the lower surface of the lower conductive pattern two；
1 pin being electrically connected with the upper conductive pattern one passes through 1 inner via hole corresponding to it and metallizes outside column and 1
Excess metal layer is electrically connected with the lower surface of the upper conductive pattern one；
1 pin being electrically connected with the upper conductive pattern two passes through 1 inner via hole corresponding to it and metallizes outside column and 1
Excess metal layer is electrically connected with the lower surface of the upper conductive pattern two；
1 pin being electrically connected with the upper conductive pattern three passes through 1 inner via hole corresponding to it and metallizes outside column and 1
Excess metal layer is electrically connected with the lower surface of the upper conductive pattern three；
1 pin being electrically connected with the upper conductive pattern four passes through 1 inner via hole corresponding to it and metallizes outside column and 1
Excess metal layer is electrically connected with the lower surface of the upper conductive pattern four；
The top of the inner via hole metallization column is with the lower surface of corresponding lower buried layer metalization layer or upper buried layer metalization layer
In the integrally connected of the base of ceramic sintered into during sintering porcelain into, the top of external groove metalization layer with it is corresponding under
The lower surface of buried layer metalization layer or upper buried layer metalization layer is sintering into during sintering porcelain into the base of ceramic
Integrally connected, the bottom end of the inner via hole metallization column are sintering into the base of ceramic with the upper surface of corresponding pin
The integrally connected sintered into during porcelain, the bottom end of the external groove metalization layer are described with the upper surface of corresponding pin
Base of ceramic sinters the integrally connected sintered into during porcelain into；
The first nickel coating is provided on the side metallization, the company of soldering on the first nickel coating on the side metallization
It connects and is provided with becket frame, the metal cover board is used to cover the open ceramic shell to constitute sealing of the becket frame；
The becket frame, lower buried layer metalization layer, upper buried layer metalization layer, 8 pins and 8 external groove metalization layers
The first nickel coating being sequentially arranged from inside to outside, the second nickel coating, Gold plated Layer are provided on whole exposed metal surfaces.
2. ceramic shell according to claim 1, which is characterized in that 8 pins are entirely located in the outer of the base of ceramic
Within the surrounding edge in cassette bottom face.
3. ceramic shell according to claim 1, which is characterized in that the becket frame is connected by the soldering of silver-copper brazing alloy
It connects on the first nickel coating being set on the side metallization.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920911775.2U CN209729885U (en) | 2019-06-17 | 2019-06-17 | Encapsulate the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ |
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|---|---|---|---|
| CN201920911775.2U CN209729885U (en) | 2019-06-17 | 2019-06-17 | Encapsulate the ceramic shell of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112105A (en) * | 2019-06-17 | 2019-08-09 | 济南市半导体元件实验所 | For encapsulating the ceramic shell and preparation method thereof of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ |
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2019
- 2019-06-17 CN CN201920911775.2U patent/CN209729885U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112105A (en) * | 2019-06-17 | 2019-08-09 | 济南市半导体元件实验所 | For encapsulating the ceramic shell and preparation method thereof of double metal-oxide-semiconductors and replacement SOP8 plastic device in situ |
| CN110112105B (en) * | 2019-06-17 | 2023-12-29 | 济南市半导体元件实验所 | Ceramic shell for packaging double MOS (metal oxide semiconductor) tubes and in-situ replacing SOP8 plastic packaging device and preparation method thereof |
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Effective date of registration: 20240123 Address after: No. 13856 Jingshi West Road, Ping'an Street, Changqing District, Jinan City, Shandong Province, 250101 Patentee after: JINAN JINGHENG ELECTRONICS Co.,Ltd. Country or region after: China Address before: 250014 No. 51 Heping Road, Lixia District, Shandong, Ji'nan Patentee before: JINAN SEMICONDUCTOR Research Institute Country or region before: China |