CN209590536U - Exposure stage and semiconductor exposure device - Google Patents
Exposure stage and semiconductor exposure device Download PDFInfo
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- CN209590536U CN209590536U CN201920373403.9U CN201920373403U CN209590536U CN 209590536 U CN209590536 U CN 209590536U CN 201920373403 U CN201920373403 U CN 201920373403U CN 209590536 U CN209590536 U CN 209590536U
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- cavity
- exposure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 90
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 7
- 230000008569 process Effects 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 9
- 239000008187 granular material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000013618 particulate matter Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
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- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The utility model relates to a kind of exposure stages, it include: stage body, the stage body includes the first open cavity, first cavity includes the first side surface and the first bottom surface for connecting with first side surface, angle between first side surface and first bottom surface is obtuse angle, first bottom surface is parallel to horizontal plane, for placing semiconductor base to be exposed.The utility model in stage body by processing inclined first cavity in the first side surface, keep first cavity wide at the top and narrow at the bottom, therefore the semiconductor base of offset can be slipped to automatically on the first bottom surface of first cavity bottom, realize being automatically aligned to for the semiconductor base, and the semiconductor base is made to be not easy to skid off first cavity after the completion of placement, so that the semiconductor base is more firm, the process can significantly improve alignment precision, to increase the alignment rate of the semiconductor base position.
Description
Technical field
The utility model relates to field of semiconductor devices more particularly to a kind of exposure stage and semiconductor exposure devices.
Background technique
In semiconductor lithography processing procedure, exposure accuracy requirement is general other in the micron-scale, even higher, so to exposure stage
Levelness and the semiconductor base status requirement it is high.
In prior art, semiconductor base (such as Silicon Wafer) is typically all to be transmitted by mechanical arm and be placed directly in exposure
It is exposed after on optical platform, mechanical arm has transmission error at present, so the semiconductor base is placed in exposure every time
There is certain deviation when platform, but the prior art does not control the position of the semiconductor base effectively, and
Deviation is bigger, and the time that the semiconductor base needs to search when exposure stage does exposure prealignment contraposition mark is longer.
Even when deviation is excessive, prealignment is identified not in search area, and board will alarm.
Fig. 1 is the schematic diagram that technique is exposed using existing exposure stage.As shown in Figure 1, semiconductor base is placed
It is exposed in existing exposure stage 01, if the place that the semiconductor-based bottom back side is not cleaned, which is sticked, some particles
Object, the particulate matter on these particulate matters and existing stage body 02 may result in the semiconductor substrate surface in exposure process
Figure is not on same focussing plane, the phenomenon that causing poor focusing.And the direct result of poor focusing seeks to the portion of exposure
Component shape is not opened, this will seriously affect the yield of product.
Utility model content
The purpose of this utility model is to provide a kind of exposure stage and semiconductor exposure devices, by adjusting exposure stage
Structure, it is possible to reduce the deviation of exposure stage semiconductor-on-insulator substrate and the contact surface of the semiconductor base and exposure stage
Product, to increase the alignment rate and levelness of the semiconductor base position.
In order to achieve the above object, the utility model provides a kind of exposure stage, comprising:
Stage body, the stage body include the first open cavity, and first cavity includes the first side surface and with described the
First bottom surface of one side surface connection, the angle between first side surface and first bottom surface is obtuse angle, described
First bottom surface is parallel to horizontal plane, for placing semiconductor base to be exposed.
Optionally, in the exposure stage, the stage body further includes penetrating through with first cavity and being located at described the
The second cavity below one cavity, the shape of first bottom surface are annular, are centered around above second cavity.
Optionally, in the exposure stage, the semiconductor base is a circular-base, the shape of first bottom surface
Shape is an annulus, and the outer diameter of the annulus is greater than or equal to the diameter of the circular-base, and the internal diameter of the annulus is less than described
The diameter of circular-base.
Optionally, in the exposure stage, the semiconductor base is Silicon Wafer, and the silicon wafer diameter of a circle is
300mm, the circular diameter that the top edge of first side surface is surrounded are 305mm~315mm.
Optionally, in the exposure stage, the semiconductor base is a square base, the shape of first bottom surface
Shape is a Fang Huan, and the maximal side of the outboard square-like of the Fang Huan is greater than or equal to the maximal side of the square base, described
The rectangular maximal side in the inside of Fang Huan is less than the maximal side of the square base.
Optionally, in the exposure stage, direction of the back side of the semiconductor base from edge to center has one
Edge clean area, the Ring Width of first bottom surface are less than or equal to the width in the edge clean area.
Optionally, in the exposure stage, the Ring Width of first bottom surface is 20mm~40mm.
Optionally, in the exposure stage, first cavity and second cavity all have one perpendicular to described
The axis of symmetry of the axis of symmetry of first bottom surface, first cavity and second cavity is overlapped.
Optionally, in the exposure stage, the exposure stage further includes a platen cover, and the platen cover is located at parallel
In in the plane of first bottom surface, the cross section of the platen cover is greater than the maximum cross section of first cavity.
The utility model additionally provides a kind of semiconductor exposure device, including above-mentioned exposure stage.
It is empty by processing the first side surface inclined first in stage body in exposure stage provided by the utility model
Chamber keeps first cavity wide at the top and narrow at the bottom, therefore the semiconductor base deviated can be slipped to the of first cavity bottom automatically
On one bottom surface, being automatically aligned to for the semiconductor base is realized, and the semiconductor base is not easy after the completion of placement
First cavity is skidded off, so that the semiconductor base is more firm, which can significantly improve alignment
Precision, to increase the alignment rate of the semiconductor base position.
Detailed description of the invention
Fig. 1 is the schematic diagram that technique is exposed using existing exposure stage.
Fig. 2 is exposure stage side view provided by the embodiment of the utility model.
Fig. 3 is that exposure stage substrate provided by the embodiment of the utility model places side view.
Fig. 4 is exposure side view provided by the embodiment of the utility model.
Description of symbols:
The existing exposure stage of 01-；The existing stage body of 02-；10- exposure stage；11- stage body；The first cavity of 12-；13- second is empty
Chamber；14- platen cover；The first side surface 15-；The first bottom surface of 16-；20- semiconductor base.
Specific embodiment
Below in conjunction with schematic diagram to the exposure stage of the utility model and the specific embodiment of semiconductor exposure device
It is described in more detail.According to following description, exposure stage and the advantages of semiconductor exposure device and spy in the utility model
Sign will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to side
Just, the purpose of the utility model embodiment is lucidly aided in illustrating.
Hereinafter, term " first " " second " etc. is used between similar element distinguish, and is not necessarily for retouching
State certain order or time sequencing.It is appreciated that in the appropriate case, these terms so used are replaceable.
Substrate is essentially all to be placed in exposure stage by mechanical arm at present, can all be existed when placement certain inclined
Difference, and at present for the position of substrate and levelness there is no effectively being controlled, if but its position when having certain deviation, meeting
The time for extending contraposition mark identification or basic search is caused to identify less than the contraposition；If levelness deviates, exposing
The phenomenon that figure of substrate surface be may result in the process not on same focussing plane, cause poor focusing, and focus not
The partial graphical that good direct result seeks to exposure is not opened, this will seriously affect the yield of product.
In order to effectively control the above problem, Fig. 2 is exposure stage side view provided by the embodiment of the utility model, is such as schemed
Shown in 2, the utility model provides a kind of exposure stage 10, comprising:
Stage body 11, the stage body 11 include the first open cavity 12, and first cavity 12 includes the first side surface 15
With the first bottom surface 16 being connect with first side surface 15, between first side surface 15 and first bottom surface 16
Angle be obtuse angle, first bottom surface 16 is parallel to horizontal plane, for placing semiconductor base 20 to be exposed.Usually
, the truncated cone-shaped or prismatic table shape for being preferably shaped to stand upside down of first cavity 12 are that is, wide at the top and narrow at the bottom；If being exposed object is it
First cavity 12 then can be shaped to other arbitrary shapes by its shape.And first bottom surface 16 is not yet
It is limited to round and rectangular, can also be that the polygons such as hexagon, first bottom surface 16 can carry the semiconductor base 20
.
Further, to make the semiconductor base 20 slide into first bottom surface 16 of 12 bottom of the first cavity
Uniform force when upper preferably makes 12 symmetric figure of the first cavity, so that the semiconductor base 20 slides into described first
Uniform force when 12 bottom of cavity and even acceleration decline, and are not easy because unbalance stress causes the semiconductor base 20 impaired.
By processing inclined first cavity 12 in the first side surface 15 in stage body 11 in the utility model, make described first
Cavity 12 is wide at the top and narrow at the bottom, therefore the semiconductor base 20 deviated can be slipped to the first bottom surface of 12 bottom of the first cavity automatically
On 16, being automatically aligned to for the semiconductor base 20 is realized, and the semiconductor base 20 is made to be not easy to slide after the completion of placement
First cavity 12 out, so that the semiconductor base 20 is more firm, which can significantly be improved pair
Quasi- precision, to increase the alignment rate of 20 position of semiconductor base.
Further, the stage body 11 further includes that 12 lower section of the first cavity is penetrated through and be located at first cavity 12
The second cavity 13, the shape of first bottom surface 16 is annular, is centered around 13 top of the second cavity.Described second is empty
Chamber 13 is used to reduce the contact area of the semiconductor base 20 and the exposure stage 10, so as to reduce granule foreign pair
The influence of 20 levelness of semiconductor base, with the figure on effective less 20 surface of semiconductor base not same poly-
The phenomenon that causing poor focusing on focal plane, to improve the yield of product.
The inner space of second cavity 13 can be any shape, such as can be cylinder, truncated cone-shaped, pros
Body, cuboid or other shapes can be circle for the shape of wide at the top and narrow at the bottom or upper and lower equivalent width, preferably described second cavity 13
Cylindricality or truncated cone-shaped wide at the top and narrow at the bottom, convenient for cleaning.
As shown in Fig. 2, first cavity 12 and second cavity 13 can be depressed in the upper surface of the stage body 11
Setting, then the top of first cavity 12 is equal with the upper level of the stage body 11；First cavity 12 and described
Second cavity 13 can also protrude from the upper surface setting (not shown) of the stage body 11, then the upper surface of the stage body 11
Height lower than first cavity 12 top height, it is preferred that the height of 13 bottom of the second cavity is higher than or waits
Height in the upper surface of the stage body 11 so can according to need mobile first cavity 12 and second cavity
13, so as to adjust exposure position of the semiconductor base 20 in the exposure stage 10, and need not be in the stage body
Recess is formed on 11, it is not necessary to change the shape and structure of the stage body 11.
In one embodiment, the semiconductor base 20 is a circular-base, then the shape of first bottom surface 16
It can be circular ring shape, and the outer diameter of the annulus is greater than or equal to the diameter of the circular-base, the internal diameter of the annulus is less than
The diameter of the circular-base.The semiconductor base 20 can be Silicon Wafer, and the silicon wafer diameter of a circle can be 300mm,
The circular diameter that then top edge of preferably first side surface 15 is surrounded can be 305mm~315mm, first side
The circular diameter that the lower edge on surface 15 is surrounded can be 300mm ± 0.5mm, then it can be seen that first cavity 12
Shape is truncated cone-shaped wide at the top and narrow at the bottom.
In another embodiment, the semiconductor base 20 can be a square base, then first bottom surface 16
Shape be a Fang Huan, the maximal side of the outboard square-like of the Fang Huan is greater than or equal to the maximal side of the square base,
The rectangular maximal side in the inside of the Fang Huan is less than the maximal side of the square base.
In the present invention, Fig. 3 is that exposure stage substrate provided by the embodiment of the utility model places side view, is such as schemed
Shown in 3, direction of the back side of the semiconductor base 20 from edge to center has an edge cleaning area, first bottom surface
16 Ring Width is less than or equal to the width in the edge clean area.Common, the semiconductor base 20 is before exposure
It will do it cleaning, can generally be used at the back side of the semiconductor base 20 from edge to the region of center about 30mm~40mm
The cleaning solutions such as OK73 do back cleaning and the preparation without particulate matter, to make the edge at the back side of the semiconductor base 20 about
The region of 30mm~40mm is cleaned very much, and the region of the edge about 30mm~40mm at the back side of the semiconductor base 20 is edge
Clear area, the edge clean area are ring-type.
Further, the Ring Width of first bottom surface 16 is about 20mm~40mm.First bottom surface 16 is used
It is contacted in the edge clean area of the semiconductor base 20, and the width of first bottom surface 16 is less than or equal to the side
The width of edge clear area, so that the contact area of the semiconductor base 20 and the exposure stage 10 is substantially reduced, and
The granule foreign and/or the granule foreign in exposure stage 10 for being effectively reduced 20 back of semiconductor base continue to retain
Between the semiconductor base 20 and the exposure stage 10, so that it is flat so that the semiconductor base 20 is placed in the exposure
More smooth when in platform 10, the figure for reducing 20 surface of semiconductor base does not cause to focus on same focussing plane
Bad phenomenon, to improve the yield of product.
In the present embodiment, first cavity 12 and second cavity 13 all have one perpendicular to first bottom table
The axis of symmetry of the axis of symmetry in face 16, first cavity 12 and second cavity 13 is overlapped, for making the semiconductor
The edge clean area of substrate 20 is more overlapped with first bottom surface 16.
Further, the exposure stage 10 further includes a platen cover 14, and the platen cover 14 is located parallel to described
In the plane of one bottom surface 16, the cross section of the platen cover 14 is greater than the maximum cross section of first cavity 12.It is described flat
Platform lid 14 is used to cover first cavity 12 and second cavity 13 when the exposure stage 10 is idle, and it is dirty to reduce particle
Contaminate the cavity bottom that object enters first cavity 12 and second cavity 13.Preferably, 14 cross section of platen cover
Shape can be circle, for saving material；Certainly, the cross section of the platen cover 14 may be other any shapes.
Specifically, Fig. 4 is exposure side view provided by the embodiment of the utility model, as shown in figure 4, by described semiconductor-based
Bottom 20 is placed in first cavity 12, and for the semiconductor base 20 under the action of the first cavity 12, position is very
Accurately, and the semiconductor base 20 will not be made to be in inclined state because of granule foreign etc., light beam is vertical parallel at this time
It beats on the semiconductor base 20, makes the figure on 20 surface of semiconductor base all on same focussing plane, very great Cheng
The yield for improving product of degree.
The utility model embodiment additionally provides a kind of semiconductor exposure device, and the semiconductor exposure device includes above-mentioned
Exposure stage 10.Specifically include: stage body 11, the stage body 11 include the first open cavity 12, and first cavity 12 wraps
The first bottom surface 16 for including the first side surface 15 and being connect with first side surface 15, first side surface 15 and described
Angle between one bottom surface 16 is obtuse angle, and first bottom surface 16 is parallel to horizontal plane, described semiconductor-based for placing
Bottom 20 is to be exposed.By processing a kind of the first cavity 12 of sidewall slope in stage body 11, the semiconductor base is realized
20 are automatically aligned to；Also by reducing 20 He of semiconductor base in 12 second cavity of following settings 13 of the first cavity
The contact area of the exposure stage 10 increases by 20 levelness of semiconductor base, to improve the yield of product.
To sum up, in exposure stage provided by the utility model, by processing the first side surface inclined in stage body
One cavity keeps first cavity wide at the top and narrow at the bottom, therefore the semiconductor base deviated can be slipped to first cavity bottom automatically
The first bottom surface on, realize being automatically aligned to for the semiconductor base, and make the semiconductor base after the completion of placement
It is not easy to skid off first cavity, so that the semiconductor base is more firm, which can significantly be improved
Alignment precision, to increase the alignment rate of the semiconductor base position.And the utility model is also below first cavity
It is provided with the second cavity, for reducing the contact area at semiconductor bottom and the exposure stage described in base, so as to reduce
Influence of the grain impurity to the semiconductor base levelness, with the figure of the effective less semiconductor substrate surface not same
The phenomenon that causing poor focusing on one focussing plane, to improve the yield of product.
Illustrate the principle and effect of the utility model to being given for example only property of above-described embodiment, not for limiting this reality
With novel.Any person of ordinary skill in the field can be to this reality under the spirit and scope without prejudice to the utility model
Any type of equivalent replacement or modification etc. are made with the technical solution of novel exposure and technology contents to change, and are still fallen within practical
Within novel protection scope.
Claims (10)
1. a kind of exposure stage characterized by comprising
Stage body, the stage body include the first open cavity, first cavity include the first side surface and with first side
First bottom surface of surface connection, the angle between first side surface and first bottom surface is obtuse angle, described first
Bottom surface is parallel to horizontal plane, for placing semiconductor base to be exposed.
2. exposure stage as described in claim 1, which is characterized in that the stage body further include with first cavity perforation and
The shape of the second cavity below first cavity, first bottom surface is annular, is centered around second cavity
Top.
3. exposure stage as claimed in claim 2, which is characterized in that the semiconductor base is a circular-base, described the
The shape of one bottom surface is an annulus, and the outer diameter of the annulus is greater than or equal to the diameter of the circular-base, the annulus
Internal diameter is less than the diameter of the circular-base.
4. exposure stage as claimed in claim 3, which is characterized in that the semiconductor base is Silicon Wafer, the Silicon Wafer
Diameter be 300mm, the circular diameter that the top edge of first side surface is surrounded be 305mm~315mm.
5. exposure stage as claimed in claim 2, which is characterized in that the semiconductor base is a square base, described the
The shape of one bottom surface is a Fang Huan, and the maximal side of the outboard square-like of the Fang Huan is greater than or equal to the square base most
Big side length, the rectangular maximal side in the inside of the Fang Huan are less than the maximal side of the square base.
6. such as the described in any item exposure stages of claim 2 to 5, which is characterized in that the back side of the semiconductor base is from side
Edge has an edge cleaning area to the direction at center, and the Ring Width of first bottom surface is less than or equal to the edge clean
The width in area.
7. exposure stage as claimed in claim 6, which is characterized in that the Ring Width of first bottom surface be 20mm~
40mm。
8. exposure stage as claimed in claim 2, which is characterized in that first cavity and second cavity all have one
Perpendicular to the axis of symmetry of first bottom surface, the axis of symmetry of first cavity and second cavity is overlapped.
9. exposure stage as described in claim 1, which is characterized in that the exposure stage further includes a platen cover, described flat
Platform lid is located parallel in the plane of first bottom surface, and the cross section of the platen cover is greater than the maximum of first cavity
Cross section.
10. a kind of semiconductor exposure device, which is characterized in that including such as described in any item exposure stages of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920373403.9U CN209590536U (en) | 2019-03-22 | 2019-03-22 | Exposure stage and semiconductor exposure device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920373403.9U CN209590536U (en) | 2019-03-22 | 2019-03-22 | Exposure stage and semiconductor exposure device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209590536U true CN209590536U (en) | 2019-11-05 |
Family
ID=68374915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920373403.9U Expired - Fee Related CN209590536U (en) | 2019-03-22 | 2019-03-22 | Exposure stage and semiconductor exposure device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209590536U (en) |
-
2019
- 2019-03-22 CN CN201920373403.9U patent/CN209590536U/en not_active Expired - Fee Related
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191105 |
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| CF01 | Termination of patent right due to non-payment of annual fee |