CN209571414U - Interconnection structure - Google Patents

Interconnection structure Download PDF

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Publication number
CN209571414U
CN209571414U CN201920511807.XU CN201920511807U CN209571414U CN 209571414 U CN209571414 U CN 209571414U CN 201920511807 U CN201920511807 U CN 201920511807U CN 209571414 U CN209571414 U CN 209571414U
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China
Prior art keywords
layer
seed layer
metal material
metal
interconnection structure
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Expired - Fee Related
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CN201920511807.XU
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Chinese (zh)
Inventor
孙明亮
吴孝哲
林宗贤
吴龙江
熊建锋
吴明
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Huaian Imaging Device Manufacturer Corp
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Huaian Imaging Device Manufacturer Corp
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Abstract

The utility model relates to technical field of semiconductor device, provide a kind of interconnection mechanism of semiconductor devices.Wherein, the interconnection structure of semiconductor devices includes: dielectric layer;Metal interconnecting layer is set in dielectric layer, and metal interconnecting layer is made by the first metal material;Seed layer is set between dielectric layer and metal interconnecting layer, and seed layer has the first seed layer and second of sublayer, and the first seed layer is made by the first metal material, and second of sublayer is made by the second metal material that metal active is better than the first metal material.In the present invention; the seed layer of interconnection structure includes the first seed layer and second of sublayer; wherein the metal active of second of sublayer is better than the metal active of the first seed layer; to when carrying out electroless plating; by sacrificing second of sublayer; and form passivation layer in the first seed layer and protect the first seed layer, alleviate the first seed layer and is plated the phenomenon that liquid corrodes.

Description

Interconnection structure
Technical field
The utility model relates to technical field of semiconductor device, in particular to a kind of interconnection structure of semiconductor devices.
Background technique
With the development of semiconductor integrated circuit manufacturing technology, copper wiring technique has become post-channel interconnection work in chip manufacturing The preparation of the mainstream technology of skill, copper conductor (metal interconnecting layer) uses chemical plating process substantially.
Before carrying out chemical plating process, it usually needs in the area deposition seed layer of copper conductor to be grown, later will Silicon wafer with seed layer, which is immersed as cathode in acid copper-bath, carries out electroless plating, due to carrying out electroless plating Plating solution acidic, therefore, when wafer is just immersed in electroplate liquid, copper seed layer will certainly be led by acid electroplating corrosion Copper seed layer surface is caused to form copper seed layer deficient phenomena, so that copper can not give birth at deletion sites during subsequent electro-coppering It is long, copper conductor cavity blemish is caused, the reliability of semiconductor devices is seriously affected.
Utility model content
In view of the above problem of the prior art, the utility model provides a kind of interconnection structure of semiconductor devices, this is mutually Linking structure can prevent seed layer rotten in an acidic solution while keeping seed layer to cause the effect of wire metals growth Erosion.
The utility model provides a kind of interconnection structure of semiconductor devices, comprising: dielectric layer;Metal interconnecting layer, setting In in the dielectric layer, the metal interconnecting layer is made by the first metal material;Seed layer is set to the dielectric layer and described Between metal interconnecting layer, the seed layer has the first seed layer and second of sublayer, and first seed layer is by described first Metal material is made, and second of sublayer is made by the second metal material that metal active is better than first metal material.
Compared with prior art, in the utility model offer, the seed layer of interconnection structure includes the first seed layer and the Two seed layers, wherein the metal active of second of sublayer is better than the metal active of the first seed layer, it is living when carrying out electroless plating Property stronger second of sublayer can preferentially participate in reacting, inhibit reacting between the first seed layer and electroplate liquid.The device junction Structure can alleviate the phenomenon that the first seed layer is plated corrosion, reduce the cavity blemish formed in metal interconnecting layer, it is ensured that gold The quality for belonging to interconnection layer, improves the reliability of semiconductor devices.
Preferably, the surface of the seed layer is also formed with passivation layer.
By forming passivation layer on the surface of seed layer, electroplate liquid and seed layer can be deadened, prevents it from directly contacting, is risen The effect of protection seed layer is arrived.
Further, preferably, the passivation layer is made by the oxide of second metal material.
The passivation layer as made from the oxide of the second metal material can be directly anti-by second of sublayer and acidic Bath It should obtain, easily facilitate preparation.
In addition, preferably, first metal material is copper.
Further, preferably, second metal material be hafnium, aluminium, titanium, zirconium, vanadium, manganese, niobium, zinc, chromium, gallium, iron, The combination of one or more of cadmium, indium, thallium, cobalt, nickel, molybdenum, tin, lead.
Further, preferably, second metal material is zinc.
In addition, preferably, the interconnection structure further include be arranged in the metal interconnecting layer side through-hole connection it is mutual Line.
In addition, preferably, the seed layer is additionally arranged between the through-hole connection interconnection line and the dielectric layer.
In addition, preferably, it includes first metal material and second metal material that the seed layer, which uses, Alloy material is made, and first seed layer and second of sublayer are configured to same phase.
By the way that the first seed layer and second of sublayer are configured to same phase, the first seed layer has phase with second of sublayer Same interface, when the second metal material of second of sublayer aoxidizes to form passivation layer, which will cover the first seed simultaneously The surface of layer, more efficiently the first seed layer and electroplate liquid barrier to come.
Further, preferably, the alloy material is brass.
Detailed description of the invention
Fig. 1-4 is each step of process flow that the interconnection structure of semiconductor devices is formed in an embodiment of the utility model The schematic diagram of middle interconnection structure.
Description of symbols
1- substrate;1a- contact structures;2- dielectric layer;2a- interconnects line trenches;2b- through-hole;4- seed layer;The interconnection of 5- metal Layer;5a- through-hole connects interconnection line.
Specific embodiment
With reference to the accompanying drawings of the specification, the utility model is described in further detail.It is schematically simple in attached drawing Change shows the interconnection structure etc. of semiconductor devices.
The present embodiment provides firstly a kind of forming method of semiconductor devices, comprising the following steps:
It is shown in Figure 1, substrate 1 is provided, and form dielectric layer 2 on the base 1.
Substrate 1, which can be, to be formed with device architecture or is not formed the body silicon of device architecture, silicon-on-insulator (SOI), It is also possible to be formed with device architecture or the germanium of device architecture, germanium silicon, GaAs or germanium on insulator is not formed.This reality It applies in example, substrate 1 is to be formed with device (not shown), interlayer dielectric layer and the first intermetallic dielectric layer (not show in figure Body silicon base out).Wherein, contact structures 1a is formed in interlayer dielectric layer, contact structures 1a is tungsten plug.
In some embodiments of the utility model, dielectric layer 2 can be interlayer dielectric layer (ILD), be also possible to metal Between dielectric layer (IMD).In the present embodiment, dielectric layer 2 is the second intermetallic dielectric layer (IMD2).The material of dielectric layer 2 can be (dielectric coefficient is big for silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride, low k dielectric materials In or be equal to 2.5, less than 3.9, such as porous silica or porous silicon nitride) or ultra-low k dielectric material (dielectric coefficient is less than 2.5, such as porous SiC OH).In the present embodiment, the material of the dielectric layer is silica;The formation process of the deielectric-coating For fluid chemistry vapor deposition (Flowable Chemical Vapor Deposition, FCVD) technique, high-density plasma Deposit one of (High Density Plasma, HDP) technique, plasma enhanced deposition technique or a variety of.
It is shown in Figure 2, through-hole 2b and interconnection line trenches 2a is formed in dielectric layer 2.
The formation of through-hole 2b and interconnection line trenches 2a can be specifically includes the following steps: form patterning on dielectric layer 2 The first photoresist layer;Using the first photoresist layer as exposure mask, using the first anisotropic dry etch process, etch media layer 2; The first photoresist layer is removed, forms patterned second photoresist layer on dielectric layer 2;Using the second photoresist layer as exposure mask, adopt With the second anisotropic dry etch process, etch media layer 2.
Shown in Figure 3, deposit forms seed layer 4 in through-hole 2b and interconnection line trenches 2a.
In some embodiments of the utility model, seed layer 4 can be made of the first seed layer and second of sublayer, the One seed layer is covered on through-hole 2b and the interconnection surface line trenches 2a, second of sublayer are covered on the first sub-layer surface;Alternatively, the Two seed layers are covered on through-hole 2b and the interconnection surface line trenches 2a, the first seed layer are covered on second seed layer surface.Wherein, The material of one seed layer is copper, and the material of second of sublayer is zinc.
In the present embodiment, seed layer 4 is made by brass alloys, and brass alloys are the alloy including at least metallic copper and zinc Material.Alloy material is uniform solid solution, is existed as an individual phase.
It is shown in Figure 4, by chemical plating method, metallic copper, and benefit are deposited in through-hole 2b and interconnection line trenches 2a It is ground with chemical-mechanical planarization technology, until exposing the top surface of dielectric layer 2, forms metal interconnecting layer 5.
During electroless plating, electroplate liquid is acid copper sulfate baths.Electric current flows to yin from the copper electrode of anode The substrate 1 of pole, sulfuric acid copper ionization are Cu2+And SO4 2-, Cu2+It is flow to substrate 1 with electric current, and in through-hole 2b and interconnection line trenches 2a Reduction reaction and nucleating growth occur for interior 4 surrounding of seed layer, ultimately form metal interconnecting layer 5.
In the present embodiment, using brass alloys as seed layer 4, since brass alloys are homogeneous phase, the copper on surface can To help seed layer that it is kept to cause the effect of copper conductor deposition growing, meanwhile, the zinc on surface can be because of activity compared with Gao You It is first passivated with sulfuric acid reaction, generates fine and close oxide passivation layer, be coated on brass alloys surface, prevent seed layer 4 by acid The corrosion of property solution.
The present embodiment further provides a kind of interconnection structure of semiconductor devices, shown in Figure 4, comprising: dielectric layer 2;Metal interconnecting layer 5 is set in dielectric layer 2, and metal interconnecting layer 5 is made by the first metal material;Seed layer 4 is set to Jie Between matter layer 2 and metal interconnecting layer 5, seed layer 4 has the first seed layer and second of sublayer, and the first seed layer is by the first metal Material is made, and second of sublayer is made by the second metal material that metal active is better than the first metal material.
The first metal material is copper in the present embodiment.Specifically, compared with other metal materials, the resistivity of copper compared with Ability that is low, resisting electromigration is stronger, and is easy to obtain, and is common metal material in semiconductor devices.
Based on the selection of the first metal material, the second metal material is zinc.It can be led to using zinc as the second metal material It crosses the preferential mode for participating in electrochemical corrosion and protects the first metal material (copper).Wherein, the chemical property of zinc is more active, favorably In the generation of electrochemical corrosion, there is preferable protecting effect, and zinc acquisition is easier.In addition, zinc reacts energy in electroplate liquid Enough oxidation films in the densification of its Surface Creation, to prevent the corrosion of electroplate liquid.
Certainly, in the other embodiments of the utility model, the second metal material can also for hafnium, aluminium, titanium, zirconium, vanadium, The combination of one or more of manganese, niobium, zinc, chromium, gallium, iron, cadmium, indium, thallium, cobalt, nickel, molybdenum, tin, lead, as long as the second metal material The metal active of material is better than the first metal material, and can form primary battery with the first metal material in electroplate liquid to subtract Few corrosion of the electroplate liquid to the first metal material.
Specifically, during electroless plating, electroplate liquid is changed into electrochemistry corruption to the chemical attack of the first metal material Erosion can reduce corrosion of the electroplate liquid to the first metal material by sacrificing the second metal material, to be conducive to subsequent metal The growth of interconnection layer 5.Wherein, the first metal material is protected as the anode of electrochemical corrosion, and the second metal material is as negative Pole is corroded.
It is further preferred that in the present embodiment, in order to further strengthen the protecting effect of second of sublayer, seed layer 4 Surface is also formed with passivation layer (not shown).Passivation layer due to being formed in 4 surface of seed layer will not be plated corrosion, And passivation layer covers the surface of seed layer 4, therefore can deaden electroplate liquid and contact with seed layer 4, plays protection seed The effect of layer 4.By reducing the contact of electroplate liquid and seed layer 4, corrosion of the electroplate liquid to the first metal material can be weakened, had Effect ground reduces cavity blemish, so that the step of subsequent formation metal interconnecting layer 5 can be gone on smoothly, improves and partly leads The quality of body device.
Also, in the present embodiment, in order to reduce to form passivation layer needed for processing step, control production cost, passivation Layer is made by the oxide of the second metal material.Wherein, passivation layer made from the oxide of the second metal material can be by second Seed layer directly reacts to obtain with acidic Bath, easily facilitates preparation.
In the present embodiment, seed layer 4 is made using the alloy material for including the first metal material and the second metal material, the One seed layer and second of sublayer are configured to same phase.
Wherein, since the material of metal interconnecting layer 5 is the first metal material, be conducive to forming metal interconnecting layer 5 When need the first metal material seed crystal boundary carry out crystal growth.Also, due to formed seed layer 4 in the first seed layer and Second of sublayer is configured to same phase, therefore the first seed layer and second of sublayer interface having the same, when second of sublayer The second metal material when aoxidizing to form passivation layer, which will cover the surface of the first seed layer simultaneously, can more added with First seed layer and electroplate liquid barrier are come on effect ground.
In the embodiment that the first metal material is copper, the second metal material is zinc, alloy material is brass.Wherein, yellow Copper is standby simply, it is low to obtain difficulty, and can satisfy the demand of above-mentioned metal active, it is ensured that the metal interconnecting layer 5 of formation Quality.
In addition, in the present embodiment, interconnection structure further includes the through-hole connection interconnection line that 5 side of metal interconnecting layer is arranged in 5a.Wherein, seed layer 4 is additionally arranged between through-hole connection interconnection line 5a and dielectric layer 2.By being connect in dielectric layer 2 with through-hole Seed layer 4 is formed between interconnection line 5a, can be reduced cavity blemish in the processing step for forming through-hole connection interconnection line 5a, be mentioned The reliability of high through-hole connection interconnection line 5a, to improve the quality of semiconductor devices.
It will be understood by those skilled in the art that in above-mentioned each embodiment, in order to keep reader more preferably geographical It solves the application and proposes many technical details.But even if without these technical details and based on the respective embodiments described above Various changes and modifications can also realize each claim of the application technical solution claimed substantially.Therefore, in reality In, can to above embodiment, various changes can be made in the form and details, without departing from the spirit of the utility model And range.

Claims (10)

1. a kind of interconnection structure of semiconductor devices characterized by comprising
Dielectric layer;
Metal interconnecting layer is set in the dielectric layer, and the metal interconnecting layer is made by the first metal material;
Seed layer is set between the dielectric layer and the metal interconnecting layer, and the seed layer has the first seed layer and the Two seed layers, first seed layer are made by first metal material, and second of sublayer is better than institute by metal active The second metal material for stating the first metal material is made.
2. interconnection structure according to claim 1, which is characterized in that the surface of the seed layer is also formed with passivation layer.
3. interconnection structure according to claim 2, which is characterized in that the passivation layer by second metal material oxygen Compound is made.
4. interconnection structure described in any one of -3 according to claim 1, which is characterized in that first metal material is Copper.
5. interconnection structure according to claim 4, which is characterized in that second metal material be hafnium, aluminium, titanium, zirconium, One of vanadium, manganese, niobium, zinc, chromium, gallium, iron, cadmium, indium, thallium, cobalt, nickel, molybdenum, tin, lead.
6. interconnection structure according to claim 5, which is characterized in that second metal material is zinc.
7. interconnection structure according to claim 1, which is characterized in that the interconnection structure further includes being arranged in the metal The through-hole of interconnection layer side connects interconnection line.
8. interconnection structure according to claim 7, which is characterized in that it is mutual that the seed layer is additionally arranged at the through-hole connection Between line and the dielectric layer.
9. interconnection structure according to claim 1, which is characterized in that it includes first metal material that the seed layer, which uses, The alloy material of material and second metal material is made, and first seed layer and second of sublayer are configured to same Phase.
10. interconnection structure according to claim 9, which is characterized in that the alloy material is brass.
CN201920511807.XU 2019-04-15 2019-04-15 Interconnection structure Expired - Fee Related CN209571414U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201920511807.XU CN209571414U (en) 2019-04-15 2019-04-15 Interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201920511807.XU CN209571414U (en) 2019-04-15 2019-04-15 Interconnection structure

Publications (1)

Publication Number Publication Date
CN209571414U true CN209571414U (en) 2019-11-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
CN (1) CN209571414U (en)

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