CN209515676U - Semiconductor devices and chip - Google Patents
Semiconductor devices and chip Download PDFInfo
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- CN209515676U CN209515676U CN201920301065.8U CN201920301065U CN209515676U CN 209515676 U CN209515676 U CN 209515676U CN 201920301065 U CN201920301065 U CN 201920301065U CN 209515676 U CN209515676 U CN 209515676U
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Abstract
The utility model relates to a kind of semiconductor devices and chip, which includes: terminal trenches grid structure and several cellular trench gate structures in substrate；The terminal trenches grid structure has along the spaced several annular side surfaces of direction initialization；Several cellular trench gate structures are located at the inside of several annular side surfaces, and the annular side surface of each terminal trenches grid structure is arranged concentrically with the side surface of the cellular trench gate structure of corresponding inside with constant space.The technical solution of the utility model, which solves the problems, such as that the trench gate structure spacing of existing splitting bar trench MOSFET cannot be consistent, causes electrical parameter consistency poor.
Description
Technical field
The utility model relates to technical field of semiconductors more particularly to a kind of semiconductor devices and chip.
Background technique
Compared to plane MOSFET (Metal Oxide Semiconductor Field Effect Transistor), trench MOSFET is vertical because of it
Conductive feature has many advantages, such as driving current is big, power density is high, conducting resistance is small, thus is widely applied.Its
In, splitting bar trench MOSFET is due to can reduce internal resistance as a kind of common trench MOSFET.
As shown in Figure 1, a kind of existing splitting bar trench MOSFET includes several trench gates in substrate 1 and substrate 1
Structure 2 (only illustrates one) in figure.Wherein, trench gate structure 2 includes 20 inner wall of groove 20 and covering groove in substrate 1
Dielectric layer 21, first grid 22 and second grid 23.First grid 22 is located at second grid 23 along the depth direction of groove 20
Lower section, and the two is kept apart by dielectric layer 21.
Several trench gate structures include two class of cellular trench gate structure and terminal trenches grid structure, wherein several terminal ditches
Slot grid structure is located at the outside of several cellular trench gate structures, using as terminal protection structure.About cellular trench gate structure with
Specific arrangement mode between terminal trenches grid structure common are following two kinds:
As shown in Fig. 2, several bar shaped cellular trench gate structure 2a are alternatively arranged along direction X1, two neighboring cellular trench gate
D1 is divided between structure 2a, several bar shaped terminal trenches grid structure 2b are distributed in several cellular trench gate structures along direction Y1
The two sides of 2a, and terminal trenches grid structure 2b is perpendicular to cellular trench gate structure 2a, terminal trenches grid structure 2b and cellular groove
D2 is divided between grid structure 2a, D2 is equal to D1.
As shown in figure 3, several bar shaped cellular trench gate structure 2c are alternatively arranged along direction X2, several arcuate terminal ends trench gates
Structure 2d is arranged in the outside of several cellular trench gate structure 2c.
However, above-mentioned splitting bar trench MOSFET, which has trench gate structure spacing, cannot be consistent so that there is electricity
The problem of parameter consistency difference.For example, with continued reference to Fig. 2, between terminal trenches grid structure 2b and cellular trench gate structure 2a
Although interval D 2 is equal to D1, electric stress of the substrate in the area Tu2Zhong A and the area B in channel bottom by two grooves only ensure that
Couple it is identical, but the substrate in the area C by from the electric stress of terminal trenches and the cellular groove tripartite of two sides tilted direction couple,
The electric stress in the area C is just different with the electric stress in the area A, B in this way.With continued reference to Fig. 3, terminal trenches grid structure 2d shown in a-quadrant
Interval between cellular trench gate structure 2c is not equal to terminal trenches grid structure 2d shown in B area and cellular trench gate structure
Interval between 2c, and cannot be guaranteed that substrate everywhere is consistent by the electric stress coupling of channel bottom
In addition, above-mentioned splitting bar trench MOSFET there is also place die stress unanimously towards the problem of because all
Cellular trench gate structure is arranged along the same direction, is easy to cause chip excessive stress.
Utility model content
Technical problem to be solved in the utility model first is that, the trench gate structure of existing splitting bar trench MOSFET
The poor problem of spacing consistency.
Technical problem to be solved in the utility model second is that, the deep trench of existing splitting bar trench MOSFET easily causes
Die stress is concentrated where making it.
To solve the above-mentioned problems, the utility model provides a kind of semiconductor devices comprising: the end in substrate
Hold trench gate structure and several cellular trench gate structures；If the terminal trenches grid structure has spaced along direction initialization
Dry annular side surface；Several cellular trench gate structures are located at the inside of several annular side surfaces, and each institute
Annular side surface and the side surface of the cellular trench gate structure of corresponding inside for stating terminal trenches grid structure are concentric with constant space
Setting.
Optionally, the annular side surface of the terminal trenches grid structure, the cellular trench gate structure side surface cross
It is round rectangle or orthogonal rectangle to section.
Optionally, the terminal trenches grid structure includes: several first segments；Several second segments, with several cellular ditches
Slot grid structure is staggeredly alternatively arranged along the direction initialization；The end of the two of the arbitrary neighborhood second segments on the direction initialization
Portion is connected by the first segment；When the transversal cross-section is round rectangle, the first segment is segmental arc, and the second segment is
Bar segment；When the transversal cross-section is orthogonal rectangle, the first segment, second segment are bar segment.
Optionally, the thickness of the first segment is equal with the thickness of the second segment, described with a thickness of being parallel to the lining
Size on the direction at bottom.
Optionally, the thickness of the cellular trench gate structure is equal to the thickness of the first segment.
Optionally, the semiconductor devices includes the division with the terminal trenches grid structure and cellular trench gate structure
Gate groove type MOSFET；The terminal trenches grid structure and cellular trench gate structure include: the groove in the substrate；
It is covered in the dielectric layer of the trench wall；First grid in the groove, the first grid pass through the dielectric
Layer is kept apart with substrate；The cellular trench gate structure further includes the second grid in the groove, the first grid
Pole and second grid are kept apart by the dielectric layer.
Optionally, the first grid and second grid are arranged along the direction interval for being parallel to the substrate, and described the
Two grids are located at the outside of the first grid.
Optionally, the first grid and second grid are alternatively arranged along the depth direction of the groove.
Optionally, further includes: the insulation on the substrate, terminal trenches grid structure and cellular trench gate structure
Layer；Across the first conductive plunger of the insulating layer, first conductive plunger and the first grid form Ohmic contact electricity
Connection；Metal layer on the insulating layer and the first conductive plunger, the metal layer and first conductive plunger electricity
Connection.
Optionally, first kind doped region and Second Type doped region are formed in the substrate, the Second Type is mixed
Miscellaneous area is located at the surface of the first kind doped region；The semiconductor devices further include: pass through the insulating layer and the second class
Second conductive plunger of type doped region, second conductive plunger and the first kind doped region, Second Type doped region are equal
Form Ohmic contact electrical connection.
Optionally, the semiconductor devices includes the groove with the terminal trenches grid structure and cellular trench gate structure
Type Schottky diode；The terminal trenches grid structure and cellular trench gate structure include: the groove in the substrate；
It is covered in the dielectric layer of the trench wall；In the groove and the grid that is covered on the dielectric layer.
In addition, the utility model additionally provides a kind of chip comprising any of the above-described semiconductor devices.
Optionally, the cellular trench gate structure of at least one semiconductor devices is arranged along first direction interval
Column, the cellular trench gate structure of the semiconductor devices another at least within are alternatively arranged in a second direction, and described second
Direction is perpendicular to the first direction.
In the semiconductor devices of the utility model, the cellular ditch of the annular side surface of terminal trenches grid structure and corresponding inside
The side surface of slot grid structure is arranged concentrically with constant space so that the annular side surface of each terminal trenches grid structure with it is corresponding
Spacing of the side surface of the cellular trench gate structure of inside on 360 degree of directions remains definite value, realizes trench gate structure
Spacing is consistent, so that product electrical parameter has better consistency.
By the way that the cellular trench gate structure of semiconductor devices certain in chip is alternatively arranged along first direction, other
The cellular trench gate structure of semiconductor devices is alternatively arranged along the second direction perpendicular to first direction, realizes the member on chip
Born of the same parents' trench gate structure is alternately distributed along two perpendicular directions, and consistent court will not be presented in cellular deep groove structure bring stress
To.
Detailed description of the invention
Fig. 1 is a kind of diagrammatic cross-section of existing splitting bar trench MOSFET；
Fig. 2 is in splitting bar trench MOSFET shown in Fig. 1 between cellular trench gate structure and terminal trenches grid structure
A kind of planar arrangement figure；
Fig. 3 is in splitting bar trench MOSFET shown in Fig. 1 between cellular trench gate structure and terminal trenches grid structure
Another planar arrangement figure；
Fig. 4 be semiconductor devices in an embodiment of the present invention cellular trench gate structure and terminal trenches grid structure it
Between planar arrangement figure；
Fig. 5 is sectional view of the Fig. 4 along the direction A-A；
Fig. 6 is sectional view of the Fig. 4 along the direction B-B；
Fig. 7 is the diagrammatic cross-section of semiconductor devices in the utility model first embodiment；
Fig. 8 to Figure 13 is diagrammatic cross-section of the semiconductor devices shown in Fig. 7 in each production phase；
Figure 14 is the diagrammatic cross-section of semiconductor devices in the utility model second embodiment；
Figure 15 is the diagrammatic cross-section of semiconductor devices in the utility model 3rd embodiment；
Figure 16 is the floor map of chip in an embodiment of the present invention.
Specific embodiment
Fig. 4 be semiconductor devices in an embodiment of the present invention cellular trench gate structure and terminal trenches grid structure it
Between planar arrangement figure, Fig. 5 is sectional view of the Fig. 4 along the direction A-A, and Fig. 6 is sectional view of the Fig. 4 along the direction B-B, extremely in conjunction with Fig. 4
Shown in Fig. 6, the semiconductor devices of the present embodiment includes terminal trenches grid structure 20 in the substrate 10 and several (with three in figure
For a) cellular trench gate structure 30.
The terminal trenches grid structure 20 has along the spaced several annular side surface F1 of direction initialization X, in this reality
In novel, so-called side surface refers to that, along the surface of the thickness direction Z extension of substrate 10, so-called annular refers in 360 degree of directions
Upper is in closed, which can be circle, or the ring-type other than round.Several cellular trench gate structures 30 distinguish position
In the inside of the annular side surface F1 of several terminal trenches grid structures 20 so that terminal trenches grid structure 20 be distributed in it is each
The periphery of cellular trench gate structure 30, using as terminal protection structure.
The side table of the annular side surface F1 of each terminal trenches grid structure 20 and the cellular trench gate structure 30 of corresponding inside
Face F2 is arranged concentrically with constant space, it may be assumed that the annular side surface F1 of all terminal trenches grid structures 20 and all cellular trench gates
Structure 30 corresponds, and the annular side surface F1 of each terminal trenches grid structure 20 is located at a corresponding cellular trench gate knot
The periphery of structure 30, the side table of the annular side surface F1 of each terminal trenches grid structure 20 and corresponding cellular trench gate structure 30
Face F2 has same shape, and each annular side surface F1 and the side surface F2 of corresponding inside are arranged concentrically with constant space S,
So that the spacing of each annular side surface F1 and the side surface F2 of corresponding inside on 360 degree of directions remains S, realize
Trench gate structure spacing in semiconductor devices is consistent, so that product electrical parameter has better consistency.
In some embodiments, the interval S between annular side surface F1 and the side surface F2 of corresponding inside be 0.5 μm extremely
2.5 μm, terminal trenches grid structure 20, the depth of cellular trench gate structure 30 are 1 μm to 15 μm.
In the present embodiment, the annular side surface F1 of each terminal trenches grid structure 20, the cellular trench gate structure 30
The transversal cross-section shape of side surface F2 be round rectangle, so-called transversal cross-section shape refers on the direction for being parallel to substrate
Cross sectional shape, so-called rounded rectangles refer to rectangle two of them side be parallel interval setting linear, two other side
For the semicircle shape or nearly semicircle shape tangent with the two of them side.
Certainly, in other embodiments, the annular side surface F1, cellular trench gate structure 30 of terminal trenches grid structure 20
Side surface F2 may be set to be other easily fabricated annular surfaces, as long as the two is arranged concentrically, such as round, fillet
Hexagon etc..For example, in an alternative, annular side surface F1, the cellular trench gate structure 30 of terminal trenches grid structure 20
The transversal cross-section shape of side surface F2 can also be orthogonal rectangle, manufacture processing of being more convenient in this way.In this alternative,
Terminal trenches grid structure includes the side of several the first bar segments extended along direction initialization X and several edges perpendicular to direction initialization X
To the second bar segment of extension, between all second bar segments and all cellular trench gate structures interlock along direction initialization X
Every arrangement, and on direction initialization X, the end of two second bar segments of arbitrary neighborhood is connected by first bar segment.
In the present embodiment, terminal trenches grid structure 20 includes several (in figure for four) bar segments 21 and several
(in figure for six) segmental arc 22, several bar segments 21 are with several cellular trench gate structures 30 along the direction initialization
X is staggeredly alternatively arranged, and the end of the two of the arbitrary neighborhood bar segments 21 passes through the segmental arc 22 on the direction initialization X
Connection, so that two bar segments 21 of arbitrary neighborhood and corresponding two segmental arcs 22 for connecting two bar segments 21 surround packet
Enclose the rounded rectangles of a cellular trench gate structure 30, the side outer profile F3 and annular side surface F1 of terminal trenches grid structure 20
There is same shape in opposite position.
It should be noted that in other embodiments, the side outer profile F3 and annular side surface of terminal trenches grid structure 20
F1 also can have different shape in opposite position, such as the side outer profile F3 of terminal trenches grid structure 20 is rectangle, circle
Shape, ellipse etc..
Further, the thickness D1 of the segmental arc 22, the thickness D3 of the bar segment 21, cellular trench gate structure 30
Thickness D2 is equal, so that the thickness of terminal trenches grid structure 20, cellular trench gate structure 30 keeps identical, so-called thickness refers to
The size being parallel on the direction of the substrate.In some embodiments, thickness D1, D2, D3 is set as 1 μm to 3.5 μm.
It should be noted that in other embodiments, terminal trenches grid structure 20, cellular trench gate structure 30 thickness can also
To be set as different, such as the thickness of terminal trenches grid structure 20 is greater than the thickness of cellular trench gate structure 30.
According to described above it is found that the above-mentioned arrangement mode between terminal trenches grid structure and cellular trench gate structure can
Realize that the trench gate structure spacing in semiconductor devices is consistent, so that product electrical parameter has better consistency.Terminal
The arrangement mode between trench gate structure and cellular trench gate structure can be applied in a variety of partly leading with trench gate structure
In body device, three embodiments will be passed sequentially through below and will be explained.
First embodiment
Fig. 7 is the diagrammatic cross-section of semiconductor devices in the utility model first embodiment, as shown in fig. 7, the semiconductor
Structure includes splitting bar trench MOSFET, which includes the terminal trenches grid structure 20 in substrate 10
With several cellular trench gate structures 30, the arrangement mode between terminal trenches grid structure 20 and several cellular trench gate structures 30 is joined
Examine described above, details are not described herein.
Terminal trenches grid structure 20, cellular trench gate structure 30 include the groove T in substrate 10, and dielectric layer 40 covers
Be placed on the inner wall of groove T, first grid 50 is located in the groove T, and first grid 50 by dielectric layer 40 and substrate 10 every
It leaves and.Wherein, cellular trench gate structure 30 further includes the second grid 60 in groove T, second grid 60 and the first grid
Pole 50 is kept apart by dielectric layer 40.Specifically, the first grid 50 and second grid 60 are along being parallel to the substrate 10
The setting of direction interval, and the second grid 60 is located at the outside of the first grid 50.In further embodiments, second
The depth of grid 60 is 0.6 μm to 2 μm.
In the present embodiment, substrate 10 includes first kind heavy doped conduction substrate 101 and first kind heavy doped conduction substrate 101
The first kind lightly doped epitaxial layer 102 on surface is formed with first kind doped region in first kind lightly doped epitaxial layer 102
103 and Second Type doped region 104, the Second Type doped region 104 be located at the surface of the first kind doped region 103.
In the present embodiment, the material of substrate 10 is silicon, and the first kind is N-type, and Second Type is p-type.In other embodiments,
According to the type of semiconductor devices, it may be set to be that the first kind is p-type, Second Type is N-type.Specifically, first
The depth of type doped region 103 can be set to 0.2 μm to 1.5 μm, and the depth of Second Type doped region 104 can be set to
0.1 μm to 0.7 μm.
In the present embodiment, the longitudinal cross-section of groove T is substantially rectangular cross-sectional configuration, and side wall is vertical with 10 surface of substrate, and bottom
There is fillet so that groove T inner wall surface is more smooth can avoid the occurrence of spike electric field for corner, so that improves device can
By property.In other specific embodiments of the utility model, groove T has sloped sidewall, so that the top width of groove T is omited
Greater than bottom width, convenient for filling trench interiors substance, the tilt angle of the specific sloped sidewall, i.e., the described sloped sidewall
Angle between 10 surface of substrate is 85 °~90 ° (89.5~90deg is best), can make current path upper width can also
Consistent to reach bottom width, conducting resistance reduces.
In the present embodiment, the material of dielectric layer 40 is silica, and the material of first grid 50 and second grid 60 is more
Crystal silicon, and first grid 50 is the heavy doping of the first kind.
With continued reference to shown in Fig. 7, it is covered on substrate 10, terminal trenches grid structure 20 and several cellular trench gate structures 30
Insulating layer 70, the first conductive plunger CT1 passes through insulating layer 70, and forms Ohmic contact with first grid 50 and be electrically connected, and second leads
Electric plug CT2 pass through the insulating layer 70 and Second Type doped region 104, and with the first kind doped region 103, the second class
Type doped region 104 is respectively formed Ohmic contact electrical connection.Metal layer 80 is located at the insulating layer 70, the first conductive plunger CT1, second
On conductive plunger CT2, and it is electrically connected with the first conductive plunger CT1, the second conductive plunger CT2.Metal layer 80 is led by second
Electric plug CT2 and first kind doped region 103 form Ohmic contact, are shorted first kind doped region 103 and Second Type doping
Area 104 is to avoid parasitic triode conducting.Third conductive plunger is (not shown) to pass through insulating layer 70, one end and second grid 60
Ohmic contact electrical connection is formed, the other end is electrically connected with another metal layer (not shown), another to this when which works
One metal layer applies different voltages from metal layer 80.
In the present embodiment, insulating layer 70 is undoped silicon glass or p-doped Pyrex, the first conductive plunger CT1, the
The aperture of two conductive plunger CT2 is 0.2 μm to 1.2 μm, and the material of metal layer 80 includes other metal materials such as aluminium or Cu.
Fig. 8 to Figure 13 is diagrammatic cross-section of the semiconductor devices shown in Fig. 7 in each production phase, extremely below with reference to Fig. 7
The forming method of the semiconductor devices of first embodiment is described in detail in Figure 13.
As shown in figure 8, providing substrate 10.Substrate 10 includes that first kind heavy doped conduction substrate 101 and the first kind are heavily doped
The first kind lightly doped epitaxial layer 102 on miscellaneous 101 surface of substrate.In the present embodiment, the material of substrate 10 be silicon, described first
Type is N-type, and Second Type is p-type.In other embodiments, it according to the type of semiconductor devices, may be set to be described
The first kind is p-type, Second Type is N-type.
Several groove T are formed in the lightly doped epitaxial layer 102 of substrate 10, which includes two kinds, is respectively used for shape
At the terminal trenches of terminal trenches grid structure, it is used to form the cellular groove of cellular trench gate structure.Form the method packet of groove T
It includes: forming Patterned masking layer (not shown) on substrate 10；Substrate 10 is carved using the Patterned masking layer as mask
Erosion, to form groove T, the method for the etching can be dry etching or wet etching；Remove the Patterned masking layer.
As shown in connection with fig. 4, in several groove T, the terminal trenches where terminal trenches grid structure 20 have along setting side
To the spaced several annular side surfaces of X, the cellular groove where several cellular trench gate structures 30 is located at several institutes
State the inside of annular side surface, and the side table of the annular side surface of each terminal trenches and the cellular trench gate of corresponding inside
Face is arranged concentrically with constant space.
With continued reference to shown in Fig. 8, upper surface, the side wall of groove T and the first dielectric of bottom wall of covering substrate 10 are formed
Material layer 400, the first dielectric materials layer 400 do not fill up groove T.The material of first dielectric materials layer 400 is silica, thickness
It is 0.5 μm to 2 μm, forming method is chemical vapor deposition, thermal oxide, atomic layer deposition etc..On the first dielectric materials layer 400
First grid material layer 500 is formed, part first grid material layer 500 is filled in groove T.First grid material layer 500
Material is polysilicon, and forming method is chemical vapor deposition, atomic layer deposition etc..
As shown in figure 9, the first grid material layer 500 (in conjunction with Fig. 8) except removal groove T, remaining first grid material
The bed of material 500 constitutes first grid 50.The minimizing technology of first grid material layer 500 is dry etching.
As shown in Figure 10, part first dielectric materials layer 400 (in conjunction with Fig. 9) in cellular groove T is removed, so that institute
The end sidewalls of the top sidewall, groove T of stating the first grid 50 in cellular groove T are all exposed.In some embodiments, expose
First grid 50 top sidewall depth H be 0.6 μm to 2 μm.
As shown in figure 11, second is formed in the top sidewall of the first grid 50 of exposing, the end sidewalls of groove T
Dielectric materials layer 401, second dielectric materials layer 401 is interior, and there is the groove for being located at 50 periphery of first grid (not mark
Know).The material of second dielectric materials layer 401 be silica, by thermal oxide expose the first grid 50 top sidewall,
The end sidewalls of groove T are formed.Form the second grid material layer 600 being covered on the second dielectric materials layer 401, second gate
Pole material layer 600 is filled in the groove of the second dielectric materials layer 401.In some embodiments, second grid material layer 600
Material is polysilicon.
As shown in figure 12, the second dielectric materials layer 401 except removal groove T and second grid material layer 600 are (in conjunction with figure
11), to be respectively formed terminal trenches grid structure 20 and cellular trench gate structure 30.Remove second dielectric materials layer of part 401
Method with second grid material layer 600 is etching or chemical mechanical grinding.
As shown in figure 13, ion implanting is carried out to the lightly doped epitaxial layer 102 of section substrate 10 to mix to form the first kind
Miscellaneous area 103.In the present embodiment, the first kind is N-type, and the depth of first kind doped region 103 is 0.2 μm to 1.5 μm.It connects
, ion implanting is carried out again in the surface layer shape of first kind doped region 103 to the lightly doped epitaxial layer 102 of section substrate 10
At Second Type doped region 104.In the present embodiment, Second Type is p-type, and the depth of Second Type doped region 104 is 0.1 μm
To 0.7 μm.
In conjunction with shown in Fig. 7 and Figure 13, formed on substrate 10, terminal trenches grid structure 20 and cellular trench gate structure 30
Insulating layer 70, in the present embodiment, the material of insulating layer 70 are undoped silicon glass or p-doped Pyrex, and forming method is to change
Learn vapor deposition.Then, it performs etching, to form the first jack (not identifying) across the insulating layer 70, third jack is (not
Diagram) and across insulating layer 70 and Second Type doped region 104 the second jack (not identifying), first jack exposes the
One grid 50, the third jack expose second grid 60, and second jack exposes first kind doped region 103.Then, to
Filling metal is in first jack and the second jack, third jack to be respectively formed and 50 Ohmic contact of the first grid electricity
First conductive plunger CT1 of connection, is electrically connected with the first kind doped region 103, the equal Ohmic contact of Second Type doped region 104
The the second conductive plunger CT2 connect, the third conductive plunger (not shown) being electrically connected with second grid 70.In the present embodiment,
One conductive plunger CT1, the second conductive plunger CT2 aperture be 0.2 μm to 1.2 μm.It is located at insulating layer 70, first finally, being formed
Metal layer 80 on conductive plunger CT1 and the second conductive plunger CT2 forms another gold being located on the third conductive plunger
Belong to layer (not shown).In the present embodiment, the material of metal layer 80 includes other metal materials such as aluminium or Cu, forms metal layer 80
Method be physical vapour deposition (PVD) or plating.
Second embodiment
Difference between second embodiment and first embodiment is: with reference to shown in Figure 14, the first grid 50 and the
Two grids 60 are alternatively arranged along the depth direction Z of groove T.
3rd embodiment
With reference to shown in Figure 15, in the present embodiment, semiconductor devices includes groove-shaped Schottky diode, the diode packet
Include terminal trenches grid structure 20b in substrate 10b and several cellular trench gate structure 30b, terminal trenches grid structure 20b and several
Arrangement mode between cellular trench gate structure 30b is with reference to described above, and details are not described herein.Terminal trenches grid structure 20b and
Cellular trench gate structure 30b includes the groove T1 being located in the substrate 10b, the dielectric layer for being covered in the groove T1 inner wall
40b, and in the groove T1 and the grid 50b that is covered on the dielectric layer 40b.Specifically, dielectric layer 40b
Material is silica, and the material of grid 50b is polysilicon.Schottky metal layer 90 is covered in substrate 10b, terminal trenches grid structure
On 20b and cellular trench gate structure 30b, to form Schottky contacts.
On the embodiment basis of above-mentioned semiconductor device, the utility model additionally provides a kind of chip, the chip packet
The first several semiconductor devices and several second of semiconductor devices are included, the first described semiconductor devices is led for second half
The specific structure of body device is with reference to described above, and details are not described herein.The cellular groove of the first semiconductor devices
Grid structure is alternatively arranged along first direction, the cellular trench gate structure of second of semiconductor devices in a second direction between
Every arrangement, for the second direction perpendicular to the first direction, the cellular trench gate structure as a result, on chip is perpendicular along two
Direction be alternately distributed, cellular trench gate structure bring stress is also alternately distributed along two perpendicular directions, avoids core
The problem of piece.
In embodiment, with reference to shown in Figure 16, chip includes semiconductor devices C1-C7, the cellular of semiconductor devices C1-C6
Trench gate structure 30c is alternatively arranged along first direction L1, the cellular trench gate structure 30d of three semiconductor devices C7 along perpendicular to
The second direction L2 of first direction L1 is alternatively arranged.Semiconductor devices C1-C3 arranges in a row along first direction L1, semiconductor device
Part C4-C6 arranges in a row along first direction L1, and L2 is alternatively arranged the two rows semiconductor devices in a second direction.Three semiconductors
Device C7 arranges in a row along first direction L1 and is distributed between the two rows semiconductor devices.
The above is only the preferred embodiment of the utility model, it is noted that for the common skill of the art
Art personnel can also make several improvements and modifications without departing from the principle of this utility model, these improvements and modifications
Also it should be regarded as the protection scope of the utility model.
Claims (13)
1. a kind of semiconductor devices characterized by comprising
Terminal trenches grid structure and several cellular trench gate structures in substrate；
The terminal trenches grid structure has along the spaced several annular side surfaces of direction initialization；
Several cellular trench gate structures are located at the inside of several annular side surfaces, and each terminal trenches
The annular side surface of grid structure is arranged concentrically with the side surface of the cellular trench gate structure of corresponding inside with constant space.
2. semiconductor devices according to claim 1, which is characterized in that the annular side table of the terminal trenches grid structure
Face, the cellular trench gate structure the transversal cross-section of side surface be round rectangle or orthogonal rectangle.
3. semiconductor devices according to claim 2, which is characterized in that the terminal trenches grid structure includes:
Several first segments；
Several second segments are staggeredly alternatively arranged with several cellular trench gate structures along the direction initialization；
The end of the two of the arbitrary neighborhood second segments is connected by the first segment on the direction initialization；
When the transversal cross-section is round rectangle, the first segment is segmental arc, and the second segment is bar segment；
When the transversal cross-section is orthogonal rectangle, the first segment, second segment are bar segment.
4. semiconductor devices according to claim 3, which is characterized in that the thickness of the first segment and the second segment
Thickness is equal, the size with a thickness of on the direction for being parallel to the substrate.
5. semiconductor devices according to claim 4, which is characterized in that the thickness of the cellular trench gate structure is equal to institute
State the thickness of first segment.
6. semiconductor devices according to any one of claims 1 to 5, which is characterized in that the semiconductor devices includes tool
There is the splitting bar trench MOSFET of the terminal trenches grid structure and cellular trench gate structure；
The terminal trenches grid structure and cellular trench gate structure include:
Groove in the substrate；
It is covered in the dielectric layer of the trench wall；
First grid in the groove, the first grid are kept apart by the dielectric layer with substrate；
The cellular trench gate structure further includes the second grid in the groove, and the first grid and second grid are logical
The dielectric layer is crossed to keep apart.
7. semiconductor devices according to claim 6, which is characterized in that the first grid is parallel to second grid edge
The direction interval of the substrate is arranged, and the second grid is located at the outside of the first grid.
8. semiconductor devices according to claim 6, which is characterized in that the first grid and second grid are along the ditch
The depth direction of slot is alternatively arranged.
9. semiconductor devices according to claim 7, which is characterized in that further include:
Insulating layer on the substrate, terminal trenches grid structure and cellular trench gate structure；
Across the first conductive plunger of the insulating layer, first conductive plunger and the first grid form Ohmic contact electricity
Connection；
Metal layer on the insulating layer and the first conductive plunger, the metal layer are electrically connected with first conductive plunger
It connects.
10. semiconductor devices according to claim 9, which is characterized in that be formed with first kind doping in the substrate
Area and Second Type doped region, the Second Type doped region are located at the surface of the first kind doped region；
The semiconductor devices further include: across the second conductive plunger of the insulating layer and Second Type doped region, described
Two conductive plungers are respectively formed Ohmic contact and are electrically connected with the first kind doped region, Second Type doped region.
11. semiconductor devices according to any one of claims 1 to 5, which is characterized in that the semiconductor devices includes tool
There is the groove-shaped Schottky diode of the terminal trenches grid structure and cellular trench gate structure；
The terminal trenches grid structure and cellular trench gate structure include:
Groove in the substrate；
It is covered in the dielectric layer of the trench wall；
In the groove and the grid that is covered on the dielectric layer.
12. a kind of chip, which is characterized in that including the described in any item semiconductor devices of several claims 1 to 11.
13. chip according to claim 12, which is characterized in that the member of at least one semiconductor devices
Born of the same parents' trench gate structure is alternatively arranged along first direction, the cellular trench gate structure of the semiconductor devices another at least within
It is alternatively arranged in a second direction, the second direction is perpendicular to the first direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920301065.8U CN209515676U (en) | 2019-03-11 | 2019-03-11 | Semiconductor devices and chip |
Applications Claiming Priority (1)
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| CN109935635B (en) * | 2019-03-11 | 2024-03-12 | 福建龙夏电子科技有限公司 | Semiconductor device, forming method thereof and chip |
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