CN209471444U

CN209471444U - Main control chip, chip and chip upgrade system

Info

Publication number: CN209471444U
Application number: CN201920567444.1U
Authority: CN
Inventors: 高文宏; 李孟; 梁永强; 赵博阳
Original assignee: Beijing Radium Hi Tech Photoelectric Technology Co Ltd
Current assignee: Jiangsu radium Technology Co.,Ltd.
Priority date: 2019-04-24
Filing date: 2019-04-24
Publication date: 2019-10-08
Anticipated expiration: 2029-04-24

Abstract

This application discloses a kind of main control chip, chip and chip upgrade systems, in main control chip provided herein, comprising: the communication port of main control chip receives upgrade file；First pin of main control chip is connected by Master Communications line with the chip of all levels, and second pin is connected by downloading notice line with the chip of all levels, and third pin is connected by chip select line with the chip of all levels；Main control chip according to the upgrade file, determine upgrade file for upgrading promotion levels chip；Wherein, promotion levels chip are as follows: the level chip corresponding with upgrade file in the chip of all levels；Main control chip notifies line to send control signal to downloading, and the first pin for controlling main control chip passes through the on-off of Master Communications line and the communication channel of the chip of all levels foundation；For main control chip by chip select line corresponding with promotion levels chip, piece chooses the chip of promotion levels, and the chip of upgrade file to promotion levels is sent by communication channel.

Description

Main control chip, chip and chip upgrade system

Technical field

This application involves electronic technology fields, and in particular to a kind of main control chip, chip and chip upgrade system.

Background technique

With the development of electronic technology, the use of electronic equipment is more and more common in all trades and professions.Currently on the market mostly Several electronic equipments is all to carry out assembling it to the module in electronic equipment as made of the identical module assembled of multiple functions Before, the chip in modules that can be assembled respectively to needs first carries out hardware debugging and software download, finally to all moulds Module is carried out being assembled into complete machine and be dispatched from the factory after block completes hardware debugging and software download.

Since electronic equipment is by constituting by completing hardware debugging and each standalone module after software download, in electricity In the use process of sub- equipment in the future, if wanting to modify to the chip in module each in electronic equipment, then need to electricity Chip in sub- equipment in each standalone module carries out software upgrading, at this point, then needing module all in electronic equipment is only Vertical carry out software upgrading, considerably increases the maintenance difficulties of maintenance personnel, improves maintenance cost.

So being badly in need of a kind of upgrade method for chip in standalone modules more in electronic equipment, to solve containing multiple In the electronic equipment of standalone module the problem of modules scaling difficulty.

Utility model content

In view of this, the main purpose of the application is to provide a kind of main control chip, chip and chip upgrade system, with solution Certainly in but standalone module equipment identical containing multiple functions the problem of modules scaling difficulty.

The application first aspect discloses a kind of main control chip, and the main control chip is used to carry out the chip of multiple levels Upgrading, wherein each level includes at least one chip, and the main control chip includes:

The communication port of the main control chip, the communication port is for receiving upgrade file；

First pin of the main control chip is connected by Master Communications line with the chip of all levels, and second pin passes through Downloading notice line is connected with the chip of all levels, and third pin passes through the chip phase of chip select line and all levels Even；

The main control chip according to the upgrade file, determine the upgrade file for upgrading promotion levels chip； Wherein, the promotion levels chip are as follows: the level chip corresponding with the upgrade file in the chip of all levels；

The main control chip sends control signal to downloading notice line, and the first pin for controlling the main control chip is logical Cross the on-off of the communication channel of the chip foundation of Master Communications line and all levels；

The main control chip chooses the core of the promotion levels by chip select line corresponding with the promotion levels chip, piece Piece, and send by the communication channel chip of the upgrade file to the promotion levels.

Optionally, in above-mentioned main control chip, the first pin of the main control chip passes through Master Communications line and all layers The chip of grade is connected, comprising:

First pin of the main control chip is connected by the Master Communications line with the first level chip；

Wherein, the connection type of the level chip in the chip of all levels in addition to the first level chip is: preceding The chip of one level is connected by the Master Communications line with the chip of latter level.

Optionally, in above-mentioned main control chip, the second pin of the main control chip passes through downloading notice line and the institute There is the chip of level to be connected, comprising:

The second pin of the main control chip is connected by downloading notice line with the first level chip；

The main control chip is also connected with I/O expansion module, and the I/O expansion module passes through described in downloading notice line and removing Other level chips outside first level chip are connected.

Optionally, in above-mentioned main control chip, the third pin of the main control chip passes through chip select line and all layers The chip of grade is connected, comprising:

The third pin of the main control chip is connected by first order chip select line with the first level chip；

The main control chip is also connected with I/O expansion module, and the I/O expansion module passes through chip select line and removing described first Other level chips outside level chip are connected.

Optionally, in above-mentioned main control chip, the main control chip determines the upgrade file according to the upgrade file The chip of promotion levels for upgrading, comprising:

The main control chip parses the received upgrade file, obtains the filename of the upgrade file Claim；

The main control chip according to the file name of the upgrade file, determine the upgrade file for upgrading upgrading The chip of level.

The application second aspect discloses a kind of chip, comprising: field programmable gate array fpga chip, selector And storage chip；Wherein, the fpga chip is connected with the selector and storage chip respectively, and the selector is deposited with described Chip is stored up to be connected；

The fpga chip is connected by Master Communications line with main control chip, for receiving upgrade file；

The selector is connected by downloading notice line with the main control chip, and the selector is according to the main control chip The control signal issued, establishes the communication passage between the storage chip and the main control chip；

The selector is connected by chip select line with the main control chip, and the selector is issued according to the main control chip Chip selection signal, itself upgrade file is belonged to the storage chip by the communication passage storage.

Optionally, in said chip, the fpga chip is connected by Master Communications line with main control chip, comprising:

If the chip belongs to the first level chip, the fpga chip in the chip passes through Master Communications line and the master Chip is controlled to be connected；

If the chip is not belonging to the first level chip, the fpga chip in the chip by Master Communications line with it is previous Fpga chip in level chip is connected.

Optionally, in said chip, if the chip belongs to the first level chip, the fpga chip in the chip is used for The upgrade file that the main control chip issues is received, and the upgrade file is forwarded to the FPGA in next level chip Chip；

If the chip is not belonging to the first level chip, the fpga chip in the chip is for receiving previous level chip In fpga chip forwarding the upgrade file, and the upgrade file is forwarded to the FPGA core in next level chip Piece.

Optionally, in said chip, if the chip belongs to the first level chip, the selector in the chip leads to respectively It crosses downloading notice line and chip select line is connected with the main control chip；

If the chip is not belonging to the first level chip, the selector in the chip is also connected with I/O expansion module, institute State I/O expansion module pass through respectively downloading notice line and chip select line be connected with the main control chip.

The application third aspect discloses a kind of chip upgrade system, the main control chip as described in above-mentioned any one, with And the chip as described in above-mentioned any one.

Compared with prior art, the application includes following advantages:

This application discloses a kind of main control chip, chip and chip upgrade systems, in chip upgrade provided herein In system, which includes the chip of main control chip and multiple levels, wherein main control chip is used for the chip to multiple levels Upgraded, the chip of each level at least contains a chip, which includes: fpga chip, selector and storage core Piece, wherein the fpga chip in chip is connected with selector and storage chip respectively, and selector is connected with storage chip.Wherein, The connection type of main control chip and the chip of multiple levels are as follows: the first pin of main control chip passes through Master Communications line and all layers Grade chip be connected, second pin by downloading notice line be connected with the chip of all levels, the used chip select line of third pin and The chip of all levels is connected.Main control chip receives upgrade file by the communication port of main control chip, and according to the upgrading File, determine the upgrade file for upgrading promotion levels chip, and then pass through chip select line, piece chooses the core of all levels Piece level chip corresponding with the upgrade file, and it is logical by the connection that main control chip and the promotion levels chip are established Upgrade file is sent to upgrade file level chip, completes the upgrading to the chip in the upgrade file level chip by road.It is logical The chip upgrade system is crossed, realizes the disposably upgrading to all chips in the chip of level corresponding with upgrade file, together When also achieve grading control to electronic equipment so that the control operating process to the chip in different levels in electronic equipment It is more convenient, solve the problems, such as modules scaling difficulty in the electronic equipment containing multiple identical function modules, convenient for containing There is the operation and maintenance of the electronic equipment of multiple identical function modules.

Detailed description of the invention

In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis The attached drawing of offer obtains other attached drawings.

Fig. 1 is a kind of structural schematic diagram of the upgrade-system of chip disclosed in the embodiment of the present application；

Fig. 2 is a kind of flow diagram of the upgrade method of chip disclosed in the embodiment of the present application；

Fig. 3 is a kind of structural schematic diagram of main control chip disclosed in the embodiment of the present application；

Fig. 4 is a kind of structural schematic diagram of chip disclosed in the embodiment of the present application.

Specific embodiment

Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall in the protection scope of this application.

It, can be with except the realizations of functions of the equipments is realized except through an independent electronic equipment in existing technology Large scale electronic equipment is constituted by assembling each independent electronic equipment, each independent electronic equipment is made to cooperate to realize The function of equipment.For example, the equipment of food processing assembly line is exactly by multiple independent electronic equipments in food processing factory What is constituted has the large scale equipment of processed food function.

In an independent electronic equipment, contain multiple functional modules.It wherein, include identical in multiple functional modules The module of function and the module of different function.And by assembling each independent electronic equipment, make each independent electronics Equipment cooperates in the large scale equipment for the functions of the equipments realized, each independent electronic equipment included in the equipment, Equally with multiple functional modules in above-mentioned independent electronic equipment.

Wherein, the module in multiple functional modules contained in above-mentioned electronic equipment is made of different types of chip 's.Therefore, the module of multiple functional modules contained in above-mentioned electronic equipment can also be considered as is assembled by each different chips Made of a kind of chip.In the process upgraded to the chip in each functional module, also correspond to by each not same core The process that the chip in a kind of chip that piece assembles is upgraded.

It should be noted that during upgrading to above-mentioned functional module, as to by each different chipsets During chip in chip made of dress is upgraded, matching between main control chip and each functional module can be passed through It closes, completes the upgrading to each functional module, as, main control chip and the core as made of each different chip assemblings can be passed through Each upgrading to the chip as made of each different chip assemblings is completed in cooperation between piece.Wherein, main control chip with it is each Cooperation between functional module can complete the upgrading to modules in electronic equipment in chip upgrade system.

Wherein, the control chip upgraded for control function module is main control chip, and with the core in functional module The corresponding chip as made of each different chip assemblings of piece, is mainly used for the control by responding main control chip, carries out phase Corresponding upgrading or data forwarding.

It should be noted that may include for controlling each core in the above-mentioned electronic equipment containing multiple functional modules The main control chip of piece upgrading, can not also include the main control chip for controlling each chip upgrade.Certainly, which removes Each chip constitutes outer, wherein the chip is the chip as made of the assembling of each chip, it is also possible to including other function device Part.Be primarily related in the application: to containing multiple functional modules electronic equipment in functional module in each chip, Or by each core in each functional module in the large scale equipment that assembles of electronic equipment containing multiple functional modules Piece, and the main control chip of upgrading control is carried out to above-mentioned each chip.Other component and the application in electronic equipment is without too More associations, just no longer describes one by one.

It should also be noted that, the upgrade method of chip, can be applied to chip system, wherein the chip system is needle To the module in the above-mentioned electronic equipment containing multiple functional modules, the chip system constructed when being upgraded, as, the core Piece system is the chip system constructed when being upgraded for the chip in the above-mentioned electronic equipment containing multiple functional chips. Chip in the chip system is equal to a certain extent in the module in above-mentioned electronic equipment or above-mentioned electronic equipment Chip.

As shown in Figure 1, chip system includes: the chip of main control chip 101 and multiple levels, each level includes at least one A chip.

Main control chip 101 is used for: being upgraded to the chip in the chip of multiple levels.

Wherein, main control chip 101 is connected with the chip 102 of the first level, and main control chip 101 passes through the chip of the first level 102 are connected with the chip 103 of the second level, and main control chip 101 passes through the chip 102 of the first level and the chip of the second level 103 are connected with the chip 104 of third level, and so on, main control chip 101 by the chip of previous level successively with later layer The chip of grade establishes a connection.Wherein, the number of levels of the chip for the level being connected with main control chip 101 can be any Number.

By taking chip system shown in FIG. 1 as an example, which includes: the chip of 3 levels, and each level includes one A chip.

Main control chip 101 is connected by Master Communications line with the chip 102 of the first level.Specifically, main control chip 101 is logical Cross the field programmable gate array (Field-Programmable in Master Communications line and the chip 102 of the first level Gate Array, FPGA) chip is connected, the selector in chip that main control chip 101 passes through Master Communications line and the first level It is connected.

Wherein, the selector in the chip 102 of the first level is connected with storage chip, in the chip 102 in the first level Fpga chip respectively in the chip 102 of the first level selector and storage chip be connected.It should be noted that first layer Chip in the chip 102 of grade is made of fpga chip, selector and storage chip, in the chip 102 of the first level, It can be containing any chip, wherein the chip is the chip being made of fpga chip, selector and storage chip.

Main control chip 101 is connected by downloading notice line with the selector in the chip 102 of the first level, main control chip 101 are also connected by chip select line with the selector in the chip 102 of the first level.

Main control chip 101 is connected by the chip 102 of the first level with the chip 103 of the second level.Specifically, master control core The fpga chip in chip 102 that piece 101 passes through the first level carries out the extension of Master Communications line, so that the chip of the second level 103 being connected by fpga chip in the chip 102 of the first level and main control chip 101.Wherein, the chip of the second level It includes: that the chip 103 of the second level leads to that 103, which are connected by the fpga chips in the chip 102 of the first level with main control chip 101, The fpga chip crossed in the chip 102 of the first level is connected with the fpga chip in the chip 103 of the second level, the second level The fpga chip in chip 102 that chip 103 passes through the first level, is connected with the selector in the chip 103 of the second level.

Wherein, the selector in the chip 103 of the second level is connected with storage chip, in the chip 103 of the second level Fpga chip respectively in the chip 103 of the second level selector and storage chip be connected.It should be noted that the second level Chip 103 in chip be to be made of fpga chip, selector and storage chip.It, can in the chip 103 of second level To contain any chip, wherein the chip is the chip being made of fpga chip, selector and storage chip.

Main control chip 101 expands module by IO, and the connection for establishing the selector in the chip 103 with the second level is closed System.Wherein, main control chip 101 is expanded module by IO and is established, so that downloading notice line and chip select line expand module by IO, builds The connection relationship between selector and main control chip 101 in the chip 103 of vertical second level.

Main control chip 101 is connected by the chip 102 of the first level with the chip 103 of the second level.Specifically, master control core The fpga chip in chip 103 that piece 101 passes through the second level carries out the extension of Master Communications line, so that the chip of third level 104 are connected by the fpga chip in the chip 103 of the second level.Wherein, the chip 103 of the second level passes through the first level Fpga chip in chip is connected with main control chip 101, and therefore, the chip 104 of third level is equivalent to through the second level Chip 103 and the chip of the first level 102 and main control chip 101 establish connection relationship.

Wherein, the chip of the fpga chip in chip that the chip 104 of third level passes through the second level and the first level In fpga chip establish a connection, comprising: the chip 104 of third level passes through the FPGA in the chip 103 of the second level Chip establishes the fpga chip connection relationship in the chip 104 with third level, and the chip 104 of third level passes through the second level Chip 103 in fpga chip, establish the connection relationship with the selector in the chip 104 of third level.

It should be noted that the selector in chip 104 in third level is connected with storage chip, the core of third level Fpga chip in piece 104 respectively in the chip 104 of third level selector and storage chip be connected.There is still a need for explanations It is that the chip in the chip 104 of third level is made of fpga chip, selector and storage chip, third level In chip 103, any chip can be contained, wherein the chip is made of fpga chip, selector and storage chip Chip.

Main control chip 101 expands module by IO, and the connection for establishing the selector in the chip 104 with third level is closed System.Wherein, main control chip 101 expands module by IO, so that the selector in the chip 104 of third level passes through downloading notice Line and chip select line establish a connection with main control chip 101.

It should be noted that when the selector and main control chip 101 that are not belonging in the chip 102 of the first level pass through downloading It when notice line and chip select line establish connection, needs to expand module by IO, wherein IO expansion module is equivalent to provide to expand and connect Mouthful, the interface can be used for the selector in the chip 103 of the second level or the selector in the chip 104 of third level with Main control chip 101 establishes communication passage.Wherein, IO expands interface provided by module and is not restricted to for the second level Connection of the selector between main control chip 101 in chip 103 in selector or the chip of third level 104, can be with It is the connection between the selector and main control chip in the chip of any level.

It, can also it should be further noted that the chip connecting with main control chip 101 to be divided into the standard of which level Being divided by the function of the chip and with the order of connection of main control chip 101, it is also possible to artificially to divide.Specifically , the chip 102 of the first level in this chip system is the chip directly to establish a connection with main control chip 101, first Chip in the chip 102 of level belongs to same functional module, as, first in the electronic equipment upgraded The function of chip in the chip 102 of level is identical.Contain multiple independent chips in the chip 102 of first level, it is each Chip is identical in addition to function, and the chip and device in other one standalone feature chips of composition are also identical.

It still needs to further illustrate, the chip for being divided into same level in the electronic equipment upgraded, The functional module of the chip functions ownership of the chip is also possible to different.That is, in addition to can be in the electronic equipment The chip for belonging to same function is divided into the chip of the first level, the core for belonging to same function another in the electronic equipment Piece is divided into except the chip of other levels, it is of course also possible to be divided into several layers the identical chip of same function is belonged to The chip of grade.

When the chip for wanting one of the chip in the electronic equipment to a variety of different function types identical function carries out When upgrading, then need to carry out level division to the chip in the electronic equipment.Wherein, when the level of the chip for the upgrading to be divided When dividing more than two layers, main control chip controls to be established between the chip of the storage chip and previous level in the chip of latter level Communication passage.Wherein, the chip of previous level and the chip of latter level belong in the chip of multiple levels except the first level The chip of level except chip.

It needs to be illustrated, main control chip is by extension Master Communications line, so that depositing in the chip of latter level Communication passage is established between storage chip and the chip of previous level.

Wherein, in the chip 103 of the second level and the chip 104 of third level, the chip 102 of the second level relative to The chip 101 of first level just needs to establish storage chip in the chip 102 with the second level by the chip 101 of the first level Communication passage.It is to need to pass through first layer for the link relation between the chip 102 and main control chip 101 of the second level What the chip 102 of grade was established.It can similarly obtain, the link relation between the chip 103 and main control chip 101 of third level will also lead to The chip 103 of the chip 102 and the second level of crossing the first level is established.

Main control chip 101 is connected by downloading notice line with the selector in the chip 102 of the first level, main control chip 101 are also connected by chip select line with the selector in the chip 102 of the first level.Selector in the chip of latter level can be with Module is expanded by IO, is connected by downloading notice line with the selector in the chip of latter level, can similarly pass through piece Route selection is connected with the selector in the chip of latter level.

It is each to the electronic equipment for being able to achieve functions of the equipments above by an independent electronic equipment, or by assembling Independent electronic equipment constitutes large scale equipment to realize the electronic equipment of functions of the equipments, constructs chip upgrade system presented above System, can be used to upgrade the modules in multiple functional modules in above-mentioned electronic equipment.

The chip system provided based on the above embodiment, another embodiment of the application additionally provide a kind of upgrading side of chip Method, referring to FIG. 2, the described method comprises the following steps:

S201, main control chip obtain upgrade file.

Wherein, main control chip is for upgrading the chip of multiple levels, wherein each level includes at least one core Piece.

It should be noted that main control chip can obtain what user submitted by the data transmission interface in main control chip The chip of upgrade file, a certain level which is used to connect main control chip upgrades.

Also it should be further noted that main control chip is to carry out in the chip system for controlling the chip of each level The chip of upgrading.

The communication passage between storage chip in the chip of S202, main control chip foundation and each level.

Wherein, storage chip is the storage chip that program is stored in chip.

It should be noted that the selector in chip of the main control chip by controlling each level, is established and each level Chip in storage chip between communication passage.

Wherein, as shown in connection with fig. 1, main control chip establish and the chip of each level in storage chip between connection Channel, comprising: main control chip issues high level signal to the chip of each level by downloading notice line, and high level signal is enabled The pin for the downloading notice line being connected with selector in the chip of each level, and then control the storage in main control chip and chip The foundation of communication passage between chip.

It should be noted that the signal that main control chip is issued by downloading notice line can may be low electricity for high level It is flat.Above content is pointed out that the downloading for the chip for enabling each level by high level signal notifies wire pin, certainly, The downloading notice wire pin of the chip of each level can be enabled by low level signal.

In example in conjunction with Fig. 1 chip system shown, the specific content as shown in Figure 2 of step S202, comprising:

Main control chip 101 establishes the communication passage with storage chip in the chip 102 of the first level respectively, establishes and second The communication passage of storage chip in the chip 103 of level, the connection for establishing storage chip in the chip 104 with third level are logical Road.

Specifically, main control chip 101 issues high electricity by selector of the downloading notice line into the chip 102 of the first level Ordinary mail number, the pin of the enabled downloading notice line being connected with the selector in the chip 102 of the first level of high level signal.

It should be noted that the selector in chip of the main control chip 101 by controlling each level, establish itself and it is every The communication passage between storage chip in the chip of one level.

Main control chip 101 notifies line by the downloading that the selector in the chip 103 with the second level is connected, to the second layer Selector in the chip 103 of grade issues high level signal, the selection in the enabled chip 103 with the second level of high level signal The pin for the downloading notice line that device is connected, and then the core of the fpga chip and the second level in the chip 102 of the first level of control The foundation of the communication passage between storage chip in piece 103.

Because main control chip 101 by the selector in the chip 102 of enabled first level, is established and first layer The chip 102 of grade establishes communication passage by Master Communications line.So the chip 103 when the second level passes through to the first level Chip 102 in fpga chip carry out the extension of Master Communications line, and main control chip 101 is made to issue enable signal to the second level Chip 103 in selector so that the fpga chip in the chip 103 of the second level and the chip 102 of the first level is established Communication passage is also equivalent to, and main control chip 101 carries out the extension of Master Communications line by the chip 102 to the first level, is established 103 communication passage of chip of main control chip 101 and the second level.

Specifically, main control chip 101 makes master control chip 101 pass through downloading notice line and third by I/O expansion module Selector in the chip 104 of level is connected.Main control chip 101 is connected by the selector in the chip 104 with third level Downloading notify line, the selector into the chip 104 of third level to issue high level signal, high level signal is enabled, with the The pin for the downloading notice line that selector in the chip 104 of three levels is connected, and then in the chip 103 of the second level of control The foundation of the communication passage between storage chip in fpga chip and the chip of third level 104.

Because main control chip 101 by the selector in the chip 103 of enabled second level, is established and first layer The communication passage that the chip 103 of fpga chip and the second level in the chip 102 of grade is established by Master Communications line, so, When the chip 104 of third level carries out the extension of Master Communications line by fpga chip in the chip 103 to the second level, and make Main control chip 101 issues selector of the enable signal into the chip 104 of third level so that the chip 104 of third level with Fpga chip in the chip 103 of second level establishes communication passage, is also equivalent to, and main control chip 101 is by the second layer The chip 102 of grade carries out the extension of Master Communications line, establishes 104 communication passage of chip of main control chip 101 Yu third level.

By examples detailed above it can be seen that main control chip establish and each level chip in storage chip between connection The mode in channel, comprising:

The communication passage between storage chip in the chip of main control chip foundation and the first level；

Main control chip controls that connection is established between the chip of the storage chip and previous level in the chip of latter level is logical Road.

Wherein, the chip of previous level and the chip of latter level belong in the chip of multiple levels the core for removing the first level The chip of level except piece.

The control of S203, chip response main control chip, establish the connection between storage chip and main control chip in chip Channel.

Selector choosing when the pin for the downloading notice line being connected when main control chip is enabled with selector in chip, in chip The connection state for selecting switching Master Communications line and chip, the connection for establishing main control chip between the storage chip of chip are logical Road, the above process can be understood as being that main control chip notifies the chip in each level to prepare upgrading.

In example in conjunction with Fig. 1 chip system shown, the specific content as shown in Figure 2 of step S203, comprising:

The chip 104 of the chip 102 of first level, the chip 103 of the second level and third level responds master control respectively The control of chip 101 is established the communication passage between the storage chip in the chip 102 of the first level and main control chip 101, is built The communication passage between storage chip and main control chip 101 in the chip 103 of vertical second level, and establish third level Communication passage in chip 104 between storage chip and main control chip 101.

Specifically, the selector in the chip 101 of the first level receives high level signal instruction, select Master Communications Line is connect with the storage chip in the chip 102 of the first level, establishes the storage chip in the chip 102 of the first level and master control Communication passage between chip 101.

Specifically, the selector in the chip 103 of the second level receives high level signal instruction, select the first level Chip 102 in fpga chip by Master Communications line extension connect with the storage chip in the chip 103 of the second level, build Storage chip in the chip 103 of vertical second level and the communication passage between the fpga chip in the chip 102 of the first level.

Specifically, the selector in the chip 104 of third level receives high level signal instruction, select the second level Chip 103 in fpga chip by Master Communications line extension connect with the storage chip in the chip 104 of third level, build Storage chip in the chip 104 of vertical third level and the communication passage between the fpga chip in the chip 103 of the second level.

By examples detailed above it can be seen that chip responds the control of main control chip if chip is the chip of the first level, establish The communication passage between storage chip and main control chip in chip, comprising: chip responds the control of the main control chip, establishes The communication passage between storage chip and the main control chip in itself.

If chip is the chip of the level in addition to the chip of the first level in the chip of multiple levels, chip responds master control core The communication passage between storage chip and main control chip in chip is established in the control of piece, comprising: chip responds main control chip Control, establishes the communication passage between the storage chip in itself and the chip of previous level.

S204, main control chip select level corresponding with upgrade file according to upgrade file in the chip of all levels Chip.

Wherein, the chip of all levels includes the chip that each level of communication passage is established with main control chip.

For main control chip according to upgrade file, that is arrived selected in all levels by chip select line is corresponding with upgrade file The chip of level.When main control chip has chosen the chip of level corresponding with upgrade file by chip select line, just mean Be determined that the upgrade file is to be used to the chip of the level for choosing chip select line be upgraded.

It should be noted that main control chip can be according to the file name in upgrade file, by chip select line in all layers The chip of selection level corresponding with upgrade file in the chip of grade.Specifically, main control chip can by chip select line it is enabled with The chip select pin of the corresponding chip of upgrade file selects level corresponding with upgrade file in the chip of currently all level in fact Chip.Optionally, main control chip, can in such a way that chip select line enables the chip select pin of chip corresponding with upgrade file To be the chip select pin for sending chip selection signal to chip by chip select line.

The file name of the file name of upgrade file based on main control chip, the upgrade file can be main control chip By being parsed to upgrade file, the file name of obtained upgrade file.

It still needs to be further illustrated, chip select line is corresponding pass with the relationship of the chip in the chip of each level System, as, the chip in the chip of each level has corresponding chip select line.Main control chip can be by selecting the layer The corresponding chip select line of all chips, chooses the chip of the level in the chip of grade.

In example in conjunction with Fig. 1 chip system shown, step S204 is specific as shown in Fig. 2, main control chip 101 is according to liter Grade file, selection and upgrading in the chip 104 of the chip 102 of the first level, the chip 103 of the second level or third level The detailed process of the chip of the corresponding level of file are as follows:

File name of the main control chip 101 according to upgrade file, by chip select line the first level chip 102, second The chip of level corresponding with upgrade file is selected in the chip 103 of level and the chip 104 of third level.

If upgrade file is upgraded for the chip 101 to the first level, main control chip 101 just passes through first The corresponding chip select line of chip 102 of level sends chip selection signal to the chip 102 of the first level, main control chip 101 is made to choose the The chip of one level.

If upgrade file is upgraded for the chip 103 to the second level, main control chip 101 just passes through second The corresponding chip select line of chip 103 of level sends chip selection signal to the chip 103 of the second level, main control chip 101 is made to choose the The chip 103 of two levels.

If upgrade file is upgraded for the chip 104 to third level, main control chip 101 just passes through third The corresponding chip select line of chip 104 of level sends chip selection signal to the chip 104 of third level, main control chip 101 is made to choose the The chip 104 of three levels.

It should be noted that if main control chip 101 determined the upgrade file be for the chip 102 to the first level into Row upgrading, then main control chip 101 just sends chip selection signal by the corresponding chip select line of chip 102 of the first level, selection the The chip 102 of one level.If the chip 103 of the second level, then main control chip 101 is corresponding by the chip 103 of the second level Chip select line send chip selection signal, select the second level the corresponding chip select line of chip 103, and so on, if other levels Chip, the corresponding chip select line of chip that main control chip just passes through other levels sends chip selection signal, selection and upgrade file pair The chip for other levels answered.

It can be seen that in one embodiment, main control chip 101 can determine whether out the corresponding level chip of upgrade file, Chip selection signal is sent to the chip select pin of chip using the corresponding chip select line of level chip determined, with real currently all level Chip in corresponding with the upgrade file level of selection chip.

In addition, in another embodiment, main control chip 101 can also send different types of choosing letter by chip select line Number, to determine the corresponding relationship of upgrade file and all level chips.

Specifically, main control chip 101 determines the corresponding level chip of upgrade file, it is corresponding using determining level chip Chip select line sends the chip selection signal of the first kind, such as high level letter to the chip select pin of the corresponding level chip of upgrade file Number；The layer that main control chip 101 is connected using the corresponding chip select line of level chip in addition to determining level chip to chip select line The chip select pin of grade chip, sends the chip selection signal of Second Type, such as low level signal.

S205, chip response main control chip for upgrade file selection level chip control operation, determine chip with The relationship of upgrade file.

It should be noted that control operation of the chip response main control chip for the selection level chip of upgrade file, really Determine the relationship of chip and upgrade file.It executes, it is intended that chip can respond main control chip according to upgrade file, in all levels Chip in corresponding with the upgrade file level of selection chip operation, determine the relationship of itself and upgrade file.

It should also be noted that, control operation of the chip response main control chip for the selection level chip of upgrade file, Determine that the mode of the relationship of chip and upgrade file can be with are as follows: receive the chip selection signal that main control chip is issued by chip select line, really The relationship of fixed itself and upgrade file.

In example in conjunction with Fig. 1 chip system shown, step S205 specifically:

The chip select pin of the chip 101 of first level receives, and the chip 102 of main control chip 101 to the first level is corresponding The chip selection signal that chip select line is sent, determines the chip 102 of the first level and the relationship of upgrade file.

The chip select pin of the chip 103 of second level receives, and the chip 103 of main control chip 101 to the second level is corresponding The chip selection signal that chip select line is sent, determines the chip 103 of the second level and the relationship of upgrade file.

The chip select pin of the chip 104 of third level receives, and the chip 104 of main control chip 101 to third level is corresponding The chip selection signal that chip select line is sent, determines the chip 104 of third level and the relationship of upgrade file.

Specifically, chip judges that chip select pin receives the chip selection signal that chip select line issues, then in a kind of embodiment It determines itself to belong to the corresponding chip of upgrade file.Chip judges that chip select pin does not receive the piece choosing letter that chip select line issues Number, it is determined that go out and itself is not belonging to the corresponding chip of upgrade file.

Certainly, in another embodiment, the class for the chip selection signal that chip is issued according to the received chip select line of chip select pin Type, to determine the relationship of itself and upgrade file.Specifically, chip identifies that the chip selection signal that chip select line issues is the first kind Signal, it is determined that itself belong to the corresponding chip of upgrade file；Chip identifies that the chip selection signal that chip select line issues is second The signal of type, it is determined that itself be not belonging to the corresponding chip of upgrade file.

S206, main control chip pass through communication passage, the chip of transmission upgrade file to each level.

It should be noted that main control chip is logical by the connection established with the storage chip in the chip of each level Road issues upgrade file to the storage chip in the chip of each level.

In example in conjunction with Fig. 1 chip system shown, the specific content as shown in Figure 2 of step S206, comprising:

The chip 103 with the chip 102 of the first level, the second level that main control chip 101 is established by step S202 And the communication passage of the storage chip in the chip 104 of third level, upgrade file is sent into the chip 102 of the first level Storage chip, send upgrade file to the storage chip in the chip 103 of the second level, and send upgrade file to third Storage chip in the chip 104 of level.

S207, chip judge the relationship of itself and upgrade file.

Wherein, after chip receives upgrade file, it is thus necessary to determine that the relationship of itself and upgrade file.Specifically, chip can To pass through the received chip selection signal of chip select line, to determine the relationship of itself and upgrade file.

Chip itself and the relationship of upgrade file include: the chip that chip belongs to the corresponding level of upgrade file and chip not Belong to the chip of the corresponding level of upgrade file.When upgrade file is for upgrading to chip itself, chip itself with The relationship of upgrade file are as follows: chip belongs to the chip of the corresponding level of upgrade file.When upgrade file is not intended to chip certainly When body is upgraded, the relationship of chip itself and upgrading text are as follows: chip is not belonging to the chip of the corresponding level of upgrade file.

In example in conjunction with Fig. 1 chip system shown, setting upgrade file belongs to the corresponding liter of chip of the second level Grade file, then in this example, the judging result of step S207 is specifically as shown in Figure 2:

The chip 102 of first level judges the relationship of itself and upgrade file are as follows: the chip 102 of the first level is not belonging to rise The chip of the grade corresponding level of file.The chip 103 of second level judges the relationship of itself and upgrade file are as follows: the second level Chip 103 belongs to the chip of the corresponding level of upgrade file.The chip 104 of third level judges the relationship of itself and upgrade file Are as follows: the chip 104 of third level is not belonging to the chip of the corresponding level of upgrade file.

It should be noted relationship of the chip according to itself and upgrade file, Lai Zhihang step S208.

S208, chip ignore upgrade file or receive and store upgrade file.

Wherein, when chip judges the relationship of itself and upgrade file are as follows: chip is not belonging to the corresponding level of upgrade file Chip, then chip ignores upgrade file.When chip judges the relationship of itself and upgrade file are as follows: it is opposite that chip belongs to upgrade file The chip of level is answered, then chip receives and stores upgrade file.

It should also be noted that, then chip receives upgrading text when chip belongs to the chip of the corresponding level of upgrade file Part is simultaneously upgrade file storage chip stored in the chip.

It is still to be illustrated, the mode that chip ignores upgrade file, which can be, first to be received the upgrade file and delete again The upgrade file is also possible to first receive the upgrade file and stores storage chip of the upgrade file into chip, can be with It is that chip neither receives upgrade file nor stores the upgrade file, certainly, chip can also not make upgrade file any Reaction movement.

In example in conjunction with Fig. 1 chip system shown, the specific content as shown in Figure 2 of step S208, comprising:

The chip 102 of first level ignores upgrade file.

It should be noted that the mode that the chip 102 of the first level ignores upgrade file can be with are as follows: the chip of the first level 102 reception the upgrade file after delete the upgrade file.

The chip 103 of second level receives and stores upgrade file.

It should be noted that the chip 103 of the second level receives upgrade file, and upgrade file is stored in the second level Chip 103 in storage chip.

The chip 104 of third level ignores upgrade file.

Similarly, the chip 104 of third level ignores the mode of upgrade file and may be: the chip 104 of third level is first The upgrade file is deleted after receiving the upgrade file.

By examples detailed above it can be seen that chip passes through the relationship of itself and the upgrade file, receives main control chip and issue The upgrade file.

Specifically, chip is determined itself to belong to the corresponding chip of upgrade file, then the upgrading that main control chip issues is received File, and the upgrade file is written to itself storage chip.Chip determines itself to be not belonging to the corresponding chip of upgrade file, The upgrade file is deleted again after then can receive the upgrade file that main control chip issues.

It should be noted that from step S206 to the content of step S208: main control chip is incited somebody to action by communication passage Upgrade file is written to the storage chip in the chip of level corresponding with the upgrade file.

It should also be noted that, upgrade file is written in the chip of the corresponding level of the upgrade file by main control chip After storage chip, main control chip can discharge the chip select pin of chip, i.e. main control chip is not passing through piece of the chip select line to chip Pin is selected to send chip selection signal.

Optionally, main control chip can also discharge selector in the chip of each level and connect again by downloading notice line Downloading notice line pin, with realize notify the chip upgrade of each level to terminate.Certainly, main control chip can use and pass through The pin for the downloading notice line that downloading notice line selector into the chip of each level connects sends the mode of release signal, real Now to the release of pin.

After the chip of each level receives the release signal again, then download communication line can be disconnected by selector and is deposited Store up the communication passage between chip.

The upgrade method for the chip that the present embodiment is shown is carried out by three-level of the number of levels of the chip in chip system It shows.It is right referring again to above-mentioned method when the chip number of levels in the chip system upgraded is more than three-level The chip of each level is upgraded in chip system.No matter in chip system the level of chip quantity, upgrade method with it is upper It states shown method and has no the similarities and differences, just no longer repeat one by one.

The upgrade method of chip provided in this embodiment is selected in the chip of all levels and upgrading by main control chip The chip of the corresponding level of file, and upgrade file is issued to level corresponding with upgrade file by established communication passage Chip in, wherein the communication passage established are as follows: main control chip establish and each level chip in storage chip between Communication passage, realize the disposably upgrading to all chips in the chip of level corresponding with upgrade file, while also real The grading control to electronic equipment is showed, so that more just to the control operating process of the chip in different levels in electronic equipment Victory solves the problems, such as modules scaling difficulty in the electronic equipment containing multiple identical function modules, convenient for containing multiple The operation and maintenance of the equipment of function equal modules.

The embodiment of the present application provides a kind of main control chip, and the main control chip is for rising the chip of multiple levels Grade, wherein each level includes at least one chip, refers to Fig. 3, the main control chip, comprising:

The communication port 301 of main control chip, the communication port 301 is for receiving upgrade file.

It should be noted that the communication port 301 of main control chip can be USB port or the master control on main control chip With the port of data-transformation facility in chip, for example, serial ports, parallel port on main control chip.

User passes through the communication port 301 of the main control chip, can transmit data to the main control chip, wherein with regard to being passed Defeated data include: the upgrade file for being upgraded to each level chip.

First pin 302 of main control chip is connected by Master Communications line with the chip of all levels, and second pin 303 is logical It crosses downloading notice line to be connected with the chip of all levels, third pin 304 is connected by chip select line with the chip of all levels.

It should be noted that main control chip inherently carries pin.The pin can pass through connecting line and each level core Piece is connected, or is connected with other components, for realizing the data interaction between main control chip and each level chip, or Realize the data interaction between main control chip and other components.

It should be noted that the pin of main control chip, can be according to master control in such a way that connecting line is connected with the external world The type for needing to carry out data interaction between chip and the external world, determines the pin of main control chip passes through which kind of connecting line and extraneous phase Even.Specifically, can choose any one pin in main control chip if main control chip is want to communicate with external world's realization, passing through The connection type of communication line, is attached with the external world；If main control chip is wanted to control some component, so that it may which selection has The connecting line of transmission of control signals, make the pin of master control chip and the component that needs to receive transmission of control signals port or Person's pin is connected.

It still needs to it is noted that the first pin 302 of main control chip passes through the chip phase of Master Communications line and all levels Even, which can be carried out data transmission by the Master Communications line, the chip of Xiang Suoyou level, wherein just including transmission Upgrade file.The second pin 303 of main control chip is connected by downloading notice line with the chip of all levels, which can With by downloading notice line, the chip of Xiang Suoyou level sends downloading notification signal, wherein the downloading notification signal just includes: High level signal and low level signal.The third pin 304 of main control chip is connected by chip select line with the chip of all levels, should Main control chip can send chip selection signal by chip select line, the chip of Xiang Suoyou level.

It should be noted that the second pin 303 of main control chip and the third pin 304 of main control chip can be master control core The same pin of piece, the pin can be connected by downloading notice line and chip select line with the chip of each level, the pin Effect to the chip of all levels is: sending control signal to all level chips by main control chip, controls all levels Chip in chip according to it is described control signal response main control chip movement.

Main control chip according to upgrade file, determine upgrade file for upgrading promotion levels chip.Wherein, promotion levels Chip are as follows: the level chip corresponding with upgrade file in the chip of all levels.

It should be noted that main control chip according to upgrade file, determine upgrade file for upgrading the side for upgrading chip Formula can be with are as follows: main control chip parses upgrade file, obtains the file name of upgrade file, main control chip is according to the upgrading The file name of file, determine upgrade file for upgrading promotion levels chip.

Main control chip sends control signal to downloading notice line, and the first pin for controlling main control chip passes through Master Communications line The on-off for the communication channel established with the chip of all levels.

It should be noted that main control chip sends downloading notification signal to downloading notice line, the first of main control chip is controlled The communication channel connection that pin is established by Master Communications line and the chip of all levels.

Main control chip is by chip select line corresponding with promotion levels chip, and piece chooses the chip of promotion levels, and by logical Believe that channel sends the chip of upgrade file to the promotion levels.

It should be noted that each chip in each level chip, is connected by chip select line with main control chip, master control If chip is wanted to choose chip, the chip select pin of the chip is enabled by the chip select line being connected with the chip, so that it may which piece is chosen The chip.Main control chip is to disposably select all chips in a level, then by enabling each chip in the level Enabled pin, so that it may piece chooses all chips of the level.

The purpose that piece chooses the chip of promotion levels is, enables the promotion levels chip, the chip of the level is notified to connect It receives upgrade file and stores storage chip of the upgrade file into the chip of the promotion levels.Wherein, main control chip, which is sent, rises The mode of grade file is: being established by the chip of the promotion levels and the first pin of main control chip by Master Communications line Communication passage completes transmission.

In the present embodiment, main control chip receives upgrade file by the communication port of main control chip, and according to the liter Grade file, determine the upgrade file for upgrading promotion levels chip, and then pass through chip select line, piece chooses all levels Chip level chip corresponding with the upgrade file, and the connection established by main control chip and the promotion levels chip Upgrade file is sent to upgrade file level chip, completes the upgrading to the chip in promotion levels chip by channel.Pass through master The chip upgrade system that control chip and the chip of all levels are constituted, is realized disposably to level corresponding with upgrade file The upgrading of all chips in chip, while the grading control to electronic equipment is also achieved, so as to different in electronic equipment The control operating process of chip in level is more convenient, solves each in the electronic equipment containing multiple identical function modules The problem of module upgrade difficulty, convenient for the operation and maintenance of the electronic equipment containing multiple identical function modules.

The upgrade method for the chip that the course of work and above method embodiment of main control chip disclosed in the present embodiment provide Identical, reference can be made to above method embodiment, details are not described herein again.

Optionally, in another embodiment of the application, the first pin of the main control chip by Master Communications line with The chip of all levels is connected, comprising:

First pin of main control chip is connected by Master Communications line with the first level chip.

Wherein, the connection type of the level chip in the chip of all levels in addition to the first level chip is: preceding layer The chip of grade is connected by the Master Communications line with the chip of latter level.

Specifically, the first pin of main control chip passes through Master Communications line and the fpga chip phase in the first level chip Even.

Specifically, referring to Figure 1, main control chip passes through by taking the chip upgrade system containing the chip there are three level as an example Master Communications line is connected with the first level chip, and the first level chip is connected with the second level chip by Master Communications line It connects, the second level chip is connect with third level chip by Master Communications line.

Optionally, in another embodiment of the application, the second pin of the main control chip by downloading notice line with The chip of all levels is connected, comprising:

The second pin of main control chip is connected by downloading notice line with the first level chip.

Main control chip is also connected with I/O expansion module, and the I/O expansion module is by downloading notice line and removes the first level Other level chips outside chip are connected.

Specifically, the second pin of main control chip is connected by downloading notice line with the selector in the first level chip.

Main control chip is also connected with I/O expansion module, and the I/O expansion module is by downloading notice line and removes the first level Other level chips outside chip are connected.Specifically, the I/O expansion module is by downloading notice line and removes first layer Selector connection in other level chips outside grade chip.

Equally by taking the chip upgrade system containing the chip there are three level as an example, referring to FIG. 1, main control chip and I/O expansion Module is connected by downloading notice line, and I/O expansion module is connected by downloading notice line with the selector in the second level chip It connects, I/O expansion module is connected by downloading notice line with the selector in third level chip.

Present invention also provides a kind of chip, which can constitute chip upgrade system, the chip upgrade with main control chip System can be used for upgrading chip itself, refer to Fig. 4, and the chip includes: field programmable gate array FPGA Chip 401, selector 402 and storage chip 403；Wherein, the fpga chip 401 respectively with the selector 402 and storage Chip 403 is connected, and the selector 402 is connected with the storage chip 403；

The fpga chip 401 is connected by Master Communications line with main control chip, for receiving upgrade file；

The selector 402 is connected by downloading notice line with the main control chip, and the selector 402 is according to the master The control signal that control chip issues, establishes the communication passage between the storage chip 403 and the main control chip；

The selector 402 is connected by chip select line with the main control chip, and the selector 402 is according to the master control core The chip selection signal that piece issues belongs to itself upgrade file to the storage chip 403 by the communication passage storage.

It should be noted that each chip is made of fpga chip 401, selector 402 and storage chip 403, it should Storage chip 403 in chip is for storing the upgrade procedure upgraded to the fpga chip 401 of itself, fpga chip 401 The upgrade procedure being stored in storage chip 403 can be read automatically, for automatically updating the programming system of itself to complete pair The upgrading of itself.

Selector 402 is used to control chip according to the control received according to the control signal for receiving main control chip transmission Signal processed makes corresponding response action.Specifically, selector 402 is notified according to the downloading that received main control chip issues Signal controls the storage chip 403 and main control chip in chip when received downloading notification signal is high level signal Between communication passage connection.According to the chip selection signal received, the storage chip 403 controlled in chip passes through selector 402 The communication passage that storage chip itself and main control chip are established, storage belong to the upgrade file of itself into storage chip 403.

The course of work of chip disclosed in the present embodiment is identical as the upgrade method for the chip that above method embodiment provides, It can be found in above method embodiment, details are not described herein again.

Optionally, in another embodiment of the application, the fpga chip passes through Master Communications line and main control chip phase Even, comprising:

It should be noted that if chip belongs to the first level chip, the fpga chip in chip by Master Communications line with Main control chip is connected directly；If chip is not belonging to the first level chip, the fpga chip in chip is by Master Communications line with before Fpga chip in one level chip is connected.

It is by taking the chip upgrade system containing the chip there are three level as an example specifically, same referring to FIG. 1, the first level core Fpga chip in piece is connected directly by Master Communications line with main control chip, and the fpga chip in the second level chip passes through master Control communication line is connected with the fpga chip in the first level chip, and the fpga chip in third level chip passes through Master Communications Line is connected with the fpga chip in the second level chip.

Optionally, in another embodiment of the application, if the chip belongs to the first level chip, in the chip The upgrade file is forwarded to next level for receiving the upgrade file that the main control chip issues by fpga chip Fpga chip in chip；

It should be noted that then the fpga chip in the chip is for connecing when chip belongs to the last one level chip Receive the upgrade file of the fpga chip forwarding in previous level chip.

Optionally, in another embodiment of the application, if the chip belongs to the first level chip, in the chip Selector passes through downloading notice line respectively and chip select line is connected with the main control chip；

It should be noted that the pin that downloading notice line and chip select line are connect with selector can be the same pin, Selector control signal according to received by the pin, control chip respond main control chip.Wherein, received by the selector Control signal be downloading notification signal, then control the communication passage connection between the storage chip and main control chip in chip. The control signal received by the selector is chip selection signal, then controls the storage chip storage upgrade file in chip.

In the present embodiment, the chip upgrade system being made up of chip and main control chip, realize disposably to liter The upgrading of all chips in the chip of the grade corresponding level of file, while the grading control to electronic equipment is also achieved, make It is more convenient to the control operating process of the chip in different levels in electronic equipment to obtain, and solves containing multiple identical function moulds In the electronic equipment of block the problem of modules scaling difficulty, convenient for the use of the electronic equipment containing multiple identical function modules And maintenance.

Present invention also provides a kind of chip upgrade systems, upgrade for the chip to multiple levels, the chip Upgrade-system includes: main control chip and chip as described above.The escalation process of chip upgrade system can be found in above-mentioned show The course of work of main control chip and chip, just no longer repeats one by one.

The chip upgrade system being made up of the chip of main control chip and all levels is realized disposably to literary with upgrading The upgrading of all chips in the chip of the corresponding level of part, while the grading control to electronic equipment is also achieved, so that right The control operating process of chip in electronic equipment in different levels is more convenient, solves containing multiple identical function modules In electronic equipment the problem of modules scaling difficulty, using and tieing up convenient for the electronic equipment containing multiple identical function modules Shield.

The upgrading for the chip that the course of work of chip upgrade system disclosed in the present embodiment and above method embodiment provide Method is identical, reference can be made to above method embodiment, details are not described herein again.

All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.Especially for system or For system embodiment, since it is substantially similar to the method embodiment, so describing fairly simple, related place is referring to method The part of embodiment illustrates.System and system embodiment described above is only schematical, wherein the conduct The unit of separate part description may or may not be physically separated, component shown as a unit can be or Person may not be physical unit, it can and it is in one place, or may be distributed over multiple network units.It can root According to actual need that some or all of the modules therein is selected to achieve the purpose of the solution of this embodiment.Ordinary skill Personnel can understand and implement without creative efforts.

Professional further appreciates that, unit described in conjunction with the examples disclosed in the embodiments of the present disclosure And algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware and The interchangeability of software generally describes each exemplary composition and step according to function in the above description.These Function is implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Profession Technical staff can use different methods to achieve the described function each specific application, but this realization is not answered Think beyond scope of the present application.

The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one The widest scope of cause.

It should also be noted that, herein, relational terms such as first and second and the like are used merely to one Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain Lid non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including the element.

Claims

1. a kind of main control chip, which is characterized in that the main control chip is for upgrading the chip of multiple levels, wherein Each level includes at least one chip, and the main control chip includes:

First pin of the main control chip is connected by Master Communications line with the chip of all levels, and second pin passes through downloading Notice line is connected with the chip of all levels, and third pin is connected by chip select line with the chip of all levels；

The main control chip according to the upgrade file, determine the upgrade file for upgrading promotion levels chip；Wherein, The promotion levels chip are as follows: the level chip corresponding with the upgrade file in the chip of all levels；

The main control chip sends control signal to downloading notice line, and the first pin for controlling the main control chip passes through master Control the on-off of the communication channel of the chip foundation of communication line and all levels；

The main control chip chooses the chip of the promotion levels by chip select line corresponding with the promotion levels chip, piece, And the chip of the upgrade file to the promotion levels is sent by the communication channel.

2. main control chip according to claim 1, which is characterized in that the first pin of the main control chip is logical by master control Letter line is connected with the chip of all levels, comprising:

3. main control chip according to claim 1, which is characterized in that the second pin of the main control chip is logical by downloading Know that line and the chip of all levels are connected, comprising:

The main control chip is also connected with I/O expansion module, and the I/O expansion module passes through downloading notice line and removing described first Other level chips outside level chip are connected.

4. main control chip according to claim 1, which is characterized in that the third pin of the main control chip passes through chip select line It is connected with the chip of all levels, comprising:

The main control chip is also connected with I/O expansion module, and the I/O expansion module is by chip select line and removes first level Other level chips outside chip are connected.

5. main control chip according to claim 1, which is characterized in that the main control chip is according to the upgrade file, really The chip of promotion levels of the fixed upgrade file for upgrading, comprising:

The main control chip parses the received upgrade file, obtains the file name of the upgrade file；

The main control chip according to the file name of the upgrade file, determine the upgrade file for upgrading promotion levels Chip.

6. a kind of chip characterized by comprising field programmable gate array fpga chip, selector and storage chip； Wherein, the fpga chip is connected with the selector and storage chip respectively, and the selector is connected with the storage chip；

The selector is connected by downloading notice line with the main control chip, and the selector is issued according to the main control chip Control signal, establish the communication passage between the storage chip and the main control chip；

The selector is connected by chip select line with the main control chip, the piece that the selector is issued according to the main control chip Signal is selected, itself upgrade file is belonged to the storage chip by the communication passage storage.

7. chip according to claim 6, which is characterized in that the fpga chip passes through Master Communications line and main control chip It is connected, comprising:

If the chip belongs to the first level chip, the fpga chip in the chip passes through Master Communications line and the master control core Piece is connected；

If the chip is not belonging to the first level chip, the fpga chip in the chip passes through Master Communications line and previous level Fpga chip in chip is connected.

8. chip according to claim 7, which is characterized in that if the chip belongs to the first level chip, the chip In fpga chip for receiving the upgrade file that the main control chip issues, and the upgrade file is forwarded to next Fpga chip in level chip；

If the chip is not belonging to the first level chip, the fpga chip in the chip is for receiving in previous level chip The upgrade file of fpga chip forwarding, and the upgrade file is forwarded to the fpga chip in next level chip.

9. chip according to claim 6, which is characterized in that if the chip belongs to the first level chip, the chip In selector pass through respectively downloading notice line and chip select line be connected with the main control chip；

If the chip is not belonging to the first level chip, the selector in the chip is also connected with I/O expansion module, the IO Expansion module passes through downloading notice line respectively and chip select line is connected with the main control chip.

10. a kind of chip upgrade system characterized by comprising the main control chip as described in claim 1 to 5 any one, And the chip as described in claim 6 to 9 any one.