CN113596818B - Method, system and computer readable storage medium for upgrading over-the-air technology - Google Patents

Method, system and computer readable storage medium for upgrading over-the-air technology Download PDF

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Publication number
CN113596818B
CN113596818B CN202110920684.7A CN202110920684A CN113596818B CN 113596818 B CN113596818 B CN 113596818B CN 202110920684 A CN202110920684 A CN 202110920684A CN 113596818 B CN113596818 B CN 113596818B
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chip
upgrade
mode
upgrading
communication module
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CN113596818A (en
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郑凯
黄泽洋
郑龙
李冬
姜豪
刘风雷
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Zhejiang Crystal Optech Co Ltd
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Zhejiang Crystal Optech Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W8/00—Network data management
    • H04W8/22—Processing or transfer of terminal data, e.g. status or physical capabilities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W8/00—Network data management
    • H04W8/22—Processing or transfer of terminal data, e.g. status or physical capabilities
    • H04W8/24—Transfer of terminal data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W8/00—Network data management
    • H04W8/22—Processing or transfer of terminal data, e.g. status or physical capabilities
    • H04W8/24—Transfer of terminal data
    • H04W8/245—Transfer of terminal data from a network towards a terminal

Abstract

The application provides an over-the-air technology upgrading method, a system and a computer readable storage medium, comprising the following steps: the communication module receives the upgrade firmware sent by the server and determines a target chip to be upgraded according to the upgrade sequence of each chip; the communication module sends an upgrade starting instruction to the first chip, and each chip sequentially sends the upgrade starting instruction to the following chip by taking the first chip as the start, if the chip which receives the upgrade starting instruction is the target chip, the target chip adjusts the chip mode into an upgrade mode, and other chips except the target chip adjust the chip mode into a transparent transmission mode or a dormant mode; the communication module sends the upgrade firmware to the first chip; starting from the first chip, each chip sequentially receives the upgrade firmware, and executes upgrade operation or data transparent transmission according to the current respective chip mode. Through the steps, the phenomenon that one chip on one side has errors to affect other chip upgrades in multi-chip upgrades can be avoided, and the reliability of OTA upgrade of equipment is improved.

Description

Method, system and computer readable storage medium for upgrading over-the-air technology
Technical Field
The present application relates to the field of chip technologies, and in particular, to an over-the-air technology upgrade method, system, and computer readable storage medium.
Background
With the continuous development of computer communication technology and semiconductor technology, various existing electronic devices are more and more complex, and a plurality of chips are often integrated in the electronic devices, so that firmware upgrade is generally required to repair the encountered problems and add new functions. In the prior art, an Over-the-Air Technology (OTA) is generally used to upgrade firmware, and the OTA is a manner of transmitting and upgrading firmware through an Over-the-Air wireless network, that is, the OTA is a manner of remote upgrade, specifically, the chip on the OTA remote upgrade device is used, which may mean that the upgrade firmware is downloaded from a server through a communication module and transmitted to the chip, so as to complete the process of upgrading the chip.
In the prior art, when equipment integrating a plurality of chips upgrades a plurality of chips simultaneously, the upgrading sequence of each chip is not formulated, and after errors occur in the upgrading process of one side chip, the upgrading of other side chips can be influenced, so that the upgraded equipment is abnormal.
Disclosure of Invention
In view of the foregoing, an object of the present application is to provide an over-the-air technology upgrading method, system and computer readable storage medium, so as to solve the problem in the prior art that when a device integrating multiple chips upgrades multiple chips simultaneously, the device is abnormal due to disorder of chip upgrade.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, an embodiment of the present application provides an over-the-air technology upgrading method, which is applied to an over-the-air technology upgrading system, where the upgrading system includes an electronic device to be upgraded and a communication module, the electronic device includes a plurality of chips, and a first chip in each chip is connected with the communication module, and the method includes:
the communication module receives the upgrade firmware sent by the server, and determines a current target chip to be upgraded according to the upgrade sequence of each chip, wherein the upgrade sequence of each chip is determined according to the arrangement sequence of each chip;
the communication module sends an upgrade starting instruction to the first chip, wherein the upgrade starting instruction comprises the identification of the target chip;
Starting with the first chip, each chip sequentially sends the start-upgrading instruction to the following chips, if the chip receiving the start-upgrading instruction is the target chip, the target chip adjusts the current chip mode to be an upgrading mode, and other chips except the target chip adjust the respective chip modes to be a transparent mode or a dormant mode;
the communication module sends the upgrade firmware to the first chip;
and starting from the first chip, each chip sequentially receives the upgrade firmware and executes upgrade operation or data transparent transmission according to the current respective chip mode.
As one possible implementation manner, the other chips than the target chip adjust their respective chip modes to a transparent transmission mode or a sleep mode, including:
and if the upgrading state of the second chip in the other chips is upgraded, the second chip adjusts the chip mode of the second chip to be a dormant mode, wherein the second chip is any one of the other chips.
As one possible implementation manner, the other chips than the target chip adjust their respective chip modes to a transparent transmission mode or a sleep mode, including:
And if the upgrading state of the third chip in the other chips is not upgraded, the third chip adjusts the chip mode of the third chip to be a transparent transmission mode, wherein the third chip is any one of the other chips.
As a possible implementation manner, the chips perform upgrade operations or data transparent transmission according to the current respective chip modes, including:
the target chip uses the upgrade firmware to execute upgrade operation in the upgrade mode;
and transmitting the updated firmware to the following chips connected with the chips in the transparent transmission mode.
As a possible implementation manner, the method further includes:
if the target chip finishes the upgrading operation, the target chip exits the upgrading mode and sends an upgrading completion response to other chips except the target chip.
As a possible implementation manner, the method further includes:
and after receiving the upgrade completion response, a third chip in the other chips adjusts the current chip mode to an initial state.
As a possible implementation manner, the communication module receives the upgrade firmware sent by the server, including:
The communication module sends a preparation upgrading instruction to the first chip;
the first chip determines whether each chip meets preset upgrading conditions according to the upgrading preparation instruction, and if yes, sends an upgrading preparation completion response to the communication module;
and the communication module reads the upgrade firmware from the server according to the upgrade preparation completion response.
As a possible implementation manner, before determining the current target chip to be upgraded according to the upgrading sequence of each chip, the method further includes:
and reading the upgrading sequence of each chip from the server, wherein the upgrading sequence of each chip is obtained by the fact that a user sets the upgrading sequence on the server in advance according to the arrangement sequence of each chip.
In a second aspect, an embodiment of the present application further provides an over-the-air technology upgrade system, where the system includes:
the electronic equipment to be upgraded comprises a plurality of chips, wherein a first chip in each chip is connected with the communication module, and the electronic equipment and each chip in the electronic equipment respectively execute the steps of the over-the-air technology upgrading method according to the first aspect.
In a third aspect, embodiments of the present application further provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the over-the-air technology upgrade method as described in the first aspect above.
The beneficial effects of this application are:
the method, the system and the computer readable storage medium for upgrading the air downloading technology provided by the embodiment of the application, wherein the communication module receives upgrading firmware sent by the server and determines a target chip to be upgraded currently according to the upgrading sequence of each chip, wherein the upgrading sequence of each chip is determined according to the arrangement sequence of each chip; the communication module sends an upgrade starting instruction to the first chip, wherein the upgrade starting instruction comprises the identification of the target chip; starting from a first chip, each chip sequentially sends an upgrade starting instruction to a subsequent chip, if the chip which receives the upgrade starting instruction is a target chip, the target chip adjusts the current chip mode to be an upgrade mode, and other chips outside the target chip adjust the respective chip modes to be a transparent transmission mode or a dormant mode; the communication module sends the upgrade firmware to the first chip; starting from the first chip, each chip sequentially receives the upgrade firmware, and executes upgrade operation or data transparent transmission according to the current respective chip mode. In the step, before upgrading, the upgrading sequence of each chip is preset according to the arrangement sequence of each chip, in the upgrading process, the chips can be upgraded according to the preset upgrading sequence, in the upgrading process, each chip can enter a corresponding chip mode according to the state of the chip, the problem that in the multi-chip upgrading process, after errors occur in the upgrading process, the chips on the other sides can be influenced, and then the equipment after upgrading is abnormal is caused, the reliability of OTA upgrading of the electronic equipment is improved, and the accuracy and efficiency of firmware updating of the electronic equipment are improved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an OTA upgrading system provided in an embodiment of the present application;
fig. 2 is a flow chart of an OTA upgrading method provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of another OTA upgrading system according to an embodiment of the present application;
fig. 4 is a flow chart of another OTA upgrading method according to an embodiment of the present disclosure;
fig. 5 is a flow chart of another OTA upgrading method according to an embodiment of the present disclosure;
fig. 6 is a flowchart of another OTA upgrading method according to an embodiment of the present application;
fig. 7 is a flowchart of another OTA upgrading method according to an embodiment of the present application;
Fig. 8 is a flowchart of another OTA upgrading method according to an embodiment of the present application.
Icon: a 101-electronic device; 102-a communication module; 103-a plurality of chips; 104-first chip.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the accompanying drawings in the present application are only for the purpose of illustration and description, and are not intended to limit the protection scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this application, illustrates operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one or more other operations may be added to the flow diagrams and one or more operations may be removed from the flow diagrams as directed by those skilled in the art.
In addition, the described embodiments are only some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features stated hereinafter, but not to exclude the addition of other features.
With the continuous development and maturation of OTA, when firmware upgrade and repair are required for many electronic devices, or new functions are required to be added, an OTA remote upgrade mode is generally adopted, specifically, the device downloads the upgrade firmware from a server through a communication module, such as a WIFI module, and transmits the upgrade firmware to a chip in the device, so as to complete the upgrade of the chip.
In the prior art, when the device integrating a plurality of chips upgrades a plurality of chips at the same time, the upgrading sequence is not customized, and the problem that after one chip is upgraded, the next chip is affected is solved.
In general, in an electronic device, a chip closer to a communication module may be referred to as a near-end chip, and a chip farther from the communication module may be referred to as a far-end chip. In the upgrading process, if the near-end chip is upgraded first and then the far-end chip is upgraded, there may be a problem that if the near-end chip has an error in the upgrading process, the remaining chips cannot be upgraded normally.
Assuming that 3 chips are arranged in some electronic equipment, namely a chip 1, a chip 2 and a chip 3, and the chip 1 is connected with the communication module, the chip 2 is connected with the chip 1, and the chip 3 is connected with the chip 2, then the chip 1 can be called as a near-end chip, and the chip 2 and the chip 3 are far-end chips. If the near-end chip 1 is upgraded firstly, then the far-end chip 2 and the far-end chip 3 are upgraded, if the program of the chip 1 is wrong in the upgrading process, the chip 1 cannot normally receive and process the upgrading firmware data sent by the communication module, and then the chip 2 and the chip 3 cannot be upgraded normally.
In view of the above problems of the electronic device integrated with multiple chips in the process of OTA upgrading, the application provides an OTA upgrading method, aiming at the electronic device integrated with multiple chips, the upgrading sequence of the chips is preset before the OTA upgrading, and each chip can enter a corresponding chip mode according to the state of the chip in the upgrading process, so that the problem that if an error exists in the upgrading process of one chip, the next chip cannot be normally upgraded is avoided.
The OTA upgrading method provided by the embodiment of the invention is applied to an OTA upgrading system, and the OTA upgrading system will be described first.
Referring to fig. 1, a schematic structural diagram of an OTA upgrade system provided in an embodiment of the present application, as shown in fig. 1, the OTA upgrade system may include: the electronic device 101 to be upgraded and the communication module 102, wherein the electronic device 101 to be upgraded may include a plurality of chips 103, and a first chip 104 of the plurality of chips is directly connected with the communication module 102. It should be noted that the number of chips in the plurality of chips 103 in fig. 1 is merely illustrative, and the embodiment of the present application is not limited in particular.
For example, in a scenario of upgrading a chip in an electronic device using OTA, a data interaction process between the electronic device 101, the communication module 102, and the server may be: the user operates the electronic device 101 to initiate an upgrade request instruction, the electronic device 101 sends the upgrade request instruction to the server, the server sends the upgrade instruction to the communication module 102 after receiving the upgrade instruction, the communication module 102 downloads upgrade firmware from the server, the communication module 102 sends the upgrade firmware downloaded from the server to the plurality of chips 103, the plurality of chips 103 complete the upgrade of each chip after receiving the upgrade firmware, the plurality of chips 103 return an upgrade completion response to the communication module 102 after the chip upgrade is completed, the communication module 102 returns an upgrade completion response to the server after receiving the upgrade completion response, the server returns an upgrade completion response to the electronic device 101 after receiving the upgrade completion response, and the electronic device 101 informs the user of the upgrade completion response.
Specifically, the interaction between the electronic device 101 and the server, and the interaction between the communication module 102 and the server are performed through a wireless network, where the wireless network refers to a network implemented by using a wireless communication technology, and according to a network coverage, a transmission rate, and a usage, the wireless network may be divided into a wireless wide area network (Wireless Wide Area Network, WWAN), a wireless metropolitan area network (Wireless Metropolitan Area Network, WMAN), a wireless local area network (Wireless Local Area Network, WLAN), a wireless personal area network (Wireless Personal Area Network, WPAN), a wireless body area network (Wireless Body Area Network, WBAN), and the like, or any combination thereof, where each wireless network is used to provide a communication link between the electronic device 101 and the server, and between the communication module 102 and the server.
In some embodiments, the server may be implemented on a cloud platform, which may include, by way of example only, a private cloud, public cloud, hybrid cloud, community cloud (community cloud), distributed cloud, inter-cloud (inter-cloud), multi-cloud (multi-cloud), or the like, or any combination thereof.
For simplicity of description, in the following method embodiments, when referring to the electronic device 101, description is made using "device", when referring to the communication module 102, description is made using "communication module", when referring to the plurality of chips 103, description is made using "plurality of chips", and description is made using "first chip" when referring to the first chip 104.
After describing the OTA upgrading system provided in the embodiments of the present application, the following embodiments will describe in detail the OTA upgrading method provided in the embodiments of the present application with reference to the accompanying drawings.
Fig. 2 is a flow chart of an OTA upgrading method provided in an embodiment of the present application, and as shown in fig. 2, the OTA upgrading method includes:
step S201, the communication module receives the upgrade firmware sent by the server, and determines the current target chip to be upgraded according to the upgrade sequence of each chip.
Specifically, after the communication module receives the upgrade firmware data of each chip sent by the server, the upgrade order of each chip needs to be obtained from the server, and the current chip to be upgraded is determined according to the upgrade order of each chip, where the current chip to be upgraded is the first chip in the upgrade order of each chip, and the current chip to be upgraded can be called as the target chip. The communication module may be a communication module with a wireless communication function, for example, a WIFI module, so that the electronic device may be connected to a wireless network. The upgrading sequence of each chip is determined according to the arrangement sequence of each chip in the plurality of chips.
For example, please continue to refer to fig. 1, assume that a plurality of chips include three chips, chip 1, chip 2 and chip 3, wherein chip 1 is directly connected with the communication module, chip 2 is connected with chip 1, and chip 3 is connected with chip 2, that is, the communication module, chip 1, chip 2 and chip 3 are in a connection relationship in sequence, according to the arrangement sequence of each chip and the principle of determining the upgrade priority, the chip far from the communication module is upgraded first, the upgrade sequence of each chip can be obtained as upgrade chip 3 first, upgrade chip 2 last, and upgrade chip 1 last, since the three chips have not been upgraded before, and the upgrade sequence of chip 3 is first, therefore, chip 3 is determined as the chip to be upgraded currently, that is, the target chip. Referring to fig. 3, a schematic structural diagram of another OTA upgrading system provided in the embodiment of the present application is shown in fig. 3, and since the chip 2 and the chip 3 are not connected in sequence, there is no specific limitation on the upgrading sequence of the chip 2 and the chip 3, and the chip 2 may be upgraded first, or the chip 3 may be upgraded first, that is, the target chip may be the chip 2 or the chip 3.
In step S202, the communication module sends an upgrade start instruction to the first chip.
Specifically, after receiving the upgrade firmware sent by the server and determining the target chip, the communication module sends an instruction to start the upgrade to the first chip, where the first chip may refer to a chip connected to the communication module, and referring to fig. 1 and fig. 3, in fig. 1 and fig. 3, since the chip 1 is connected to the communication module, in fig. 1 and fig. 3, the first chip is the chip 1.
Further, the instruction for starting the upgrade, which is sent by the communication module to the first chip, includes an identifier of the target chip, where the identifier of the target chip may be model information of the chip to be upgraded, and is used to characterize which chip of the multiple chips is upgraded in the current upgrade. Referring to fig. 1, in fig. 1, since the target chip is chip 3, that is, the chip to be upgraded is chip 3, the instruction for starting the upgrade sent by the communication module to the first chip, that is, chip 1, includes the identifier of the target chip, that is, the model information of chip 3.
In step S203, starting with the first chip, each chip sequentially sends an upgrade starting instruction to the following chip, if the chip receiving the upgrade starting instruction is the target chip, the target chip adjusts its current chip mode to be an upgrade mode, and other chips except the target chip adjust their respective chip modes to be a transparent mode or a sleep mode.
Specifically, after receiving an upgrade starting instruction sent by the communication module, the first chip starts with the first chip, and after each chip receives the upgrade starting instruction, the upgrade starting instruction is sent to a subsequent chip, wherein the subsequent chip can refer to a chip connected with a certain chip and subsequent to the subsequent chip. For example, referring to fig. 1, the chip 1 is a first chip, the chip 1 is a subsequent chip of the chip 1 is a chip 2, the chip 2 is a subsequent chip of the chip 3, and the chip 1 sends the start-up instruction to the chip 2 after receiving the start-up instruction sent by the communication module, and the chip 2 sends the start-up instruction to the chip 3 after receiving the start-up instruction sent by the chip 1.
Further, if the chip receiving the instruction to start upgrading is the target chip, the target chip adjusts its current chip mode to be the upgrading mode, and other chips except the target chip adjust their respective chip modes to be the transparent mode or the sleep mode because the target chip is the chip to be upgraded at this time. With continued reference to fig. 1, if the target chip for this upgrade is chip 3, chip 3 enters an upgrade mode, and chip 1 and chip 2 adjust their respective chip modes to either a transparent mode or a sleep mode.
In step S204, the communication module sends the upgrade firmware to the first chip.
Specifically, an upgrade starting instruction is received at each of the plurality of chips, and after an upgrade preparation completion instruction returned by each chip is received by the communication module, the communication module sends upgrade firmware data to the first chip. For example, with continued reference to fig. 1, since chip 1 is the first chip, the communication module sends upgrade firmware data to chip 1.
Step S205, starting with the first chip, each chip sequentially receives the upgrade firmware, and executes upgrade operation or data transmission according to the current respective chip mode.
Specifically, starting with the first chip, each chip sequentially receives the upgrade firmware data, and executes upgrade operation or data transparent transmission for the upgrade firmware data according to the current chip mode.
For example, please continue to refer to fig. 1, for example, after receiving the upgrade firmware sent by the communication module, if the chip 1 finds that its current chip mode is data transparent, the upgrade firmware is transparent to the chip 2, the chip 2 finds that its current chip mode is also data transparent, after continuing transparent, the upgrade firmware is received by the chip 3, after receiving the upgrade firmware, the chip 3 finds that its current chip mode is upgrade mode, and then uses the upgrade firmware to execute upgrade operation to complete upgrade.
For another example, after receiving the upgrade firmware sent by the communication module, the chip 1 transparently transmits the upgrade firmware to the chip 2 if finding that the current chip mode is data transparent, and the chip 2 finds that the current chip mode is the upgrade mode, and then uses the upgrade firmware to execute the upgrade operation to complete the upgrade.
In a specific embodiment, the steps S201 to S205 may be performed repeatedly until each of the plurality of chips completes the upgrade.
In summary, an embodiment of the present application provides an OTA upgrading method, including: the communication module receives the upgrade firmware sent by the server, and determines a current target chip to be upgraded according to the upgrade sequence of each chip, wherein the upgrade sequence of each chip is determined according to the arrangement sequence of each chip; the communication module sends an upgrade starting instruction to the first chip, wherein the upgrade starting instruction comprises the identification of the target chip; starting from a first chip, each chip sequentially sends an upgrade starting instruction to a subsequent chip, if the chip which receives the upgrade starting instruction is a target chip, the target chip adjusts the current chip mode to be an upgrade mode, and other chips outside the target chip adjust the respective chip modes to be a transparent transmission mode or a dormant mode; the communication module sends the upgrade firmware to the first chip; starting from the first chip, each chip sequentially receives the upgrade firmware, and executes upgrade operation or data transparent transmission according to the current respective chip mode. In the step, before upgrading, the upgrading sequence of each chip is preset according to the arrangement sequence of each chip, in the upgrading process, the chips can be upgraded according to the preset upgrading sequence, in the upgrading process, each chip can enter a corresponding chip mode according to the state of the chip, the problem that in the multi-chip upgrading process, after errors occur in the upgrading process, the chips on the other sides can be influenced, and then the equipment after upgrading is abnormal is caused, the reliability of OTA upgrading of the electronic equipment is improved, and the accuracy and efficiency of firmware updating of the electronic equipment are improved.
Optionally, the other chips than the target chip adjust their respective chip modes to a transparent mode or a sleep mode, including:
if the upgrade status of the second chip in the other chips is upgraded, the second chip adjusts the chip mode thereof to a sleep mode, wherein the second chip is any one of the other chips.
Specifically, any one of the other chips except the target chip adjusts its chip mode to the sleep mode by judging its own upgrade status if it is upgraded.
Optionally, the other chips than the target chip adjust their respective chip modes to a transparent transmission mode or a sleep mode, and further include:
and if the upgrading state of the third chip in the other chips is not upgraded, the third chip adjusts the chip mode of the third chip to be a transparent transmission mode, wherein the third chip is any one of the other chips.
Specifically, any one of the other chips except the target chip adjusts the chip mode to be a transparent transmission mode by judging the upgrading state of the chip if the chip is not upgraded.
With continued reference to fig. 1, if the target chip to be upgraded is chip 3, chip 3 enters the upgrade mode, and since chip 1 and chip 2 have not yet been upgraded, chip 1 and chip 2 enter the pass-through mode. If it is assumed that the chip 3 has been upgraded, the next time the upgrade is entered, the chip 3 adjusts its chip mode to the sleep mode after receiving the upgrade start instruction, and since the target chip of the upgrade is the chip 2, the chip 2 adjusts its chip mode to the upgrade mode, and since the chip 1 is not upgraded, the chip 1 adjusts its chip mode to the transparent mode.
The transparent transmission mode may mean that after a certain chip receives an instruction or data sent by a communication module or a preceding chip, the instruction or data is not processed and is only forwarded to a following chip, and the sleep mode may mean that the certain chip is in a low power consumption mode and does not respond or receive any instruction or data.
On the basis of pre-determining the chip upgrading sequence, other chips except the target chip adjust respective chip modes into a transparent transmission mode or a dormant mode according to the state of the chip, so that the problem that one side chip can influence the upgrading of other side chips after errors occur in the upgrading process in the multi-chip upgrading process can be avoided, and the reliability of OTA upgrading of equipment is improved.
Furthermore, when each chip is in the corresponding chip mode, if an abnormality occurs in the upgrading process, such as power failure, wire breakage or network breakage, etc., as each chip has a corresponding memory mark when the abnormality occurs, when various abnormal conditions are recovered to normal, each chip enters a state before the abnormality occurs after reading the corresponding memory mark, thereby further improving the reliability, accuracy and efficiency of OTA upgrading of the equipment.
Referring to fig. 4, a flowchart of another OTA upgrading method provided in the embodiment of the present application is shown in fig. 4, and in the step S305, an upgrading operation or data transparent transmission is performed according to a current respective chip mode, including:
in step S401, the target chip performs an upgrade operation in an upgrade mode using the upgrade firmware.
Specifically, the target chip is the chip to be upgraded at this time, so after receiving the instruction to start upgrading, the target chip adjusts the chip mode to be an upgrading mode, and then, after receiving the upgrading firmware sent by the communication module, the target chip executes the upgrading operation in the upgrading mode to finish the upgrading.
Step S402, each chip in the transparent transmission mode sends the updated firmware to the following chips connected with the updated firmware.
Specifically, since each chip in the transparent mode is not the chip to be upgraded of the current upgrade, each chip in the transparent mode only transmits the upgrade firmware to the subsequent chip connected with the chip, and each subsequent chip selects whether to upgrade or continue transmitting the upgrade firmware to the subsequent chip connected with the chip according to the own chip mode.
Step S403, if the target chip finishes the upgrade operation, the target chip exits the upgrade mode and sends an upgrade completion response to the other chips outside the target chip.
Specifically, if the target chip completes the upgrade operation, the target chip exits the upgrade mode, returns to the initial state, and sends a response to the completion of the upgrade to the other chips.
In step S404, after receiving the upgrade completion response, the third chip in the other chips adjusts the current chip mode to the initial state.
When other chips except the target chip receive the response of upgrading completion sent by the target chip, the current chip mode is exited, the respective chip modes are adjusted to be in an initial state, and the process of upgrading the target chip is completed.
Referring to fig. 1, if the current target chip to be upgraded is the chip 3, after the chip 3 completes the upgrade operation, the upgrade mode is exited, and the response of the upgrade completion is sent to the chip 1 and the chip 2, after the response of the upgrade completion sent by the chip 3 is received by the chip 1 and the chip 2, the respective chip modes are adjusted from the transparent mode to the initial state, and the process of upgrading the chip 3 is completed.
Fig. 5 is a flow chart of another OTA upgrading method provided in the embodiment of the present application, as shown in fig. 5, in the above step S201, the communication module receives the upgraded firmware sent by the server, and includes:
In step S501, the communication module sends a ready-to-upgrade instruction to the first chip.
Step S502, the first chip determines whether each chip meets a preset upgrade condition according to the upgrade preparation instruction, and if yes, sends an upgrade preparation completion response to the communication module.
Specifically, after receiving an instruction of preparing for upgrading sent by the communication module, the first chip needs to determine whether each chip in the plurality of chips meets a preset upgrading condition, if each chip meets the preset upgrading condition, the first chip sends an upgrading preparation completion response to the communication module so as to inform the communication module that each chip is ready for upgrading, and upgrading operation can be performed.
The preset upgrading condition is met, that is, the equipment body is in a non-action state, that is, the upgrading condition is met, and further, the plurality of chips judge whether the current equipment body is in an action state or not by acquiring the action state of the current equipment body, so that whether the current equipment body can be upgraded or not is judged. If the current equipment body is judged to be in a non-action state, a preset upgrading condition is met, and an upgrading preparation completion response can be sent to the communication module.
In step S503, the communication module reads the upgrade firmware from the server according to the upgrade preparation completion response.
Specifically, after receiving the upgrade preparation completion response sent by the first chip, the communication module reads the upgrade firmware from the server so as to send the upgrade firmware to the plurality of chips to complete the upgrade operation.
Optionally, in step S201, before determining the target chip to be upgraded currently according to the upgrade order of the chips, the method further includes:
the upgrade order of each chip is read from the server. The upgrading sequence of each chip is obtained by the user setting on the server in advance according to the arrangement sequence of each chip.
With continued reference to fig. 1, the connection relationship between the plurality of chips and the communication module and the arrangement sequence of the chips may determine that the order of upgrading the plurality of chips is: the following three embodiments will describe specific upgrading processes of the chip 3, the chip 2 and the chip 1, namely, upgrade the far-end chip 3, upgrade the far-end chip 2 and upgrade the near-end chip 1.
Fig. 6 is a flow chart of another OTA upgrading method provided in the embodiment of the present application, and as shown in fig. 6, an upgrading process of the chip 3 includes:
In step S601, the user operates the device to initiate an upgrade.
In step S602, the device sends a ready-to-upgrade instruction to the server.
In step S603, the server sends a ready-to-upgrade instruction to the communication module.
In step S604, the communication module sends a ready-to-upgrade instruction to the chip 1.
In step S605, the chip 1 determines whether the current chips satisfy the preset upgrade conditions.
As shown in fig. 6, since the chip 1 is connected to the communication module, the chip 1 may be referred to as the first chip in the step S502, and after receiving the instruction for preparing for upgrading sent by the communication module, the chip 1 needs to determine whether each of the current chips meets the preset upgrading condition.
In step S606, if the plurality of chips meet the upgrade condition, the chip 1 returns an upgrade preparation completion response to the communication module.
After judging that each chip meets the preset upgrading conditions, the chip 1 serving as the first chip returns an upgrading preparation completion response to the communication module.
In step S607, the communication module downloads the upgrade firmware.
As described in the foregoing step S503, after receiving the upgrade preparation completion response returned from the chip 1 as the first chip, the communication module downloads the upgrade firmware from the server so as to transmit the upgrade firmware data to the plurality of chips subsequently.
In step S608, the communication module obtains the upgrade order of each chip, and determines the current target chip to be upgraded according to the upgrade order of each chip.
The communication module obtains the upgrading sequence of each chip from the server, wherein the upgrading sequence of each chip is preset on the server by a user according to the arrangement sequence of each chip, and the communication module only needs to be read from the server in the upgrading process.
As described in the foregoing step S201, the communication module receives the upgrade firmware sent by the server, and after obtaining the upgrade order of each chip, the communication module needs to determine the current target chip to be upgraded, where the current target chip to be upgraded is the first chip in the upgrade order, and referring to fig. 6, the upgrade order of each chip can be determined from the arrangement order of the chip 1, the chip 2, and the chip 3: chip 3, chip 2, chip 1, thus the target chip of the current upgrade is chip 3.
In step S609, the communication module sends an upgrade start instruction to the chip 1, where the upgrade start instruction includes model information of the chip 3.
Since the chip 1 is the first chip, as described in the foregoing step S202, the communication module sends an upgrade starting instruction to the first chip, that is, the communication module sends the upgrade starting instruction to the chip 1, and since the target chip to be upgraded currently is the chip 3, the upgrade starting instruction includes the model information of the chip 3, and after the chip 1, the chip 2 and the chip 3 receive the upgrade starting instruction, the chip to be upgraded currently is known to be the chip 3.
In step S610, the chip 1 receives the upgrade start instruction sent by the communication module and sends the upgrade start instruction to the chip 2.
In step S611, the chip 2 receives the upgrade start instruction sent by the chip 1, and sends the upgrade start instruction to the chip 3.
In step S612, the chip 3 receives the upgrade start instruction sent by the chip 2, and returns an upgrade start completion response to the chip 2.
In step S613, the chip 3 enters an upgrade mode.
After the step S610 and the step S611, the start-up instruction sent by the communication module is sent to the chip 2 by the chip 1, and then sent to the chip 3 by the chip 2, and after the chip 3 receives the start-up instruction, the chip 3 includes the model information of the chip 3, so in this process, the chip 1, the chip 2 and the chip 3 can determine that the target chip to be upgraded is the chip 3, and therefore, as described in the step S203, the chip 3 first adjusts the chip mode to be the upgrade mode.
In step S614, the chip 2 receives the upgrade start completion response returned from the chip 3 and returns the upgrade start completion response to the chip 1.
After receiving the upgrade starting completion response returned by the chip 3, the chip 2 further returns the upgrade starting completion response to the chip 1.
In step S615, the chip 2 enters a data transparent mode.
After returning the upgrade start completion response to the chip 1, since the chip 2 has already learned from the upgrade start instruction that the target chip to be upgraded is the chip 3, the chip 2 adjusts its chip mode to the transmission mode as described in the foregoing step S203.
In step S616, the chip 1 receives the upgrade start completion response returned by the chip 2, and returns the upgrade start completion response to the communication module.
After receiving the upgrade starting completion response returned by the chip 2, the chip 1 further returns the upgrade starting completion response to the communication module.
In step S617, the chip 1 enters a data transmission mode.
After the chip 1 returns the upgrade start completion response to the communication module, since the chip 1 has already learned from the upgrade start instruction that the target chip to be upgraded is the chip 3, the chip 1 also adjusts its chip mode to the transparent mode as described in the foregoing step S203.
In step S618, the communication module sends the upgrade firmware data to the chip 1.
After the communication module receives the response of starting the upgrade from the plurality of chips, as described in the aforementioned step S204, the communication module sends the upgrade firmware data to the first chip, i.e. the chip 1.
In step S619, the chip 1 receives the upgrade firmware data and transmits the upgrade firmware data to the chip 2.
As described in the foregoing step S402, since the chip mode of the current chip 1 is the transparent mode, the chip 1 transmits the received upgrade firmware data to the chip 2.
In step S620, the chip 2 receives the upgrade firmware data and transmits it to the chip 3.
Similarly, as described in the foregoing step S402, since the chip mode of the current chip 2 is also the transparent transmission mode, the chip 2 transmits the received upgrade firmware data to the chip 3.
In step S621, the chip 3 receives the firmware upgrade data to upgrade the firmware.
As described in the foregoing step S401, after receiving the upgrade firmware data, the chip 3 performs the firmware upgrade in the upgrade mode using the upgrade firmware data.
In step S622, the chip 3 is upgraded, and exits the upgrade mode to return to the initial state.
After the chip 3 is upgraded, the upgrade mode is exited and the chip returns to the initial state as described in the previous step S403.
In step S623, the chip 3 returns an upgrade completion response to the chip 2.
In step S624, the chip 2 receives the upgrade completion response returned by the chip 3 and returns the upgrade completion response to the chip 1.
After the upgrade of the chip 3 is completed, the upgrade mode is exited and an upgrade completion response is sent to the chip 1 and the chip 2 as described in the previous step S403.
In step S625, the chip 2 exits the data transparent mode and returns to the initial state.
As described in the aforementioned step S404, after receiving the upgrade completion response of the chip 3, the chip 2 exits the transparent transmission mode and adjusts the chip state to the initial state.
In step S626, the chip 1 receives the upgrade completion response returned by the chip 2, and returns the upgrade completion response to the communication module.
After receiving the upgrade completion response returned by the chip 2, the chip 1 needs to send the upgrade completion response to the communication module so that the communication module enters the next operation process.
In step S627, the chip 1 exits the data transparent mode and returns to the initial state.
Continuing to refer to the previous step S404, after receiving the upgrade completion response sent by the chip 2, the chip 1 exits the transparent transmission mode and adjusts the chip state to the initial state.
After the upgrade of the chip 3 is completed, the chip 2 is upgraded, please refer to fig. 7, which is a flow chart of another OTA upgrade method provided in the embodiment of the present application, and as shown in fig. 7, the upgrade process of the chip 2 includes:
in step S701, the communication module sends an upgrade start instruction to the chip 1, where the upgrade start instruction includes model information of the chip 2.
After the chip 3 is upgraded, the communication module continues to send an instruction for starting the upgrade to a plurality of chips to upgrade the next chip, and the current target chip to be upgraded is the chip 2, so that the instruction for starting the upgrade comprises the model information of the chip 2, and after the chip 1, the chip 2 and the chip 3 receive the instruction for starting the upgrade, the current chip to be upgraded can be known to be the chip 2.
In step S702, the chip 1 receives the upgrade start instruction sent by the communication module and sends the upgrade start instruction to the chip 2.
In step S703, the chip 2 receives the upgrade start instruction sent by the chip 1 and sends the upgrade start instruction to the chip 3.
In step S704, the chip 3 receives the upgrade start instruction sent by the chip 2, and returns an upgrade start completion response to the chip 2.
In step S705, the chip 3 enters the sleep mode.
After the step S702 and the step S703, the start-up instruction sent by the communication module is sent to the chip 2 by the chip 1, and then sent to the chip 3 by the chip 2, and after the chip 3 receives the start-up instruction, the chip 1, the chip 2 and the chip 3 can determine that the target chip to be upgraded is the chip 2 in the process because the start-up instruction includes the model information of the chip 2, and therefore, as described in the step S203, and the chip 3 is upgraded, the chip 3 first adjusts the chip mode to the sleep mode.
In step S706, the chip 2 receives the upgrade start completion response returned by the chip 3, and returns the upgrade start completion response to the chip 1.
In step S707, the chip 2 enters an upgrade mode.
After returning the upgrade start completion response to the chip 1, since the chip 2 has already learned from the upgrade start instruction that the target chip to be upgraded is the chip 2, the chip 2 adjusts its chip mode to the upgrade mode as described in the foregoing step S203.
In step S708, the chip 1 receives the upgrade start completion response returned by the chip 2, and returns the upgrade start completion response to the communication module.
In step S709, the chip 1 enters a data transparent mode.
After returning the upgrade start completion response to the communication module, since the chip 1 has already learned from the upgrade start instruction that the target chip to be upgraded is the chip 2, the chip 1 adjusts its chip mode to the transparent mode as described in the foregoing step S203.
In step S710, the communication module sends the upgrade firmware data to the chip 1.
In step S711, the chip 1 receives the upgrade firmware data and transmits it to the chip 2.
As described in the foregoing step S402, since the chip mode of the current chip 1 is the transparent mode, the chip 1 transmits the received upgrade firmware data to the chip 2.
In step S712, the chip 2 receives the firmware upgrade data to upgrade the firmware.
As described in the foregoing step S401, after receiving the upgrade firmware data, the chip 2 performs the firmware upgrade in the upgrade mode using the upgrade firmware data.
In step S713, the chip 2 is upgraded, and exits the upgrade mode to return to the initial state.
After the chip 2 is upgraded, the upgrade mode is exited and the chip returns to the initial state as described in the previous step S403.
In step S714, the chip 2 returns an upgrade completion response to the chip 3 and the chip 1, respectively.
After the upgrade of the chip 2 is completed, the upgrade mode is exited and an upgrade completion response is sent to the chips 1 and 3 as described in the previous step S403.
In step S715, the chip 3 receives the upgrade completion response sent by the chip 2, exits the sleep mode, and returns to the initial state.
As described in the aforementioned step S404, after receiving the upgrade completion response sent by the chip 2, the chip 3 exits the sleep mode to adjust the chip state to the initial state.
In step S716, the chip 1 receives the upgrade completion response sent by the chip 2, and returns the upgrade completion response to the communication module.
In step S717, the chip 1 exits the data transmission mode and returns to the initial state.
Continuing to refer to the previous step S404, after receiving the upgrade completion response sent by the chip 2, the chip 1 exits the transparent transmission mode and adjusts the chip state to the initial state.
After the upgrade of the chip 2 is completed, the chip 1 is upgraded, please refer to fig. 8, which is a flow chart of another OTA upgrade method provided in the embodiment of the present application, and as shown in fig. 8, the upgrade process of the chip 1 includes:
in step S801, the communication module sends an upgrade start instruction, where the upgrade start instruction includes model information of the chip 1.
After the chip 3 and the chip 2 are upgraded, the communication module continues to send an instruction for starting upgrading to the plurality of chips to upgrade the next chip, and the current chip to be upgraded is the chip 1, so that the instruction for starting upgrading comprises the model information of the chip 1, and after the chip 1, the chip 2 and the chip 3 receive the instruction for starting upgrading, the current chip to be upgraded can be known to be the chip 1.
In step S802, the chip 1 receives the upgrade starting instruction sent by the communication module and sends the upgrade starting instruction to the chip 2.
In step S803, the chip 2 receives the upgrade start instruction sent by the chip 1 and sends the upgrade start instruction to the chip 3.
In step S804, the chip 3 receives the upgrade start instruction sent by the chip 2, and returns an upgrade start completion response to the chip 2.
In step S805, the chip 3 enters the sleep mode.
After the step S802 and the step S803, the start-up instruction sent by the communication module is sent to the chip 2 by the chip 1, and then sent to the chip 3 by the chip 2, and after the chip 3 receives the start-up instruction, the chip 1, the chip 2 and the chip 3 can determine that the target chip to be upgraded is the chip 1 in the process because the start-up instruction includes the model information of the chip 1, and therefore, as described in the step S203, and the chip 3 is upgraded, the chip 3 first adjusts the chip mode to the sleep mode.
In step S806, the chip 2 receives the upgrade start completion response returned from the chip 3 and returns the upgrade start completion response to the chip 1.
In step S807, the chip 2 enters the sleep mode.
Similarly, as in step S805 described above, the chip 2 also enters the sleep mode.
In step S808, the chip 1 receives the upgrade start completion response returned by the chip 2, and returns the upgrade start completion response to the communication module.
In step S809, the chip 1 enters an upgrade mode.
After returning the upgrade start completion response to the communication module, since the chip 1 has already learned from the upgrade start instruction that the target chip to be upgraded is the chip 1, the chip 1 adjusts its chip mode to the upgrade mode as described in the foregoing step S203.
In step S810, the communication module sends the upgrade firmware data to the chip 1.
In step S811, the chip 1 receives the firmware upgrade data, and performs firmware upgrade.
As described in the foregoing step S401, after receiving the upgrade firmware data, the chip 1 performs the firmware upgrade in the upgrade mode using the upgrade firmware data.
In step S812, the chip 1 is upgraded, and exits the upgrade mode to return to the initial state.
After the upgrade of the chip 1 is completed, the upgrade mode is exited and the chip returns to the initial state as described in the previous step S403. And sends an upgrade completion response to the chip 2 and the communication module.
In step S813, the chip 1 returns an upgrade completion response to the chip 2 and the communication module, respectively.
After the chip 1 is upgraded, the upgrade mode is exited, and an upgrade completion response is sent to the chip 2 and the communication module.
In step S814, the chip 2 receives the upgrade completion response returned by the chip 1, and returns the upgrade completion response to the chip 3.
In step S815, the chip 2 exits the sleep mode and returns to the initial state.
Continuing to step S404, after receiving the upgrade completion response sent by the chip 1, the chip 2 exits the sleep mode and adjusts the chip state to the initial state.
In step S816, the chip 3 receives the upgrade completion response returned by the chip 2, exits the sleep mode, and returns to the initial state.
Continuing to step S404, after receiving the upgrade completion response sent by the chip 2, the chip 3 exits the sleep mode and adjusts the chip state to the initial state.
In step S817, the communication module receives the upgrade completion response returned by the chip 1, and returns the upgrade completion response to the server.
Step S818, the server receives the upgrade completion response returned by the communication module and returns the upgrade completion response to the device.
And step S819, the device receives the upgrade completion response returned by the server and informs the user of the upgrade completion.
Thus far, the entire upgrading process of the chip 1, the chip 2 and the chip 3 is completed among the plurality of chips as shown in fig. 1.
Embodiments of the present application also provide a computer readable storage medium having a computer program stored thereon, which when executed by a processor performs the steps in the above-described embodiments of the OTA upgrading method.
In particular, the storage medium can be a general-purpose storage medium, such as a removable disk, a hard disk, or the like, and the computer program on the storage medium can execute the above-described OTA upgrading method embodiment when executed.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.

Claims (10)

1. The method is characterized by being applied to an over-the-air technology upgrading system, wherein the upgrading system comprises electronic equipment to be upgraded and a communication module, the electronic equipment comprises a plurality of chips, and a first chip in each chip is connected with the communication module, and the method comprises the following steps:
the communication module receives the upgrade firmware sent by the server, and determines a current target chip to be upgraded according to the upgrade sequence of each chip, wherein the upgrade sequence of each chip is determined according to the arrangement sequence of each chip;
the communication module sends an upgrade starting instruction to the first chip, wherein the upgrade starting instruction comprises the identification of the target chip;
starting with the first chip, each chip sequentially sends the start-upgrading instruction to the following chips, if the chip receiving the start-upgrading instruction is the target chip, the target chip adjusts the current chip mode to be an upgrading mode, and other chips except the target chip adjust the respective chip modes to be a transparent mode or a dormant mode;
the communication module sends the upgrade firmware to the first chip;
And starting from the first chip, each chip sequentially receives the upgrade firmware and executes upgrade operation or data transparent transmission according to the current respective chip mode.
2. The method of claim 1, wherein the other chips than the target chip adjust their respective chip modes to a transparent mode or a sleep mode, comprising:
and if the upgrading state of the second chip in the other chips is upgraded, the second chip adjusts the chip mode of the second chip to be a dormant mode, wherein the second chip is any one of the other chips.
3. The method of claim 1, wherein the other chips than the target chip adjust their respective chip modes to a transparent mode or a sleep mode, comprising:
and if the upgrading state of the third chip in the other chips is not upgraded, the third chip adjusts the chip mode of the third chip to be a transparent transmission mode, wherein the third chip is any one of the other chips.
4. The method of claim 1, wherein each of the chips performs an upgrade operation or data pass-through according to a current respective chip mode, comprising:
The target chip uses the upgrade firmware to execute upgrade operation in the upgrade mode;
and transmitting the updated firmware to the following chips connected with the chips in the transparent transmission mode.
5. The method according to claim 4, wherein the method further comprises:
if the target chip finishes the upgrading operation, the target chip exits the upgrading mode and sends an upgrading completion response to other chips except the target chip.
6. The method of claim 5, wherein the method further comprises:
and after receiving the upgrade completion response, a third chip in the other chips adjusts the current chip mode to an initial state.
7. The method according to any one of claims 1-6, wherein the communication module receiving the upgrade firmware sent by the server includes:
the communication module sends a preparation upgrading instruction to the first chip;
the first chip determines whether each chip meets preset upgrading conditions according to the upgrading preparation instruction, and if yes, sends an upgrading preparation completion response to the communication module;
And the communication module reads the upgrade firmware from the server according to the upgrade preparation completion response.
8. The method according to any one of claims 1-6, wherein before determining the current target chip to be upgraded according to the upgrade order of the chips, the method further comprises:
and reading the upgrading sequence of each chip from the server, wherein the upgrading sequence of each chip is obtained by the fact that a user sets the upgrading sequence on the server in advance according to the arrangement sequence of each chip.
9. An over-the-air technology upgrade system, said system comprising:
the electronic equipment to be upgraded and the communication module, wherein the electronic equipment comprises a plurality of chips, a first chip in each chip is connected with the communication module, and the electronic equipment and each chip in the electronic equipment respectively execute the steps of the air-download technology upgrading method as claimed in any one of claims 1 to 8.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the over-the-air technology upgrade method according to any one of claims 1-8.
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